JPH0612365A - Dma control system - Google Patents

Abstract

PURPOSE:To reduce the delay of an interrupt process which needs to be carried out urgently while performing high-speed data transfer by DMA continuous transfer. CONSTITUTION:A CPU 1 enables a DMA request controller 4 to sends a DMA request successively through a line 13b right before DMA transfer is indicated. The DMA transfer is indicated and the DMA continuous transfer from a general interface controller(SCC) 3 for small-sized machine to a main storage device (MS) 6 is started. If an interruption is initiated from a line controller (LC) 7 to an interruption line 18 during the DMA transfer, the DMA request controller 4 periodically inhibits the DMA request passed through a line 13a and the CPU 1 operates intermittently to process the interrupt.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA control system, and more particularly to a DMA control system which avoids a delay in interrupt processing from an input / output device during continuous DMA execution.

[0002]

2. Description of the Related Art In a system in which an input / output device (IO) and a main storage device (MS) are controlled by a CPU, a so-called DMA continuous transfer system is adopted in order to speed up data transfer.

Usually, such a system is composed of a common bus, and DMA and PIO (program input / output) are performed on the common bus. Therefore, during continuous execution of DMA, the CPU
However, the bus could not be used, and urgent processing such as interrupt processing and failure processing could not be immediately executed, and there was a case where the specified time was waited for.

[0004]

To cope with this, various DMA control methods have been proposed in the past. For example, in the technique disclosed in Japanese Patent Laid-Open No. 63-14264, a plurality of DMA devices are coupled to a system bus and each DM device is connected.
In a system in which A is given a priority to enable DMA processing, each DMA device is provided with a programmable timer, and each DMA request output to the bus is limited by the set time of the programmable timer to allow bus access of each DMA device. The bus load can be optimized without being occupied by one.

Further, in the technique disclosed in Japanese Patent Laid-Open No. 62-231367, a DMA dedicated bus is provided between the memory and the interface in the data transfer between the memory and the interface coupled by the system bus, and the memory and the interface are connected. This is a technology that enables data transfer via a DMA dedicated bus and allows the system bus to be used even during DMA data transfer.

However, the former one is regularly DMed.
Since A is interrupted, there is a problem that the throughput of the DMA continuous transfer is lowered, and the latter one has a problem that the circuit configuration becomes complicated because it is necessary to support the 2-port input / output memory and IO.

SUMMARY OF THE INVENTION An object of the present invention is to provide a DMA control system in which high-speed data transfer is performed by continuous DMA transfer and the delay of interrupt processing requiring urgent processing is reduced.

[0008]

To achieve the above object, in the present invention, in a control system for transferring data between an input / output device and a main storage device, a data transfer between the input / output device and the main storage device is performed. A DMA control means for continuously controlling the transfer of data by means of: and a means for alternately switching between the operation by the DMA control means and the program input / output operation in response to an interrupt from the input / output device during the data transfer by the control means. It is characterized by having.

[0009]

The CPU makes the DMA request control device ready to continuously issue DMA requests immediately before the DMA transfer instruction. DM to main memory when DMA transfer is instructed
A continuous transfer starts. When an interrupt occurs during the DMA transfer, the DMA request control device periodically suppresses the DMA request, and the DMA and the PIO alternately execute the fixed time.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be specifically described below with reference to the drawings. FIG. 3 is a system configuration diagram to which the present invention is applied. In the figure, the common bus 11 has a CPU 1
(Central processing unit), DMAC2 (DMA control unit), S
CSI CTL3 (general-purpose interface controller for small machines, SCC), MS6 (main memory), LINECTL
7 (line control device, LC) is connected.

A hard disk 5 (HD) is connected to the SCSI bus 12. DMAC2 and SCS
Line 13 to I3 is the DMA request line and line 14 is the response line. A line 15 between the CPU 1 and the DMAC 2 is a hold request line, and a line 16
Is a hold response line. Line 1 for line controller 7
7 is connected, and the interrupt from the line controller 7 via the interrupt line 18 is processed by the CPU 1.

The operation of loading the contents of the hard disk 5 into the MS 6 in the above system configuration will be described below.

(1) The SCC3 reads data from the HD5 via the SCSI bus 12. (2) The SCC3 issues a DMA request (DREQ) to the DMAC2 via the line 13. (3) The DMAC2 receiving the DMA request (DREQ)
C via line 15 to get the right to use bus 11
Issue a hold request (HREQ) to PU1. (4) The CPU 1 reports the hold response (HLDA) signal to the DMAC 2 via the line 16 when the bus use cycle upon receiving the HREQ ends. (5) The DMAC2 starts data transfer from the SCC3 to the MS6, and at the same time, responds to the DREQ (DAC
K) is returned to SCC3 via line 14. (6) The DMAC2 drops the HREQ of the line 15 after the data transfer from the SCC3 to the MS6 is completed. (7) The CPU 1 drops HLDA on the line 16.

The data transfer rate from the HD5 to the SCC3 is DMA by the series of procedures (1) to (7) described above.
It is higher than the transfer rate, and after the above (5) ends, the next DR
If the EQ is already on line 13, DMAC 2 has no time to release bus 11. For this reason, the time until all the data transfer from SCC3 to MS6 is completed (T
0), CPU1 cannot use the bus 11, and an interrupt (INT) from LC7 via the interrupt line 18 during the time T0 cannot be processed by CPU1.

For example, if the transfer data unit from SCC3 to MS6 is 8 KB and the DMA transfer rate is 1 MB / s, the CPU 1 cannot operate for 8 msec. On the other hand, if the transfer rate of the line 17 is 2400 bps, L
C7 receives 1-byte data every 3.3 msec from line 17, and raises INT to CPU1 via line 18.

Therefore, this INT and SCC3 to MS
When a DMA transfer to 6 collides, a maximum of 8 msec
The INT is not accepted by the CPU 1 and an overrun (receiving the next data before the previous data is processed) occurs in LC7.

The present invention has been made to solve the above-mentioned problems, and FIG. 1 is a configuration diagram of an embodiment of the present invention. In the present invention, the DMA request controller 4 (DMA REQUEST CON) is provided between the DMAC 2 and the SCC 3.
(TROLLER) is provided, and the other components are the same as those in FIG.

This DMA request controller (DRC)
Reference numeral 4 is a circuit for controlling DREQ via the line 13a between the SCC3 and the DMAC2, and has the following functions. That is, (a) a function of suppressing the DREQ of the line 13a at regular time intervals (b) a function of suppressing the function of (a) described above by a program (on the MS 6 and executed by the CPU 1) (c) by an INT This is a function to cancel the function of (b) above.

The DRC 4 provided by the present invention operates as follows. (1) The program uses the above-mentioned function (b) immediately before the DMA transfer instruction, and makes it possible to continuously issue DREQ via the line 13b. (2) A DMA transfer is instructed by the program. This starts the DMA continuous transfer from SCC3 to MS6. (3) When an interrupt (INT) is generated from the LC 7 to the interrupt line 18 during the DMA transfer of (2), the function (c) cancels the function (b), and the function (a) operates. (4) Under the above function (a), since the DREQ via the line 13a is periodically suppressed, the CPU 1 can operate intermittently and the INT is processed.

FIG. 2 is a diagram showing a specific configuration of the DMA request control device 4. In FIG. 2, reference numeral 20 is an AND gate for suppressing DREQ via the line 13a, and when the control line 24 is 0, D of the line 13b
REQ is fixed at 0. 25 is a clock of 20 KHz, and when the control latch 26 is 0, the OR gate 21
The output of the control line 24 is alternately set to 1/0 in a cycle of 50 .mu.s via the, to alternately execute DMA and PIO.

Reference numeral 26 is a latch for controlling the control line 23 via the address bus 11b and the data bus 11a, and switches between the DMA continuous execution mode and the DMA / PIO alternate execution mode. Reference numeral 18 denotes an interrupt line connected to the reset input R of the latch 26, which resets the latch 26 when an interrupt occurs to forcibly execute DMA /
Enter the PIO alternate execution mode.

The operation of FIG. 2 will be described. In the DMA continuous execution mode, the data bus 11a becomes 1 and the address of the address bus 11b is decoded by the decoder 27 to 1 immediately before the DMA execution, and becomes 1 to latch. Both the D and T inputs of 26 go to 1 and the output Q is set to 1. Then, the program activates the DMA, and the DMA is continuously executed.

When an interrupt occurs on the interrupt line 18 during continuous execution of DMA, the latch 26 is reset, its output Q becomes 0, and the control line 23 becomes 0. Therefore,
The control line 24 is alternately set to 1/0 in a cycle of 50 μsec by the clock 25 via the OR gate 21.

As a result, the DMA / PIO alternate execution mode is set thereafter, and the interrupt processing by the CPU becomes possible. That is, when the control line 24 is 1, the AND gate 20 is turned on, so DREQ is output to the line 13b and DMA is executed. On the other hand, when the control line 24 is 0, the AND gate 20 is turned off. Since DREQ is not output to the line 13b and DMA execution is suppressed, C
The PU can perform INT processing.

In the above embodiment, DMA / PIO is used.
Although a 20 KHz clock is used for switching, the frequency and the ratio of 1/0 must be determined according to the priority of each processing of DMA and PIO.

[0026]

As described above, according to the present invention, means for alternately switching between the DMA execution mode and the program input / output mode in response to an interrupt from the input / output device during DMA continuous data transfer. Since it is provided, DM
Interrupt request generated during continuous A transfer is at most tens of μs
It will be possible to accept with a delay of c. Further, during the continuous DMA transfer, the control can be entirely transferred to the DMA control device, so that the high-speed transfer which is the original purpose of the DMA can be performed.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing a specific configuration of a DMA request control device of the present invention.

FIG. 3 is a system configuration diagram to which the present invention is applied.

[Explanation of symbols]

 1 Central Processing Unit 2 DMA Control Unit 3 General Purpose Interface Control Unit for Small Machines 4 DMA Request Control Unit 5 Hard Disk 6 Main Storage Unit 7 Line Control Unit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Ken Suzuki, 1 Horiyamashita, Hinoyamashita, Hadano, Kanagawa Prefecture, Kanagawa Plant, Hitate Manufacturing Co., Ltd. (72) Inventor, Yuuo, No. 1, Horiyamashita, Hadano, Kanagawa Kanagawa Plant (72) Inventor Tomonori Takahashi 1 Horiyamashita, Hinoyama, Hadano, Kanagawa Pref., Inside Hitachi Computer Electronics Co., Ltd. (72) Eiji Takahashi 1st, Horiyamashita, Hadano, Kanagawa Hitachi Computer Engineering Co., Ltd.

Claims (1)

[Claims] 1. A control method for transferring data between an input / output device and a main storage device, comprising: DMA control means for continuously controlling transfer of data between the input / output device and the main storage device; A DMA control system characterized by comprising means for alternately switching between the operation by the DMA control means and the program input / output operation in response to an interrupt from the input / output device during data transfer by the means.