JPS6055433A - Floppy disk controller - Google Patents

Abstract

PURPOSE:To shorten an operation time with simple constitution by providing a DMA mode and program mode conversion part, and employing a control means which places CPU in a stand-by state. CONSTITUTION:When data is writeen in a floppy disk device various parameters are written on FDC (floppy disk controller) 45 in program mode firstly. Then, data from a memory 44 are written on the FDC45. At this time, the CPU43 stops until a signal DRQ arrives from the FDC45, and the data is written on the FDC45 when the signal DRQ arrives. Then, the CPU43 counts up the address of the memory 44 and data on the address is loaded in a register of the CPU43. Then, the CPU performs the writing to the FDC45, and stops as it is until the next signal DRQ arrives. The CPU is used fully in this time and the margin of time is improved as compared with the program mode.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a floppy disk control device for storing information in OA equipment and the like.

Conventional configuration and its problems FIG. 1 shows a configuration using a DMA controller. Second
The figure shows a timing chart of a general access method to a floppy disk device. First, in the program mode, input parameters (for example, the number of transfer words, transfer destination, etc.) to the floppy disk controller (hereinafter referred to as FDC) 3. After inputting the specified parameters, the DMA mode is entered and the FDC 3 receives a DRO (DMA request) signal 9. occurs, and data is exchanged with the memory 2.

After a predetermined DMA transfer, a DMA transfer result report is received in the program mode, and it is determined whether the transfer is possible or not.

Data is exchanged between the floppy disk device 6 and the memory 2 according to these sequences.

FIG. 3 shows the timing of data writing from the memory to the floppy disk device, and FIG. 4 shows the timing of data transfer from the floppy disk device to the memory. First, writing data from memory to a floppy disk device will be explained. When the DMA controller 4 takes control of the buses 13 and 14 under the control of the CPU (Central Processing Unit) 10 in response to the DRQ (DMA request signal) from the FDC 3, the FDC
DACK (DMA confirmation signal) is generated for DCa, and ADDRESS (address) 1s and MEMR (memory read signal) 11 are output from the DMA controller 4, so DATA14 is read from the memory and at this point Since IQW (I10 write signal) 8 is generated, writing to FDCa is possible. FDC
The data written to a is written to the floppy disk device 6 as serial data.

Conversely, for transfer from the floppy disk device 6 to the memory 2, as shown in FIGS. 1 and 4, if serial data from the floppy disk device 6 is passed to the FDCa, the DRQ is By setting the signal to 1", the DMA controller 4
3.14 and DACK signal 1o for FDCa.
and ADDRES from DMA controller 4.
Since S13 and IQR (I10 read signal) 7 are generated, writing to the memory 2 is possible.

In order to perform data transfer by controlling the bus using a DMA controller, memory,
/Q access time is required, and high-speed transfer is possible. However, since a DMA controller is used, the number of peripheral circuits and the like increases, resulting in a large cost.

On the other hand, there is a method of transferring data in a program mode without using a DMA controller. This method has the configuration shown in FIG. 5, and is a method in which the CPU 29 intervenes in transferring data between the FDC 31 and the memory 30, and is very advantageous because it can be configured without using a DMA controller or the like. However, as shown in FIG. 6, in response to the interrupt signal INT41 of the FDC 31, the CPU 29 accepts the interrupt and jumps to the @interrupt processing program, reads and writes the θ data,
Basically, the process counts up the transfer destination address, then accesses the FDC 31, and returns to zero.

You have to go through three stages: O and O. For this reason, if the floppy disk device 33 is, for example, a single-density mini-floppy, the INT 41 interval is 64 μs, and processing can be performed with a slight margin. However, in the case of a double-density mini-floppy, the INT41 interval is 32 μs, and due to the FDCa1 restriction, the floppy disk drive 3
26μs for reading from 3, 30μs for writing
If it is not processed within μs, an overrun error will occur, which is a severe restriction depending on the hardware including the CPU 29.

OBJECTS OF THE INVENTION The present invention solves the various problems of the prior art described above, and it is an object of the present invention to provide a floppy disk control device that has a simple configuration and can shorten operating time.

Structure of the Invention In order to achieve the above object, the present invention has means for transferring data between a floppy disk device and a memory, and a central processing unit is provided between the memory and the floppy disk controller. The floppy disk controller has means for intervening and timing the central processing unit until a request signal from the floppy disk controller is generated at the time of access, and means for causing the floppy disk controller to operate in a direct memory access mode. .

DESCRIPTION OF EMBODIMENTS A detailed explanation of the present invention will be given below with reference to the drawings from FIG. 7 onwards.

In FIG. 7, the 70-sob disk control device of this embodiment has a D
A system in which MA mode and program mode are mixed, that is, FDC45 operates in DMA mode, and CpU4
3 and a DMA mode/program mode converter 46
If the program mode is set up and operated from the CPU 43, the time can be shortened and it can be realized with a simple configuration.

The principle is shown in Fig. 8. For example, when using a double-density mini-floppy, the interval between one DRQ signal and the next DRQ signal is 3
The time is 2 μs, and processing must be performed within this range. Taking the opposite approach to the conventional method, we take the following method. First, consider the case of writing from the memory 44 to a floppy disk device. First, if you want to write data to a floppy disk device, in the program mode,
Write various parameters to FDC45.

Thereafter, the digit is extracted from the address of MEMORY 44 to be transferred to FDC 415 and written to FD04B. At this time, Cp U43 is FDC45
It stops until a DRQ signal is received from the FDC 4B, and when the DRQ signal is received, data is written to the FDC 4B. Thereafter, the @Cp U 43 counts up the current address of the memory 44 and loads the data at that address into the register of the CPU 43. Next, writing is performed to the FDC 45, and the process remains in that state until the next DRQ signal arrives. When the DRQ signal arrives, data is written to the FDC 45. Thereafter, the memory address is counted up and the data at that address is loaded into the register of the CPU 43. Thereafter, the required number of words to be transferred is transferred in the same manner.

Similarly, regarding reading from the floppy disk device 48 to the memory 44, various parameters are first written to the FD045 in the program mode. In order to send data from the FDC 45 to the start address of the memory 44 to be transferred from the EDC 45,
A data request is made to the FDC 45. At this time,
Cp U43 stops until the DRQ signal comes from FDCats, and when the DRQ signal comes, the data is transferred to the CPU.
43 register. Next, the address of the O memory 44 is counted up, and the data at that address is written. Thereafter, a data request is immediately made to the FDC 45. At this time, the CPU 43 similarly
The process stops until the DRQ signal from the C45 arrives, and at the time the DRQ signal arrives, the data is taken into the register of the CPU 43. The address of which memory 44 is next to be incremented, and data is written to that address. The same process is repeated thereafter, and a predetermined number of words are transferred.

In this way, data is immediately transferred to C at the 9th point of rising edge of the DRQ signal.
In order to capture it into PU43, the time until the next DRQ signal arrives (32 μs for double density mini croppy) is fully Cp.
U can be used, interrupt processing, etc. are not required, and there is a large margin of time compared to the access method using the program mode described above.

Fig. 9 shows a specific circuit configuration diagram of this embodiment, Fig. 10 shows a timing chart for writing to a floppy disk device, Fig. 11 shows a timing chart for reading from a 70 Soppy disk device, and Fig. 12 shows parameters. Figure 13 shows the timing chart for writing in program mode such as input, and Figure 14 shows the timing chart for program mode such as reading results after transfer is completed.
The timing chart for writing in A mode is shown in the 15th
The figure shows a timing chart for reading in DMA mode.

First, before writing to the floppy disk device, the transfer amount, transfer destination, etc. are input in program mode. Thereafter, DMA transfer is performed for the required number of words in the DMA mode, and the program mode is switched to read and check the results. It usually consists of these three basic operations.

First, in the first parameter writing mode, the ninth
In the figure, with DMA openclose 82 set to 1'', flip-flop 73.74 is connected to FDCWT79.
Let the output Q of each be 111 ml. In this state, access to the FDC 77 becomes possible, and parameters are written and deleted at the timing shown in FIG. For writing, in order to take timing with FDC77, WT,
For ACK (acknowledgement signal), shift register 7
The timing was determined at 2. When writing of a predetermined amount of parameters is completed, DMAopenclose 82 is closed to IIO#, and the outputs Q of 7 lip-flops 73 and 74 are set to "o", so that C8 does not become 0'' even if there is an access from the CPU, and FDC 77 The DRQ signal from the FACWT signal 79 is made to meet the conditions of the FACWT signal 79, so that DMA transfer is possible. FIG. 14 shows the timing. When the predetermined transfer amount is completed, DMA□p6nC1066B2 is 1# and 7+
) Set the output Q of the flop 74 to 1" and switch to program mode. After that, report the result of DMA transfer using F.
Read FDC77 using DCRDao. The timing is shown in FIG.

The same is true when data is retrieved from a floppy disk device as shown in Figure 11, and in that case the DM
The timing of A transfer is shown in FIG.

Also, if an error occurs during DMA, the interrupt signal lNT1
29 occurs, the DRQ signal is no longer generated and the CPU remains stopped. Therefore, as shown in FIG. Pass lock is prevented by setting ACK to 0#.

Effects of the Invention As described above, the present invention provides a DMA mode and program mode converter, and as a control method thereof, the CPU
By using the method of waiting for the floppy disk, time constraints are eased without being affected by the type of floppy disk.
Furthermore, the cost is significantly reduced compared to conventional peripheral circuit components including DMA controllers, and the effect is tremendous.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional floppy disk control device, and FIGS. 2 to 4 are timing charts showing the access sequence of the device. FIG. 6 is a block diagram showing another conventional floppy disk control device.
FIG. 6 is a timing chart showing the access sequence of the same device, FIG. 7 is a block diagram showing a floppy disk control device in one embodiment of the present invention, FIG. 8 is a timing chart of the same embodiment, and FIG. 9 is the same. The specific circuit diagrams of the embodiment, FIGS. 10 to 16, are timing charts for explaining the operation of the circuit. 43...CpU, 44...Memory, 4
5... FDC, 46... Program mode DMA mode converter, 47... Floppy disk controller, 48... Floppy disk device. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 5
Figure QO Figure 7 Figure 3 @ Figure 8

Claims (1)

[Claims] means for transferring data between a floppy disk device and a memory; a central processing unit interposed between the memory and the floppy disk controller; and a means for transferring data between the floppy disk device and the memory; and a means for causing the floppy disk controller to operate in a direct memory access mode.
0 Soheetask control device.