JPH04131954A - Peripheral device - Google Patents

Abstract

PURPOSE:To improve the control efficiency and the processing ability by providing an interface which controls the instructions received from a host device as a series of instructions, a holding register which holds and outputs successively a series of instructions, and an existing latch which takes the instructions out of the holding register and sends the executed instructions to a control part. CONSTITUTION:An interface 1 receives an instruction 11 from a host device and sends it to a holding register 2 as an instruction 13. When the first instruction is outputted from the register 2 as an instruction 14, an existing latch 3 fetches the instruction 14 and sends it to a control part 4 as an instruction 15. The latch 3 keeps its present state until an answer 18 is received from the part 4. The part 4 sends a control signal 16 to an operating part 17 and controls the signal 16 by reference to the operating information 17 showing the state sent from the part 5 to complete the operation prescribed by the instruction 15. Thus it is possible to reduce the necessity for intervention of the host device for control of a peripheral device and to improve the control efficiency and the processing ability.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a peripheral device that receives an operation command from a host device and performs a specified operation.

[Conventional technology]

A conventional peripheral device that receives an operation command from a host device and performs a specified operation has a control unit that receives commands and operation information from the host device and generates a control signal, and operates according to the control signal and determines its operating state. and an operation section that sends out operation information indicating the operation.

(The control unit 4 and operation unit 5 (reference numeral A) in FIG. 1 and the second correspond to this.) Such peripheral devices receive and execute instructions, and respond in accordance with their operating state. A signal is sent back to complete the operation for the command. At this time, the control unit decodes the received command and generates a control signal instructing the corresponding operation. The operating section operates according to the instructions of the control signal, and returns operating information indicating the operating state at that time to the control section. The control section refers to the returned operation information, generates a response signal corresponding to the operation, and sends a corresponding control signal to the operation section using the operation information as control information.

In this way, conventional peripheral devices perform the operation specified by each command and send back a response signal.

Therefore, a host device that controls such a peripheral device must wait for a response signal for each command.

Further, for such peripheral devices, commands for operating the peripheral devices are determined for each function, and for peripheral devices having a variety of functions, a large number of commands corresponding to the peripheral devices are set.

[Problem to be solved by the invention]

As mentioned above, conventional peripheral devices perform the operation specified by each command and return a response signal, which places a heavy burden on the host device that controls it.
This is a factor that reduces the efficiency of a host device that controls a large number of peripheral devices.

Among the large number of instructions, there are some instructions that require instantaneous exchange of information, which requires synchronization between the host device and the peripheral device, but simply specifying the operation and leaving the execution to the peripheral device. There are also commands that require instantaneous exchange of information, but there are also commands that detect changes in the state of peripheral devices in order to send commands that specify actions to peripheral devices. be. Conventionally, a host device is involved in all of these instructions. Even if an instruction can be entrusted to a peripheral device, it is necessary to check whether the instruction has been executed normally. ) Peripheral devices having many functions distinguish between many instruction codes, so the amount of information (number of bits) increases, and the burden on hardware such as transmission paths and identification logic circuits also increases.

[Means to solve the problem]

The peripheral device of the present invention starts its operation upon receiving an instruction specifying its operation from a host device, and executes the received instruction while transmitting information about the progress of the operation, the status of the operation, and the result of the operation. The peripheral device includes an interface that manages instructions received from the host device as a series of instructions, a standby register that holds and sequentially outputs the series of instructions, and a standby register that takes out instructions from the standby register and sends execution instructions to a control unit. It is equipped with the current plan to send to Sochi.

The peripheral device of the present invention also starts its operation upon receiving a command specifying its operation from a host device, and transmits information about the progress of the operation, the status of the operation, and the result of the operation while executing the received command. In a peripheral device to be executed, an interface that manages instructions received from the host device as a series of instructions, a standby register that holds and sequentially outputs the series of instructions, and a control unit that extracts instructions from the standby register and controls execution instructions. The current latch to be sent to the standby register, the output signals of the standby register and the current latch, the response signal from the control unit, and the operation information from the operation unit are inputted to the standby register to send a control signal to limit execution of the instruction. and a decision logic unit outputting to the current latch and the control unit.

〔Example〕 Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

In FIG. 1, an interface 1 receives an instruction 11 from a host device and sends it as an instruction 13 to a standby register 2. The standby register 2 sequentially holds the instructions 13 sent out by the interface 1 and sends them out in the order in which they were input. Further, operation information 19 indicating whether or not the instruction is held is sent to the interface 1. When the first instruction is output from the wait register 2 as instruction 14, the current latch 3 is
It takes it in and sends it to the control unit 4 as a command 1, and holds that state until a response 18 to it is received from the control unit 4. The control unit 4 sends a control signal 16 to the operation unit 5, and controls the control signal 16 while referring to operation information 17 indicating the state sent from the operation unit 5 to issue the command 15.
complete the specified operations. When it is detected that a predetermined operation has been completed, a response 18 is sent to notify this fact.

When the interface 1 receives the response 18 from the control unit 4, it refers to the operation information 19 indicating the state of the standby register 2, and if there is a hold command, sends the response 12 to the host device.
It only manages the information of internal instructions without generating any commands.

The response 18 also enters and updates the wait register 2 and current latch 3, which sends the next instruction to the controller 4. The same operation as described above is performed for the next instruction, and the subsequent instructions are sequentially executed.

When there are no more instructions held in the standby register 2, that information is shown in the operation information 19. At this time, when the completion of the operation is notified by response 18, it means that all the series of operations have been completed, so the interface 1 generates response 12 to notify the host device of the completion of the operation. At this time, the interface 1 returns the information management of the command to the initial state and sends it as the end information as the response 12.

When an abnormality occurs in the process of the above-mentioned operation, a response 18 from the control unit 4 notifies the occurrence of the abnormality, and the interface 1 accordingly notifies the host device of the suspension of the operation by a response 12 at that point. At the same time, the information management status of the command is sent in response 12 to notify the higher-level device of the execution status of the command.

The abnormal state is canceled only by an abnormality release command, and until then, the state is maintained and the remaining commands are not executed. The instruction information management and standby register 2 of the interface 1 is initialized by the abnormality release instruction, and becomes ready to receive new instructions.

FIG. 3 is a circuit diagram showing details of the interface and wait registers and current latches of the embodiment of FIG.

In FIG. 3, the instruction 13 sent to the standby register 2 is the same as the instruction 11 sent from the host device to the interface 1, but the code may be converted if necessary.

The decoder 101 identifies the abnormality clearing command from the instructions 11 and sends out the abnormality clearing command 13C. This abnormality cancellation command 1
3c resets the up/down counter 102, flip-flop counter 1104, and FrFO register 201, returning them to their initial states. The up/down counter 102 is reset by the abnormality release command 13C, and the up/down counter 102 is reset by the command 11C.
It counts up in response to the strobe signal 11B, and counts down in response to the operation completion response (completion response) 18A, and the count value indicates the execution state of the instruction.

That is, the count value indicates how many unprocessed instructions remain, and serves as instruction management information for determining how far the instructions have been executed when an abnormality occurs and processing is interrupted. When the instruction is completely completed, the count value is 0.
is back.

The FIF○ register 201 takes in the current instruction 13 every time the strobe signal 11B is received.

The captured instructions are sequentially sent out as instructions 14,
The later instruction is made to wait until the earlier instruction is sent. The instruction 14 is sent when the end response 18 is sent at the start of instruction execution.
When A expires, there is a termination response 18A, which activates the next command, and each time the termination response 18A expires, the commands that have been on standby are sequentially sent out.

When the end response 18A arrives, the D typer edge 301 reads the instruction 14 output from the FIFO register 201, holds the read instruction until the end response 18A expires as soon as the instruction starts, and executes the instruction as instruction 15. It maintains the current listening output.

The AND gate 103 outputs the end response 18A and the operation information 1 indicating that there are no more instructions in the FIFO register 201, which is output from the EMP output terminal of the FIFO register 201.
9 is input, and when both conditions are met, that is, when there is no command to be executed next and there is a response indicating the completion of the previous command, a response (completion response) 12A is generated and this is sent to the host device. Notice.

Flip flops 104 responds abnormally (abnormal response) 1
Set when inputting 8B and responds (abnormal response) 1
2B, notifies the host device of this fact and maintains that state, and when the abnormality release meeting 13C is input, it is reset and stops sending out the abnormality response 18B. At this time, other circuits are also initialized.

Through the operations described above, a series of input commands are executed in sequence, and when all of them are completed, a completion response is sent to the host device. Furthermore, if an abnormality occurs during execution, a response to the abnormality is sent at that point, and at the same time, the execution status of the series of instructions is reported.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

In this embodiment, a determination logic section 6 is added to the first embodiment. The decision logic unit 6 inputs the instructions 14 and 15, the response 18, and the operation information 17, and its output control signal 20 is input to the standby register 2, the current latch 3, and the control unit 4 and serves as their activation condition. . Other configurations and operations are the same as in the first embodiment.

The determination logic unit 6 determines the next instruction to be executed 14 outputted by the standby register 2, the instruction 15 that is being executed or has finished execution outputted by the current latch 3, and the response 1 outputted by the control unit 4.
8 and the operation information 17 output from the operation unit 5, and when the combination thereof satisfies a predetermined condition, the output condition is changed, and the output control signal 20 is a command to be executed next. This is the activation condition.

When activating an instruction, if the control signal 20 indicates that the operating conditions for executing the instruction are met, the control section 4 immediately sends out a control signal 16 instructing execution of the instruction and performs the control operation. If not, it waits for the control signal 20 to indicate this and then starts the operation. This signal causes the current latch 3 to hold its output state and the wait register 2 to update its output signal.

FIG. 4 is a circuit diagram showing details of the decision logic section of the embodiment of FIG. 2.

In FIG. 4, a combinational logic circuit 601 is a logic circuit into which a next instruction 14, a current instruction 15, operation information 17, and a response 18 are input. When a combination of these input signals meets a predetermined condition, a corresponding output signal is sent out. During normal operation, it corresponds to response 18, and when response 18 is present, a signal is output from the 0UTI terminal to set the flip flora 1602, and when response 18 is cut off, it becomes 0UT1.
Stop the output of the signal from the terminal, output the signal from the OUT2gJ child, and reset the flip-flop .l pro 02.

The flip 70 1602 performs a set operation and a reset operation based on the output signals from the 0UT1 terminal and the 0UT2 terminal of the combinational logic circuit 601, respectively, and outputs the control signal 20. During normal operation, control signal 2
0 becomes the same signal as response 18, and the same operation as in the first embodiment is performed.

When the execution of the instruction 14 is restricted by the previous instruction or the operating state of the device, the combinational logic circuit 601
sends an output signal from the ○UTI terminal and the 0UT2 terminal when the combination of input signals satisfies the condition for releasing the constraint, and the flip floor 602 operates accordingly. Therefore, the control signal 20 changes in accordance with the satisfaction of the execution conditions for the command, and waits until the execution conditions are met before executing the command.

Conventionally, when a host device sends a command, it is necessary to detect the operating state of the peripheral device and confirm that the peripheral device is in an operable state, and the host device intervenes for this purpose. Furthermore, when there is a restriction on the timing of execution, it has always been necessary for a higher-level device to intervene, but this embodiment makes it possible for a peripheral device to independently perform the same control operations as those of a higher-level device. This made it possible.

Next, the format of control commands effective in the first and second embodiments described above will be explained.

Assuming data transfer between registers in a peripheral device, assuming that there are eight registers R8 to R7, the command to transfer data between these registers is conventionally as follows:
Instruction to transfer from register R8 to register R1 (RO→
56 types of instructions corresponding to combinations of eight registers R6 to R7 were used, such as an instruction (RO-R2) for transferring data from register Ro to register R2.

Assuming that this transfer operation is performed in two steps via buffer register R, first transfer from one register R1 among registers R8 to R7 to buffer register RB,
Subsequently, it is sufficient to transfer from the buffer register RB to another register R,, among registers R8 to R7, and the instructions for this are instructions (Ro to R7-Re) and instructions (
It is sufficient to set 16 types of unit instructions (R8-Ro to R7) and combine them to form an execution instruction. For this reason, the length of the instruction used to be 6 bits, but
In this case, 4 bits is sufficient.

In this instruction format, even if it takes time to execute a unit instruction, if the configuration of the first or second embodiment is provided, the instruction can be received in advance for each execution unit and then operated.

〔Effect of the invention〕

As explained above, the peripheral device of the present invention receives a series of instructions all at once, executes them consecutively, and returns a response after they are completed, and the peripheral device independently determines the start of execution. By doing so, it is possible to reduce the need for intervention by a host device in controlling peripheral devices, thereby improving control efficiency and processing capacity.

Also, when transferring data between registers in a peripheral device, the bit length of the transfer instruction can be shortened by using a buffer register as an intermediary.
This has the effect of reducing the burden on hardware.

■...Interface, 2...Waiting register, 3...Current latch, 4...Control unit, 5...Operation unit, 6 ...Judgment logic unit, 101...Decoder, 102...
Up/down counter, 103...and gate, 104/602...flip-flop, 2
01...FIFO register, 301...-
・D type latch, 601... Combinational logic circuit.

Claims (1)

[Scope of Claims] 1. Starts the operation upon receiving an instruction specifying the operation from the host device, and executes the received instruction while transmitting information regarding the progress of the operation, the status of the operation, and the result of the operation. In a peripheral device, the peripheral device includes: an interface that manages instructions received from the host device as a series of instructions; a standby register that holds the series of instructions and sequentially outputs them; and a control unit that takes out instructions from the standby register and executes the instructions. A peripheral device comprising: a current latch that sends a signal to a current latch; 2. The peripheral device according to claim 1, further comprising a buffer register for transferring data between internal registers. 3. A peripheral device that starts an operation upon receiving an instruction specifying an operation from a host device, and executes the received instruction while transmitting information regarding the progress of the operation, the status of the operation, and the result of the operation. an interface that manages instructions received from a host device as a series of instructions; a standby register that holds the series of instructions and sequentially outputs them; and a current latch that takes out instructions from the standby register and sends execution instructions to a control unit. , the output signals of the standby register and the current latch, the response signal from the control unit, and the operation information from the operation unit are inputted, and a control signal for limiting execution of an instruction is input to the standby register, the current latch, and the control unit. A peripheral device comprising: a determination logic section that outputs an output to the section. 4. The peripheral device according to claim 3, further comprising a buffer register for transferring data between internal registers.