CN114328357A

CN114328357A - Interconnection communication method and system for bare chip and integrated package chip

Info

Publication number: CN114328357A
Application number: CN202210046629.4A
Authority: CN
Inventors: 黄金煌
Original assignee: Beijing Unigroup Tsingteng Microsystems Co Ltd
Current assignee: Beijing Unigroup Tsingteng Microsystems Co Ltd
Priority date: 2022-01-17
Filing date: 2022-01-17
Publication date: 2022-04-12

Abstract

The application relates to the technical field of digital communication, and discloses an interconnection communication method for a bare chip, which is applied to a first bare chip as a slave end, wherein the first bare chip is configured to be in communication connection with a second bare chip as a host end through an SPI (serial peripheral interface) protocol, the SPI protocol comprises an interrupt request input/output interface and a confirmation character input/output interface, and the method comprises the following steps: adjusting a signal of an interrupt request output interface to a high bit to send an interrupt request to the second die in an idle and sending-enabled state; under the condition that the signal of the character input interface is confirmed to be high, the slave mode is switched to the master mode; sending communication data to the second die via an SPI protocol; and after all the communication data are sent, adjusting the signal of the interrupt request output interface to a low level, and switching the master mode back to the slave mode. The application also discloses an integrated sealing chip.

Description

Interconnection communication method and system for bare chip and integrated package chip

Technical Field

The present application relates to the field of digital communication technologies, and for example, to an interconnection communication method, system and integrated encapsulated chip for a die.

Background

At present, as the chip industry develops and matures, the integrated package chip also becomes a common chip architecture mode. The integrated chip may include independent modules with different functions, such as an integrated chip for financial payment, which includes a Near Field Communication (NFC) module and a Secure Element (SE) module. The two modules are two different circuits with independent functions, and the inside of the integrated chip can be divided into an NFC Die (Die) and an SE Die (Die) in view of shortening the development period. And data interaction is carried out between the NFC module and the SE module through an agreed protocol. Meanwhile, in an integrated and sealed chip, there are usually some mature functional modules as independent dies, so the communication performance between the dies becomes an important performance index of the integrated chip. In order to enable a main program of a processor to quickly take and process data in an interrupt service routine, an existing SPI communication method based on DMA includes the following steps: initializing an SPI (serial peripheral interface), and initializing the SPI after a processor is powered on; initializing a DMA program, and initializing receiving and sending configuration of the DMA by the processor; sending data, wherein the SPI interface is circularly detected by the main program of the processor, when the data to be sent is detected by the main program of the processor, DMA is started to carry out parallel sending on the data to be sent, and when the data to be sent is sent, the DMA generates sending completion interrupt; receiving data, circularly detecting the SPI interface by the main program of the processor, starting DMA to receive the data to be received in parallel when the main program of the processor detects the data to be received, and finishing the interruption of DMA generation and reception when the data to be received is received.

In the process of implementing the embodiments of the present disclosure, it is found that at least the following problems exist in the related art: in the prior art, a mature Serial Peripheral Interface (SPI) protocol is used, and a Direct Memory Access (DMA) mode is used, so that only one-way communication between a die and a bare die can be realized, that is, a master-slave relationship between the die and the bare die cannot be switched, and interactive communication between the die and the bare die cannot be realized.

Disclosure of Invention

The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview nor is intended to identify key/critical elements or to delineate the scope of such embodiments but rather as a prelude to the more detailed description that is presented later.

The embodiment of the disclosure provides an interconnection communication method and system for a bare chip and an integrated seal chip, so that the bare chip and the bare chip can realize the switching of master-slave relation, and the bare chip as a slave terminal also has the function of actively sending data.

In some embodiments, the method is applied to a first die as a slave, the first die is configured to be communicatively connected with a second die as a master through an SPI protocol, the SPI protocol includes an interrupt request input/output interface and a confirmation character input/output interface, and the method includes:

adjusting a signal of an interrupt request output interface to a high bit to send an interrupt request to the second die in an idle and sending-enabled state;

under the condition that the signal of the character input interface is confirmed to be high, the slave mode is switched to the master mode;

sending communication data to the second die via an SPI protocol;

and after all the communication data are sent, adjusting the signal of the interrupt request output interface to a low level, and switching the master mode back to the slave mode.

In some embodiments, the method is applied to a second die as a host inside a combined chip, and the second die is configured to be in communication connection with a first die as a slave through an SPI protocol, wherein the SPI protocol includes an interrupt request input/output interface and a confirmation character input/output interface, and the method includes:

under the condition that a signal input by an interrupt request is high, switching from a host mode to a slave mode;

adjusting a signal of a confirmation character output interface to a high position so as to send a confirmation character to the first bare chip;

receiving communication data sent by the first die through an SPI protocol;

and after all the communication data are received, adjusting the signal of the confirmation character output interface to be at a low level, and switching the slave mode back to the master mode.

In some embodiments, the method is applied to a first die as a slave inside a composite chip, the first die is configured to be communicatively connected with a second die as a master through an SPI protocol, the SPI protocol includes an interrupt request input/output interface and a system operating state input/output interface, and the method includes:

under the condition that signals of an interrupt request output interface and signals of a chip selection signal input interface in the SPI protocol are all low, receiving communication data sent by the second bare chip through the SPI protocol;

adjusting a signal of a system working state input interface to a high position;

storing the received communication data into a random access memory of the first die by a direct memory access transmission mode;

and after the communication data are completely stored, generating an interrupt signal for completing the communication data receiving, and adjusting a signal of a system working state input interface to a low position.

under the condition that signals of an interrupt request output interface in an SPI protocol and signals of a system working state input interface are all low, communication data are obtained from a buffer of the second bare chip through a transmission mode of direct memory access;

adjusting a signal of a system working state output interface to a high position;

sending the communication data to the first die via an SPI protocol;

and after the communication data are completely sent, generating an interrupt signal for finishing sending the communication data, and adjusting a signal of a system working state output interface to a low level.

In some embodiments, the interconnected communication system comprises a first die as a slave and a second die as a host, the first die configured to be communicatively coupled to the second die via an SPI protocol, wherein the SPI protocol comprises an interrupt request input/output interface, a confirmation character input/output interface, and a system operating state input/output interface;

the interrupt request output interface of the first die is connected with the interrupt request input interface of the second die, and the interrupt request input interface of the first die is connected with the interrupt request output interface of the second die;

the confirmation character output interface of the first die is connected with the confirmation character input interface of the second die, and the confirmation character input interface of the first die is connected with the confirmation character output interface of the second die;

the system working state output interface of the first bare chip is connected with the system working state input interface of the second bare chip, and the system working state input interface of the first bare chip is connected with the system working state output interface of the second bare chip.

In some embodiments, the integrated package chip includes an interconnected communication system for dies as described herein.

The interconnection communication method, system and integrated package chip for the bare chip provided by the embodiment of the disclosure can realize the following technical effects:

this application is through designing the interface to the SPI agreement, make the bare core as the slave end can confirm according to actual demand using interrupt signal and affirmation character, carry out the switching from the primary relationship, thereby make the bare core of slave end possess the function of initiatively sending communication data, and then make the bare core as the master end and the bare core as the slave end all can initiatively initiate communication data transmission, in order to accomplish the communication task of bare core interconnection, and simultaneously, this application area occupation is less, be applicable to the small size low-cost joint seal chip and accomplish interconnection work fast.

The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.

Drawings

One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the accompanying drawings and not in limitation thereof, in which elements having the same reference numeral designations are shown as like elements and not in limitation thereof, and wherein:

fig. 1 is a schematic diagram of a system environment for a method for interconnection communication of dies provided in the present application;

fig. 2 is a schematic communication flow diagram of a slave end in an interconnection communication method for a die provided in the present application;

fig. 3 is a schematic communication flow diagram of a slave in another interconnection communication method for dies provided in the present application;

fig. 4 is a schematic communication flow diagram of a slave in another interconnection communication method for dies provided in the present application;

fig. 5 is a schematic communication flow diagram of a slave in another interconnection communication method for dies provided in the present application;

fig. 6 is a schematic communication flow diagram of a host in an interconnection communication method for dies provided in the present application;

fig. 7 is a schematic communication flow diagram of a host in another interconnection communication method for dies provided in the present application;

fig. 8 is a schematic communication flow diagram of a host in another interconnection communication method for dies provided in the present application;

fig. 9 is a schematic communication flow diagram of a host in another interconnection communication method for dies provided in the present application;

fig. 10 is a schematic diagram of an improved SPI protocol interface provided herein.

Detailed Description

So that the manner in which the features and elements of the disclosed embodiments can be understood in detail, a more particular description of the disclosed embodiments, briefly summarized above, may be had by reference to the embodiments, some of which are illustrated in the appended drawings. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may be practiced without these details. In other instances, well-known structures and systems may be shown in simplified form in order to simplify the drawing.

The terms "first," "second," and the like in the description and in the claims, and the above-described drawings of embodiments of the present disclosure, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the present disclosure described herein may be made. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions.

The term "plurality" means two or more unless otherwise specified.

In the embodiment of the present disclosure, the character "/" indicates that the preceding and following objects are in an or relationship. For example, A/B represents: a or B.

The term "and/or" is an associative relationship that describes objects, meaning that three relationships may exist. For example, a and/or B, represents: a or B, or A and B.

The term "correspond" may refer to an association or binding relationship, and a corresponds to B refers to an association or binding relationship between a and B.

First, terms related to the present application are explained:

bare chip (Die): the chip refers to a crystal grain before the chip is packaged, and is a small piece cut from a silicon Wafer (Wafer) by laser, each bare chip is an independent functional chip, and finally the bare chip is packaged as a unit to be a common chip.

Single sealing: only one die is contained in one packaged chip.

Integrating a sealing chip: two or more bare chips are contained in one packaged chip.

SPI protocol: the Serial Peripheral Interface protocol is a synchronous Serial Interface technology, and is a high-speed, full-duplex and synchronous communication bus.

Direct Memory Access (DMA): refers to copying data from one address space to another address space, providing high speed data transfer between a peripheral and memory or between memory and memory.

Random-Access Memory (RAM): is one of the internal memories of a computer.

Instruction Register (IR): is a type of register in a central processing unit that holds an instruction that is currently being executed. When an instruction is executed, it is first read from main memory into a data register and then transferred to an instruction register. An Instruction includes two fields, an opcode and an address code, and in order to execute the Instruction, the opcode must be tested to identify the desired operation, and an Instruction Decoder (ID) does so. The instruction decoder decodes the operation code part of the instruction register to generate the control potential of the operation required by the instruction, and sends the control potential to the micro-operation control circuit to generate a specific operation control signal under the action of the timing signal of the timing unit. The output of the opcode field in the instruction register is the input to the instruction decoder. Once the operation code is decoded, a specific signal of a specific operation is sent to the operation controller.

At present, the integrated circuit industry is competitive, and when a blue sea area is found, corresponding integrated circuit chip products can be designed and manufactured at the fastest speed, and whether the first opportunity can be preempted in the blue sea competition is determined. Therefore, in some specific application scenarios, the integrated sealed chip becomes a way of outputting products quickly. By decomposing the functions of the chip, the product characteristic module and the mature general module are divided. If a mature functional chip can be used as an independent part of the chip, the design of the chip can be directly used as an independent bare chip of the integrated package chip when the chip is designed.

The way and efficiency of inter-die communication directly affect the performance of the integrated package chip. The universality and maturity of the communication between the bare chips determine the length of a development period, so that the standard and mature SPI protocol is used as a prototype, an interface of the SPI protocol which is based on DMA and can be switched from master to slave is developed, the function of automatically moving data can be integrated, the participation of a Micro Control Unit (MCU) is reduced to the greatest extent, the thread resource of the MCU is released, and the interface hardware logic can automatically complete the moving work between data transmission and a memory according to a register instruction.

As shown in fig. 1, the first die serving as the slave according to the SPI protocol may perform handshake confirmation using an interrupt signal and the second die serving as the master according to actual transmission requirements, and perform slave-to-master switching, so that the first die serving as the slave has a function of actively transmitting data, that is, both the master and the slave have a capability of actively transmitting data. Specifically, this application includes that the integration closes first bare chip and the second bare chip that seals chip inside needs to carry out the data interaction in integrated, disposes SPI module, RAM, other functional logic module and MCU in every bare chip, the SPI module includes DMA unit and logic design unit, DMA unit and RAM communication connection, the DMA unit with logic design module communication connection, SPI module and other functional logic module pass through SFR bus and MCU communication connection, and SPI protocol interface bus between the SPI module uses the metal link to connect.

Meanwhile, the original SPI protocol is improved, an Interrupt Request (IRQ) interface, an Acknowledge Character (ACK) interface and a system working state (BUSY) interface are added, and the specific improved SPI interface based on DMA is shown in table 1 below:

TABLE 1

Signal name	Interface meaning	Signal name	Interface meaning
				SPI_SCKOUT_O	Clock output signal	SPI_SCKIN_I	Clock input signal
SPI_SSN_O	Chip select output signal	SPI_SSN_I	Chip select input signal
				SPI_MOSIOUT_O	Transmitting data signals	SPI_MOSIIN_I	Receiving a data signal
SPI_MISOIN_I	Receiving a data signal	SPI_MISOOUT_O	Transmitting data signals
				SPIIO_OUT2_O	Transmission data line 2	SPIIO_IN2_I	Reception data line 2
SPIIO_OUT3_O	Transmission data line 3	SPIIO_IN3_I	Reception data line 3
				SPI_IRQ_I	Interrupt request input signal	SPI_IRQ_O	Interrupt request output signal
SPI_ACK_O	Acknowledge character output signal	SPI_ACK_I	Confirming character input signals
				SPI_BUSY_O	System working state output signal	SPI_BUSY_I	System working state input signal
SPI_INT_O	Interrupt signal

In the above table, "Output", i.e., the Output (send) interface, is represented in the signal name ending with "O"; "Input", i.e., the Input (receiving) interface, is denoted by the end of an "I".

The integrated seal chip of this application is at first initialized improved SPI agreement, through the mode register of the SPI agreement of configuration first bare chip for the SPI module of first bare chip is as from the terminal. The mode register of the SPI protocol of the second bare chip is configured in the same mode, so that the SPI module of the second bare chip is used as a host end, and data interaction between the first bare chip and the second bare chip through the improved SPI protocol bus is realized.

With reference to fig. 2, an interconnection communication method for a die is provided in an embodiment of the present disclosure, where the interconnection communication method is applied to a first die as a slave, where the first die is configured to be communicatively connected to a second die as a host through an SPI protocol, where the SPI protocol includes an interrupt request input/output interface and a confirmation character input/output interface, where the method includes:

step 201: and in the idle and sending-enabled state, adjusting a signal of an interrupt request output interface to a high bit to send an interrupt request to the second die.

Step 202: when the signal of the character input interface is confirmed to be high, the slave mode is switched to the master mode.

Step 203: sending communication data to the second die via an SPI protocol.

Step 204: and after all the communication data are sent, adjusting the signal of the interrupt request output interface to a low level, and switching the master mode back to the slave mode.

IN the embodiment of the present application, when a first die as a slave is Idle (Idle) and is enabled to transmit (send _ IN), a signal of an SPI _ ACK _ IN interface needs to be waited for high when a transmission command is executed, indicating that a second die as a master has completed mode switching, at this time, the first die is switched from a slave mode to a master mode and masters the initiative of transmitting communication data, and the communication data is transmitted to the second die through an SPI protocol, that is, after the first die interrupts by transmitting an IRQ and acquires ACK interruption of the second die, the SPI mode is raised to the master, and simultaneously, after the second die as the master transmits an ACK, the SPI mode is lowered to the slave, thereby completing master-slave switching, so that the first die as the slave has a function of actively transmitting data.

By adopting the interconnection communication method for the bare chip provided by the embodiment of the disclosure, through designing the interface of the SPI protocol, the bare chip as a slave end can confirm by using an interrupt signal and a confirmation character according to actual requirements, and switch from a master relationship, so that the bare chip as the slave end has a function of actively sending communication data, and further the bare chip as a master end and the bare chip as a slave end can actively initiate communication data transmission to complete the communication task of bare chip interconnection.

Optionally, as shown in fig. 3, the SPI protocol further includes a system operating state input/output interface; the sending communication data to the second die via the SPI protocol includes:

step 301: and acquiring the communication data from the buffer of the first die in a direct memory access mode under the condition that a signal of a system working state input interface is low.

Step 302: and sending the communication data to the second die through a clock signal output interface, a chip selection signal output interface and a data output interface in the SPI protocol.

Step 303: and adjusting the signal of the system working state output interface to a high position.

In an embodiment of the application, the MCU of the first die configures a command register to start transmission, where the command register includes an SPI _ IRQ _ O enable signal, a data transmission enable signal send _ en, a transmission data base address tx _ addr, and a transmission data length tx _ length, after the command register is configured, the MCU releases resources to generate communication data, and the command of the command register is cached in a buffer (CMDbuffer) of the application, the buffer determines whether to execute the command in the buffer according to whether the signal of the SPI _ BUSY _ I interface is low, and when the first die is switched from the slave mode to the master mode, acquires the communication data from the buffer of the first die by direct memory access, and then transmits the communication data through the SPI _ scout _ O interface, the SPI _ SSN _ O interface, and the SPI _ MOSIOUT _ O interface of the first die, at the same time, the SPI _ BUSY _ O interface signal of the first die is adjusted high, indicating that the first die is tasking with data transfer.

Therefore, by setting an instruction cache mechanism, the MCU only needs to configure a response command register without waiting for SPI _ BUSY handshake, so that the resource occupation of the MCU is reduced, and meanwhile, by adding a logic mechanism for automatically moving data and without externally hanging a DMA module, the direct movement of communication data of the MCU in the specified quantity from the specified memory address of the MCU can be realized, and the operation occupation of the MCU is further reduced.

Optionally, as shown in fig. 4, after all the communication data is sent, the method further includes:

step 401: and generating an interrupt signal of the communication data transmission completion.

Step 402: and sending the interrupt signal of the communication data sending completion to the micro control unit of the first bare chip.

Step 403: and adjusting the signal of the system working state output interface to a low level.

In the embodiment of the application, after all the communication data are completely transmitted, the first die generates an interrupt signal tx _ done for completing the transmission of the communication data, closes the DMA, adjusts the signal of the SPI _ IRQ _ OUT interface to a low level, switches back to the slave mode, and notifies the MCU of the first die that the data transmission is completed. And finishing the influence of the slave-end MCU on tx _ done interruption, and adjusting the signal of the SPI _ BUSY _ O interface to a low position to indicate that the data transmission task to the host end is finished actively at the moment.

Therefore, by increasing the backpressure signal of the SPI _ BUSY interface, whether the die to which the SPI _ BUSY interface belongs is in an idle state or not can be correctly fed back. Only when the communication data is in the idle state, the received communication data is indicated to be processed, and the next transmission can be carried out, so that the situation that the NCU of the previous frame data is not processed and is flushed by the next frame data in the interaction is prevented, and the data security is ensured.

With reference to fig. 5, an interconnection communication method for a die is provided in an embodiment of the present disclosure, and is applied to a first die as a slave inside a bonded chip, where the first die is configured to be communicatively connected to a second die as a host through an SPI protocol, where the SPI protocol includes an interrupt request input/output interface and a system operating state input/output interface, where the method includes:

step 501: and receiving the communication data sent by the second die through the SPI protocol under the condition that the signals of the interrupt request output interface and the signals of the chip selection signal input interface in the SPI protocol are all low.

Step 502: and adjusting the signal of the system working state input interface to a high position.

Step 503: and storing the received communication data into a random access memory of the first die by a direct memory access transmission mode.

Step 504: and after the communication data are completely stored, generating an interrupt signal for completing the communication data receiving, and adjusting a signal of a system working state input interface to a low position.

IN the embodiment of the present application, when receiving communication data transmitted by the second die as the host, the first die as the slave requires that the first die should be IN an Idle (Idle) state and the data transmission enable signal send _ en is not IN an active state, or that the data transmission enable signal send _ en is IN an active state and the signal of the SPI _ IRQ _ O interface is low, which means that the first die does not need to switch to the host, at this time, the first die detects that the signal of the SPI _ SSN _ IN interface for receiving a host chip selection is low, and completes the reception of the communication data through the SPI _ SCKIN _ I interface and the SPI _ MOSIIN _ I interface, and at the same time, the DMA unit is turned on to transmit the received communication data through direct memory access, and writes the received communication data into the RAM of the first die, and at the same time, adjusts the signal of the busjy _ I interface of the first die to be high, to indicate that the first die is tasked with data transmission. After the communication data are completely stored, generating an interrupt signal rx _ done for completing receiving the communication data, and using an interrupt to notify the MCU of the first die that the receiving of the data is completed, where the MCU of the first die can process the data, and the MCU of the first die starts to process the received communication data in response to the rx _ done interrupt signal, and simultaneously adjusts the signal of the SPI _ BUSY _ I interface to a low level, indicating that the task of receiving the host data from the slave is completed.

With reference to fig. 6, an interconnection communication method for a die is provided in an embodiment of the present disclosure, and is applied to a second die serving as a host inside a bonded chip, where the second die is configured to be communicatively connected to a first die serving as a slave through an SPI protocol, where the SPI protocol includes an interrupt request input/output interface and a confirmation character input/output interface, where the method includes:

step 601: when the signal input by the interrupt request is high, the master mode is switched to the slave mode.

Step 602: and adjusting a signal of an acknowledge character output interface to a high position so as to send an acknowledge character to the first die.

Step 603: and receiving communication data sent by the first die through an SPI protocol.

Step 604: and after all the communication data are received, adjusting the signal of the confirmation character output interface to be at a low level, and switching the slave mode back to the master mode.

In the embodiment of the present application, when the second die as the host is in an Idle (Idle) state, and the second die detects that the signal of the SPI _ IRQ _ I interface is high, it indicates that the first die as the slave needs to actively upload communication data, at this time, the second die switches from the host mode to the slave mode, and adjusts the signal of the SPI _ ACK _ O interface to high, which indicates that the second die has completed the mode switching and is ready to receive. And further, the communication data sent by the first die is received through the SPI protocol, that is, the first die acquires the ACK interrupt of the second die by sending an IRQ interrupt, and then the SPI mode is increased to the master, and meanwhile, the SPI mode is decreased to the slave after the ACK is sent by the second die serving as the master, so that master-slave switching is completed, and the second die serving as the master has a function of receiving data.

Optionally, as shown in fig. 7, the SPI protocol further includes a system operating state input/output interface; the receiving, by the SPI protocol, the communication data sent by the first die includes:

step 701: and under the condition that a signal of a chip selection input interface in the SPI protocol is low, receiving the communication data sent by the first die through a clock input interface, the chip selection input interface and a data input interface of the SPI protocol.

Step 702: and adjusting the signal of the system working state input interface to a high position.

Step 703: and storing the communication data into a random access memory of the first die by a direct memory access transmission mode.

In the embodiment of the application, when the signal of the SPI _ SSN _ I interface of the second die is low, the data reception is completed through the SPI _ SCKIN _ I interface, the SPI _ SSN _ I interface, and the SPI _ MOSIIN _ I interface, and at the same time, the signal of the SPI _ BUSY _ I interface of the second die is adjusted to a high level to indicate that the host is performing a data transmission task, and the DMA unit is turned on at the same time, and the communication data is stored in the RAM of the first die by a direct memory access transmission method.

Therefore, by adding a logic mechanism for automatically moving data, a DMA module is not required to be externally hung, the MCU can directly move the communication data with the specified quantity from the memory address specified by the MCU, and the calculation occupation of the MCU is further reduced.

Optionally, as shown in fig. 8, after all the communication data are received, the method further includes:

step 801: and generating an interrupt signal that the communication data reception is completed.

Step 802: and sending the interrupt signal of the communication data receiving completion to the micro control unit of the second bare chip.

Step 803: and adjusting the signal of the system working state input interface to a low level.

In the embodiment of the present application, after all the communication data are received, the second die generates an interrupt signal rx _ done indicating that the transmission of the communication data is completed, and notifies the MCU of the second die that the data reception is completed, so that the data processing can be performed. And the MCU of the second bare chip responds to the rx _ done interrupt signal to process the received communication data, and meanwhile, the signal of the SPI _ BUSY _ I interface of the second bare chip is adjusted to be at a low position, which indicates that the task of receiving the data from the slave at the host end is completed.

Thus, by adding the SPI _ BUSY signal, if the received data is not completed, the opposite end is not allowed to send the data again, the unprocessed data is prevented from being washed away, and the safety of data transmission is ensured.

With reference to fig. 9, an interconnection communication method for a die is provided in an embodiment of the present disclosure, and is applied to a second die serving as a host inside a bonded chip, where the second die is configured to be communicatively connected to a first die serving as a slave through an SPI protocol, where the SPI protocol includes an interrupt request input/output interface and a confirmation character input/output interface, where the method includes:

step 901: and acquiring communication data from the buffer of the second die in a direct memory access transmission mode under the condition that the signals of the interrupt request output interface in the SPI protocol and the signals of the system working state input interface are all low.

Step 902: and adjusting the signal of the system working state output interface to a high position.

Step 903: sending the communication data to the first die via an SPI protocol.

Step 904: and after the communication data are completely sent, generating an interrupt signal for finishing sending the communication data, and adjusting a signal of a system working state output interface to a low level.

In the embodiment of the present application, when communication data needs to be sent to the first die as a slave, the second die as a host requires that the second die should be in an Idle state and a signal of the SPI _ IRQ _ I interface is low, which indicates that the first die does not need to be switched to the host, which indicates that the first die can receive the data, at this time, the MCU of the second die configures the command register to start transmission, where the command register includes an SPI _ IRQ _ O enable signal, a data transmission enable signal send _ en, a transmission data base address tx _ addr, and a transmission data length tx _ length, after the command register is configured, the MCU releases a resource to generate the communication data, and a command of the command register is cached in a buffer (CMDbuffer) of the present application, and the buffer determines whether to execute a command in the buffer according to whether the signal of the SPI _ BUSY _ I interface is low, if the data transmission enable signal send _ en is in an active state and the signal of the SPI _ BUSY _ I interface is low, the communication data is acquired from the buffer of the second die in a direct memory access manner, and then the communication data is transmitted through the SPI _ SCKOUT _ O interface, the SPI _ SSN _ O interface, and the SPI _ MOSIOUT _ O interface of the second die, and the signal of the SPI _ BUSY _ O interface of the second die is adjusted to high, indicating that the first die is performing a data transmission task. After the communication data are completely sent, the interrupt signal rx _ down of the communication data sending is completed, the DMA is closed, and the signal of the SPI _ BUSY _ OUT interface is adjusted to be at a low position, which indicates that the data transmission task to the slave is completed at the moment.

As shown in fig. 10, an interconnected communication system for dies includes a first die as a slave and a second die as a host, wherein:

the first die is configured to be in communication connection with the second die through an SPI protocol, wherein the SPI protocol comprises an interrupt request input/output interface, a confirmation character input/output interface and a system working state input/output interface;

In summary, the present application provides an improved SPI protocol based on DMA and a design of an interface thereof, which can complete an interconnection work between dies, the improved SPI protocol includes all logic designs of a master and a slave, and the master and the slave identities of the communication SPI protocol can be implemented through register configuration. In the application, the first bare chip serving as the slave end and the second bare chip serving as the host end can perform interrupt interaction, the mode of the first bare chip is switched to the host end, and information is actively sent. The method and the device have the advantages that the logic mechanism for automatically moving the data is added, a DMA module is not required to be hung externally, and the data with the quantity specified by the MCU can be directly moved from the memory address specified by the MCU. This application has increased SPI _ BUSY's backpressure signal, whether the interface of the SPI protocol of the feedback belonged bare core that can be correct is in idle state, only when being in idle state, indicates that the data received has been handled, just can carry out transmission on next step to in preventing the interaction, last frame data MCU still does not handle, is washed away by next frame data, has guaranteed data safety. This application has still set up command cache mechanism, and MCU only needs the command register of configuration response, need not to wait for SPI _ BUSY to handshake, reduces MCU's resource occupation. The data transmission system is also provided with three interfaces of the data lines, so that the data transmission efficiency can be increased in multiples.

An embodiment of the present disclosure provides an integrated package chip including an interconnected communication system for a die as described herein.

The disclosed embodiments provide a storage medium storing computer-executable instructions configured to perform the above-described method for consumable purchase.

The storage medium described above may be a transitory computer-readable storage medium or a non-transitory computer-readable storage medium.

The technical solution of the embodiments of the present disclosure may be embodied in the form of a software product, where the computer software product is stored in a storage medium and includes one or more instructions to enable a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method of the embodiments of the present disclosure. And the aforementioned storage medium may be a non-transitory storage medium comprising: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes, and may also be a transient storage medium.

The above description and drawings sufficiently illustrate embodiments of the disclosure to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. The examples merely typify possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in or substituted for those of others. Furthermore, the words used in the specification are words of description only and are not intended to limit the claims. As used in the description of the embodiments and the claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, the term "and/or" as used in this application is meant to encompass any and all possible combinations of one or more of the associated listed. Furthermore, the terms "comprises" and/or "comprising," when used in this application, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Without further limitation, an element defined by the phrase "comprising an …" does not exclude the presence of other like elements in a process, method or apparatus that comprises the element. In this document, each embodiment may be described with emphasis on differences from other embodiments, and the same and similar parts between the respective embodiments may be referred to each other. For methods, products, etc. of the embodiment disclosures, reference may be made to the description of the method section for relevance if it corresponds to the method section of the embodiment disclosure.

Those of skill in the art would appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software may depend upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments. It can be clearly understood by the skilled person that, for convenience and brevity of description, the specific working processes of the system, the system and the unit described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the embodiments disclosed herein, the disclosed methods, articles of manufacture (including but not limited to systems, devices, etc.) may be implemented in other ways. For example, the above-described system embodiments are merely illustrative, and for example, the division of the units may be merely a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, systems or units, and may be in an electrical, mechanical or other form. The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to implement the present embodiment. In addition, functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. In the description corresponding to the flowcharts and block diagrams in the figures, operations or steps corresponding to different blocks may also occur in different orders than disclosed in the description, and sometimes there is no specific order between the different operations or steps. For example, two sequential operations or steps may in fact be executed substantially concurrently, or they may sometimes be executed in the reverse order, depending upon the functionality involved. Each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Claims

1. An interconnection communication method for a die, applied to a first die as a slave, wherein the first die is configured to be communicatively connected with a second die as a master through an SPI protocol, wherein the SPI protocol includes an interrupt request input/output interface and a confirmation character input/output interface, and wherein the method includes:

sending communication data to the second die via an SPI protocol;

2. The communication method according to claim 1, wherein the SPI protocol further comprises a system operating status input/output interface; the sending communication data to the second die via the SPI protocol includes:

under the condition that a signal of a system working state input interface is low, the communication data is obtained from a buffer of the first bare chip in a direct memory access mode;

sending the communication data to the second die through a clock signal output interface, a chip selection signal output interface and a data output interface in an SPI protocol;

and adjusting the signal of the system working state output interface to a high position.

3. The communication method according to claim 2, further comprising, after the transmission of all the communication data is completed:

generating an interrupt signal for completing the transmission of the communication data;

sending an interrupt signal of the communication data sending completion to a micro control unit of the first bare chip;

and adjusting the signal of the system working state output interface to a low level.

4. An interconnection communication method for a die, applied to a second die as a host side inside a sealed chip, wherein the second die is configured to be in communication connection with a first die as a slave side through an SPI protocol, and the SPI protocol comprises an interrupt request input/output interface and a confirmation character input/output interface, wherein the method comprises:

receiving communication data sent by the first die through an SPI protocol;

5. The communication method according to claim 4, wherein the SPI protocol further comprises a system operating status input/output interface; the receiving, by the SPI protocol, the communication data sent by the first die includes:

under the condition that a signal of a chip selection input interface in the SPI protocol is low, receiving communication data sent by the first die through a clock input interface, the chip selection input interface and a data input interface of the SPI protocol;

and storing the communication data into a random access memory of the first die by a direct memory access transmission mode.

6. The communication method according to claim 5, further comprising, after the reception of all the communication data is completed:

generating an interrupt signal that the communication data reception is completed;

sending an interrupt signal of the communication data receiving completion to a micro control unit of the second die;

and adjusting the signal of the system working state input interface to a low level.

7. An interconnection communication method for a die, applied to a first die as a slave inside a combined chip, wherein the first die is configured to be communicatively connected with a second die as a host through an SPI protocol, and the SPI protocol includes an interrupt request input/output interface and a system operating state input/output interface, wherein the method includes:

8. An interconnection communication method for a die, applied to a second die as a host side inside a sealed chip, wherein the second die is configured to be in communication connection with a first die as a slave side through an SPI protocol, and the SPI protocol comprises an interrupt request input/output interface and a confirmation character input/output interface, wherein the method comprises:

sending the communication data to the first die via an SPI protocol;

9. An interconnected communication system for a bare chip comprises a first bare chip as a slave end and a second bare chip as a host end, wherein the first bare chip is configured to be in communication connection with the second bare chip through an SPI protocol, and the SPI protocol comprises an interrupt request input/output interface, a confirmation character input/output interface and a system working state input/output interface;

10. An integrated package chip comprising the interconnected communication system for dies of claim 9.