JP2000267928A - Memory control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory control device capable of sharing a memory bus, reducing the number of buses and securing a fixed data transfer rate. SOLUTION: The memory control device is provided with memory controllers 9a, 9b for mutually monitoring and controlling data flowing in a shared bus 7 in order to evade the interference of data in the bus 7. Exclusive right is applied to plural memory controllers 9a, 9b so that data of fixed quantity can be alternately transferred to these controllers 9a, 9b through the bus 7 or preferentially transferred to either one of the controllers 9a, 9b. Consequently the number of I/O pins to/from a memory 6 is reduced and the interference of data in the bus 7 is avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a memory control device, and more particularly to a memory control device applied to an image processing device such as a digital multifunction peripheral.

[0002]

2. Description of the Related Art In recent years, an image processing apparatus having a plurality of functions such as a copy function, a facsimile function, and a printer function has been spreading.
Hardware resources are reduced by processing duplicated functions in the same processing block.

On the other hand, by using digital processing, various kinds of image editing such as image rotation, black and white inversion, synthesis, and superposition can be performed. To perform these image editing operations, an image memory is indispensable. However, in the case of the image processing apparatus, since various functions must be executed simultaneously, it is necessary to flexibly cope with any data flow. Accordingly, Japanese Patent Application No. 10-14007 filed by the present applicant has
An image processing apparatus as described in No. 4 has been proposed.

This image processing apparatus, as shown in FIG.
It basically has a function of outputting image data input from the scanner 1 as image data input means from the printer 2 as image data output means. In this image processing apparatus, for example, image data subjected to predetermined processing by the local memory controller 9a (or 9b) is stored in the local memory 6, and the image data is output via the local memory controller 9a (or 9b). It can be transferred to the means 2 or another processing means.

Further, the image data obtained from the image data input means as described above is encoded (compressed) by the encoder 3 and temporarily written into the code data memory 5, and the image data is decoded (decompressed) and decoded. In the above transfer control, the DMA (direct memory access) controller 7 (8) executes the transfer on the encoder 3 side and the transfer on the decoder 4 side. I have.

Further, a data bus bridge 10 is provided for forming a data path between the image input means, the image output means, the local memory 6, and the code data memory 5. Here, the code data memory 5 is merely assumed to be a semiconductor memory here, but it goes without saying that a nonvolatile memory such as a hard disk may be further connected via the semiconductor memory.

That is, in the above image processing apparatus, for example, copy processing (data transfer processing from a scanner as an image input means to a printer as an output means) and reception of print data from an external personal computer or the like (a print controller as an input means) , Data storage via the code memory 5) can be performed simultaneously by the path forming process of the data bus bridge 10, and one of the processes can be performed by waiting for a long time in order. It is possible to prevent an error.

[0008]

According to the configuration of the image processing apparatus, the image processing in the local memory 6 is performed by using, for example, the local memory controller 9b to process the image data of the first page already processed in the local memory 9. The image data of the second page is written to the local memory via the local memory controller 9a while being read and transferred to an output means such as a printer.
Therefore, two sets of input and output memory buses 7a and 7b are required, and if an attempt is made to make an LSI, the number of input / output pins will increase as it is, which directly affects the cost of the LSI and the size of the package.

Further, sharing the two sets of memory buses can reduce the number of input / output pins. However, simply sharing the memory bus not only causes interference of input / output image data but also reduces the number of input / output image data. It is possible that the specified data transfer rate cannot be obtained. That is, it is necessary to input and output data at a constant transfer rate such as a scanner or a printer. In this case, image data input at a constant rate cannot be written to a local memory at the rate, or However, image data that needs to be output at a predetermined rate may not be able to secure the predetermined rate, so that image loss may occur.

An object of the present invention is to provide a memory control device capable of coping with the above situation, sharing the memory bus, reducing the number of buses, and securing the constant data transfer rate. It is assumed that.

[0011]

The present invention employs the following means to achieve the above object.

That is, the present invention is based on a memory device in which a plurality of memory controllers 9a and 9b are connected to one memory 6 via a shared bus 7.

In the memory device, the present invention is provided with the memory controllers 9a and 9b for mutually monitoring and controlling data flowing through the shared bus in order to avoid data interference on the shared bus 7.

The plurality of memory controllers 9a, 9b
Means that the data transfer is performed in predetermined units with a predetermined data amount as one unit while alternately using the shared bus 7. Thereby, the number of input / output pins to the memory 6 can be reduced, and at the same time, the data interference on the shared bus 7 is eliminated.

The above two memory controllers 9
If the arbiter 11 for arbitrating the data transfer by the a and 9b is provided, the video signal requesting means 12 informs the arbiter that one of the plurality of memory controllers 9a and 9b requires a predetermined data transfer rate. To the designated memory controller 9a,
9b can transfer a predetermined amount of data.

The present invention comprises an image data input means and an output means for outputting the input image data, wherein a predetermined processing is performed on the memory while the image data is transmitted from the image data input means to the output means. It works effectively when applied to an image processing apparatus that performs the following.

[0017]

Embodiments of the present invention will be described below with reference to the accompanying drawings. (Embodiment 1) FIG. 1 is a block diagram when a memory control device of the present invention is applied to an image processing device.

The configuration shown in FIG. 1 is basically the same as the conventional configuration described with reference to FIG. 7, except that memory buses 7a and 7b serving as data input / output paths from data bus bridge 10 to local memory 6 are provided. 7b is connected to the shared bus 7 on the local memory side of the local memory controllers 9a and 9b, and input / output to / from the local memory 6 is performed via the shared bus 7. Further, in order to avoid interference of input data and output data from the local memory 6 on the shared bus 7, the local memory controllers 9a, 9
b has a function of monitoring the flow of data in both memory buses. Although two memory buses are described here as an example, it goes without saying that two or more memory buses may be used.

The operation of the first embodiment will be described with reference to FIG.

First, image data obtained from the scanner 1 as image input means is encoded by the encoder 3 and stored in the code data memory 5. Alternatively, if storage is necessary, the data is temporarily stored in a hard disk (not shown). As described above, the image data of the first page stored in the code data memory 5 (after being read out to the code data memory 5 when stored in the hard disk) is expanded by the decoder 4 and subjected to, for example, rotation processing by the memory controller 9a. And stored in the local memory 6. When the image data of the first page is stored in the local memory 6, the memory controller 9b
Then, the data is read out and other processing, for example, is printed by the printer 2 as an image output means. Simultaneously with the reading process of the first page, the image data of the second page is expanded by the decoder 4, rotated by the memory controller 9 a and stored in the local memory 6.

At this time, since the memory controller 9a and the memory controller 9b simultaneously use the shared bus 7, arbitration of the shared bus 7 is required.

FIG. 2 is a timing chart of control signals between the memory controller 9a and the memory controller 9b at the time of arbitration of the shared bus 7. The state 21 in FIG.
Occupied state (bus use right).

The status signal 22 (FIG. 2 (b)) indicates the use state of the shared bus 7 of the memory controller 9a, and the status signal 24 (FIG. 2 (d)) indicates the status of the memory controller 9b.
Is a signal indicating the use state of the shared bus 7 of FIG. The request signal 23 (FIG. 2 (c)) and the request signal 25 (FIG. 2 (e)
) Are signals for notifying the partner memory controller of a shared bus use request when the shared bus 7 is to be used.

First, when the memory controller 9a is ready for data transfer, the request signal 23 is enabled (High: hereinafter simply referred to as H) (step 1A). At the next clock (see FIG. 2 (f)), the status signal 24 of the memory controller 9b is disabled (Low: hereinafter simply referred to as L), that is, the memory controller 9a uses the shared bus 7 If not, the request signal 23 is set to L and the status signal 22 is set to H to acquire the right to use the bus (step 2A). When the right to use the bus can be acquired in this way, the memory controller 9a executes data transfer of a predetermined data amount, and when the data transfer is completed, sets the status signal 22 to L and abandons the right to use the bus (step 5A). .

If the memory controller 9b sets the request signal 25 to H while the memory controller 9a occupies the shared bus 7, the memory controller 9b changes the status signal 22 of the memory controller 9a in the next step. After confirmation, if this is in the H state, the request signal 25 is held in the H state (step 3).
A). In this state, upon detecting that the status signal 22 of the memory controller 9a has become L, the memory controller 9b sets the status signal 24 to H and the request signal 25 to L to acquire the bus use right (step 6A). ).

Also, as long as the memory controller 9a is also ready for data transfer, the request signal 23 is set to H in the next step (step 6A) after relinquishing the right to use the bus.
Then, the other party is notified that the right to use the shared bus 7 is requested. In the next step (step 7A), since the status signal 24 is H, the memory controller 9a holds the request signal 23 at H until the right to use the shared bus 7 is released.

In the same manner, the memory controller 9a or the memory controller 9b that has acquired the right to use the shared bus 7 always releases the right to use the shared bus 7 once, and the other memory controller releases the right to use the shared bus 7. Check if you are requesting. With such a configuration, the right to use the shared bus 7 can be distributed fairly.

Next, the two memory controllers 9
The operation when the request signals output from a and 9b simultaneously become H will be described.

First, when the memory controller 9b is ready for data transfer, the request signal 25 is set to H (step 13A). If the status signal 22 of the memory controller 9a is L at the next clock, the request signal 25 of the memory controller 9b is set to L and the status signal 24 is set to H to acquire the right to use the bus (step 14).
A). When the data transfer of the predetermined data amount is completed, the memory controller 9b sets the status signal 24 to L, and relinquishes the right to use the bus (step 17A). Next, the memory controller 9b sets the request signal 25 to H after a certain period of time, for example, after setting the request signal 25 to L, and at the same time, the memory controller 9a also sets the request signal 23 to H (step S1). 21
A).

In this case, if priority is given to the memory controller which has not been used immediately before, the right to use the shared bus 7 is given to the memory controller 9a.
Therefore, in the next step, the memory controller 9a sets the status signal 22 to H and the request signal 23 to L, and acquires the right to use the bus (Step 22A).

The memory controller 9b holds the state in which the request signal 25 is set to H. In this state, when the data transfer of a predetermined amount of data is completed, the memory controller 9a sets the status signal 22 to L and sets the right to use the bus. Abandon (step 25A). Memory controller 9b
Confirms that the shared bus 7 has been opened at this point,
The right to use the bus is acquired (step 26A).

Therefore, it takes the longest time to acquire the right to use the shared bus 7 when both request signals collide. In the present embodiment, for example, the memory controller 9b sends the request signal 25 to H
The longest time until the right to use the bus is acquired after 42
Is equivalent to 5 steps. However, conversely, if the request signal is output in consideration of this value, the shared bus 7 can be occupied within the time 41 necessary to secure the minimum data transfer rate in the memory controller 9b.
The H period of each of the status signals 22 and 24 is set in advance based on the amount of data transferred by one data transfer.

As described above, in FIG. 2, the case where both the memory controllers 9a and 9b request the right to use the shared bus 7 has been described, but in FIG. 3, only one memory controller requests the right to use the shared bus 7. Will be described.

First, when the memory controller 9a is ready for data transfer, the request signal 23 shown in FIG. 3C is set to H (step 1B). Figure 3 with the next clock
(e) Status signal 2 of the memory controller 9b
If 4 is L, the request signal 23 is set to L, the status signal 22 shown in FIG. 3B is set to H, and the memory controller 9a acquires the bus use right (step 2B). The memory controller 9a that has acquired the right to use the bus has completed the status signal 2 when the data transfer of the predetermined data amount is completed.
2 to L, abandoning the right to use the bus (step 7)
B).

In the next step, if the status signal 24 of the memory controller 9b shown in FIG. 3D is L, the memory controller 9a sets the request signal 23 to L and the status signal 22 to H to acquire the right to use the bus (FIG. 3D). Step 8B).

Similarly, in the next step after releasing the right to use the shared bus 7, if the other memory controller has not requested the right to use the shared bus 7, the last time the right to use the shared bus 7 is used. , So that the memory controller having acquired the right to use the shared bus 7 can be continuously acquired. With such a configuration, when the shared bus 7 is vacant, the shared bus 7 can be continuously used, and resources can be effectively used.

With the above-described configuration, even when a complicated application accesses the local memory at the same time, data transfer to the local memory can be efficiently performed without falling below a predetermined minimum data transfer rate. Can be realized. (Embodiment 2) Next, Embodiment 2 of the present invention will be described with reference to FIG.

The configuration of the second embodiment has a configuration in which an arbiter 11 and a video signal request register 12 are added to the configuration of the first embodiment. Here, the video signal means data that must always be transferred at a constant rate, and includes, for example, output data to a printer, input data from a scanner, and the like.

The arbiter 11 is a memory controller 9
a and the memory controller 9b arbitrate for the right to use the shared bus 7 when trying to secure the right to use the shared bus 7 at the same time.
2 is a video request signal to the arbiter 11;
Which video data should be transferred at what rate and where should be notified in advance. Further, the video signal request register 12 receives and stores the transfer priority of image data, the minimum data transfer rate of each image data, the data amount of image data, and the like from a higher-level controller.

Here, the operation using the arbiter 11 will be described with reference to FIG. FIG. 5 shows the memory controller 9a and the memory controller 9b during arbitration of the shared bus 7.
FIG. 6 is a timing chart of a control signal between the arbiter and the arbiter; The state signal 31 shown in FIG. 5A indicates the occupation state of the shared bus 7.

From the arbiter 11, each memory controller 9a,
The enable signal 32 (FIG. 5 (b)) and the enable signal 34 (FIG. 5 (d)) output to the memory controller 9b are shared by the memory controller 9a and the shared bus 7 of the memory controller 9b, respectively.
The memory controller can use the shared bus 7 when this signal is H. Request signal 33 (FIG. 5 (c)), request signal 35
(FIG. 5E) are signals for transmitting a shared bus use request from the memory controllers 9a and 9b to the arbiter 11 when the shared bus 7 is used.

The mask signal 36 (FIG. 5 (f)) is an internal signal of the arbiter, and means that a request signal other than the controller designated to secure a constant transfer rate is suspended. .

The enable signals 32 and 34 are formed based on the mask signal 36 and the request signals 33 and 35. For example, in the following example, the mask signal 36 is H
The request signal 33 of the memory controller 9a
Becomes H, the enable signal 32 does not become H. However, when the mask signal 36 is H, the memory controller 9
When the request signal 35 of b becomes H, the enable signal 34 always becomes H. That is, the memory controller 9b
Is given priority. It should be noted that both the request signals 33 and 35 are accepted by the arbiter 11 while the mask signal 36 is L.

As an operation example, a case similar to the first embodiment will be described. In this operation example, the output of the memory controller 9b is the printer 2, and the printer 2 needs to input the bitmap data at a constant data transfer rate.
Although a line buffer for more than lines is provided, it is necessary to control the input to the printer device so that at least the line buffer does not become empty.
Therefore, the following description will be made assuming that the memory controller 9b is an input side to a device that requires a video signal such as a printer.

First, when the memory controller 9a is ready for data transfer, it sets the request signal 33 to H to notify the arbiter 11 (step 1C). In this state, the arbiter 11 sets the enable signal 32 to the memory controller 9a to H if the shared bus 7 is vacant (that is, if the transfer process by the memory controller 9b is not executed) (Step 2C). The memory controller 9a confirms that the enable signal 32 has become H, and secures the right to use the shared bus 7 (step 3C).

The memory controller 9a immediately sets the request signal 33 to L when the transfer of the predetermined amount of data is completed (step 5C). Upon confirming this, the arbiter immediately sets the enable signal 32 to L and sets the shared bus 7
Is released (step 6C). On the other hand, the memory controller 9b similarly sets the request signal 35 to H when data transfer preparation is completed.

In the arbiter 11, when the memory controller 9a is using the shared bus 7, the enable signal 34 for the memory controller 9b is set to H at the same time when the data transfer of the predetermined amount of data in the memory controller 9a ends ( Step 6C). The memory controller 9b confirms that the enable signal 32 has become H, and secures the right to use the shared bus 7 (step 7C).

When the transfer of the predetermined amount of data is completed, the memory controller 9b immediately sends the request signal 35
To L (step 9C). Upon confirming this, the arbiter 11 immediately sets the enable signal 34 to L and releases the right to use the shared bus 7 (step 10C).

Here, it is necessary for the memory controller 9b to satisfy a predetermined data transfer rate as described above. That is, the arbiter 11 is notified from the video signal request register 12 which data should be transferred to which rate at what rate, and based on the notification, the arbiter 11 transmits the mask signal 36 at a predetermined cycle. H state. While the mask signal 36 is H, the request signal 33 output from the memory controller 9a is suspended, and only the request signal 35 output from the memory controller 9a is accepted by the arbiter 11.

First, when the memory controller 9a is ready for data transfer, the request signal 33 is set to H (step 15C). At this time, the arbiter 11 sends the request signal 3 from the memory controller 9a in the next step.
When the mask signal is H at this time, the request signal 33 is suspended.

In the meantime, the request signal 35 from the memory controller 9b becomes H (step 16C), and the arbiter 11 detects that the request signal 35 has become H, and sets the enable signal 34 for the memory controller 9b to H. (Step 17C). In the memory controller 9b, when the transfer of the predetermined amount of data is completed,
The request signal 35 is set to L to immediately release the right to use the shared bus 7 (step 20C). Arbiter 11
Confirms this and sets the enable signal 34 to L, and sets the enable signal 32 to the memory controller 9a to H (step 21C). The memory controller 9a confirms that the enable signal 32 has become H, and secures the right to use the shared bus 7 (step 22).
C).

When the mask signal 36 is H, it is not always necessary to output the request signal 35 from the memory controller that handles video data (in this case, the memory controller 9b). In this mode, data transfer is alternately performed as described in the first embodiment. Although the present embodiment shows an example in which two memory controllers are used, the same effect can be obtained even if the number of memory controllers further increases.

With the above configuration, the memory controller 9b can compete for the shared bus 7 without breaking a substantially constant data transfer rate. still. The cycle of the mask signal 36 and the period of H are set in advance according to a desired rate. Further, the H period of each of the enable signals 32 and 34 is the same as the status signals 22 and 24 in the first embodiment.
It is set in advance according to the amount of data transferred in one data transfer. Embodiment 3 An image processing apparatus according to Embodiment 3 of the present invention will be described with reference to FIG.

The image processing apparatus according to the third embodiment is similar to the image processing apparatus shown in FIG.
As compared with the image processing apparatus of the first embodiment shown in FIG. 1, a printer controller (hereinafter referred to as RPC) 51 as an input means and a FAX modem 52 are added.

The RPC 51 receives a print command from a computer or the like via a network or a local interface, and develops the command into bitmap data.

The facsimile modem 52 is means for transmitting and receiving facsimile data via a public line, an extension or, more recently, the Internet. Facsimile is generally M
Since code data such as H and MR are used, it is described in FIG. 6 as being connected to the same CPU bus 54 as the code data memory 5, but the FAX modem itself has an encoding / decoding function. In such a case, data can be input to the data bus bridge 10 as in the case of the RPC 51.

The encoder 3 and the decoder 4 are connected to a code data bus 53, and the code data memory 5 is connected to a CPU bus 5
4 are respectively connected to the code data bus 53 and C
The PU bus 54 is connected via a bus bridge 55.

Next, facsimile transmission will be described with reference to FIG. First, an original is read from the scanner 1 and encoded by the encoder 3, and the encoded data bus 5
3, stored in the code data memory 5 via the bus bridge 55 and the CPU bus 54.

The code data in the code data memory 5 is FAX
It is transmitted to the outside through the modem 52. At this time, it is necessary to change the image size and the encoding method according to the capability of the facsimile of the other party, but if the FAX modem 52 incorporates these functions,
If not, the decoder 4 once converts the data into bitmap data, and the data bus bridge 1
Then, the encoder 3 performs encoding conversion again via 0 and transmits the result.

In the case of facsimile reception, first, FA
The code data received from X modem 52 is stored in code data memory 5. Upon completion of the reception, the code data is developed into bitmap data by the decoder 4 and printed when the printer 2 is idle. At this time, if rotation or enlargement is necessary, the image is first developed on the local memory 6 and then printed.

In the case of printing from a personal computer, a print command is received by the RPC 51, encoded by the encoder 3, and stored in the code data memory 5. In anticipation of when the printer 2 is idle, the code data is expanded by the decoder 4 and printed by the printer 2.

Although both the RPC 51 and the FAX modem 52 are described here as being provided, it is apparent that the above-described effects can be obtained even with a device provided with only one of them. It is.

In each of the above embodiments, the case where two memory controllers are used has been described, but it goes without saying that a configuration may be employed in which more memory controllers are controlled while monitoring each other.

[0064]

As described above, according to the memory control device of the present invention, the memory controller is connected to the memory via the shared bus, and when the data transfer between the memory and the memory is required, the predetermined value can be obtained. Data transfer is performed with the data amount as one unit, and the memory bus is opened for each data transfer of one unit. When the plurality of memory controllers request data transfer, mutual transfer processing by one unit interferes. In order not to use a shared bus. Therefore, even if a complicated application accesses the memory at the same time, a single memory bus can be shared and a predetermined data transfer rate can be satisfied only by optimizing the size of the data transfer unit. Memory access such as
Further, when the memory bus is free, high-speed data transfer can be performed by effectively utilizing the memory bus.

Further, by giving priority to the video signal by masking data transfer requests other than the video signal so that the video signal is prioritized at a predetermined timing, even an input / output requesting a constant data transfer rate can be performed. , Transfer data without interruption while sharing the memory bus,
It is possible to realize a combined operation.

Further, by combining a printer controller, a facsimile, and the like, it is possible to realize a larger and more complex operation system.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image processing device according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing an operation in the first embodiment.

FIG. 3 is a timing chart showing another operation in the first embodiment.

FIG. 4 is a block diagram illustrating a configuration of an image processing device according to a second embodiment of the present invention.

FIG. 5 is a timing chart showing an operation in the second embodiment.

FIG. 6 is a block diagram illustrating a configuration of an image processing device according to a third embodiment of the present invention.

FIG. 7 is a block diagram illustrating a configuration of a conventional image processing apparatus.

[Explanation of symbols]

 1: Scanner 2: Printer 3: Encoder 4: Decoder 5: Code data memory 6: Local memory 7: Shared bus 9a, 9b: Local memory controller 10: Data bus bridge 11: Arbiter 12: Video signal request register

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Taketo Yamaguchi 1006 Kadoma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (72) Inventor Yuji Okada 1006 Odaka Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co. 72) Inventor Naoki Takahashi 1006 Kadoma Kadoma, Kadoma City, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (72) Inventor Joji Tanaka 1006 Odaka Kadoma, Kadoma City, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. 1006 Kadoma Kadoma Matsushita Electric Industrial Co., Ltd. F-term (reference) 5B047 AA30 EA01 EB01 EB17 5B060 CD14 KA01 KA04 5C073 AA03 BA03 BB09 BD02 CA01 CE01

Claims (7)

[Claims] In a memory device in which a plurality of memory controllers are connected to a single memory via a shared bus, in order to avoid data interference on the shared bus, data flowing through the shared bus is exchanged. A memory controller, comprising: a memory controller for monitoring and controlling the data. 2. The memory control device according to claim 1, wherein said plurality of memory controllers execute data transfer in predetermined units each having a predetermined data amount as one unit while alternately using a shared bus. 3. An arbiter for arbitrating data transfer between the two memory controllers, and when any of the plurality of memory controllers requires a predetermined data transfer rate, transmits the data transfer rate to the arbiter. 2. The memory control device according to claim 1, further comprising a video signal requesting unit that performs the operation. 4. The arbiter preferentially allocates a shared bus to a memory controller specified by the video signal requesting means at predetermined intervals, and guarantees a predetermined data transfer rate to the memory controller. The memory control device according to claim 1. 5. An image data input means and an output means for outputting the input image data, wherein predetermined processing is performed on the memory while the image data is transmitted from the image data input means to the output means. 2. The memory control device according to claim 1, wherein the memory control device is applied to an image processing device. 6. An image data input means, comprising: a scanner;
6. The memory device according to claim 5, wherein the memory device is at least one of a facsimile receiver, a print controller for inputting data print data from a computer, and a network receiver for inputting data via a network. 7. The memory control device according to claim 6, wherein said output means is one of a printer, a facsimile transmitter, and a network transmitter for transferring data to another device via a network.