JPH10262070A - Data-processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform efficient bus control at the time of transferring the command and data of a packet form by using a common bus with respect to a data processing system. SOLUTION: In this data-processing system, plural equipment mutually transmit and receive packets by using the common bus, the respective equipment output the use request signals of the common bus of predetermined priority prior to packet transmission and a bus arbiter is provided with a control means for mediating the use request signals of the common bus, deciding the using equipment of the common bus corresponding to the priority and granting a permission. The respective equipment are provided with a means for outputting the use request signals of the common bus and outputting information for indicating the transfer opposite party, the bus arbiter is provided with a means for receiving the information and a packet reception side equipment is provided with a means for reporting the information of the state or the like to the bus arbiter or/and all the equipment, when the buffer for reception command packets of the present equipment is busy and is in a state, incapable of receiving a new command packet.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a common bus
The present invention relates to a data processing system using a common bus (CBUS), and particularly to a means for efficient packet transfer in a data processing system that transfers packet-format commands and data using the common bus (CBUS). It relates to control means.

[0002] With the recent increase in the scale of data processing, the demand for high-performance data processing systems is increasing. As a means of high performance, a low-cost and high-performance transfer capability is achieved by connecting each device with a common bus (CBUS) and performing packet format data transfer using the common bus (CBUS). Are increasing, but the packet format has the following problems, and the required performance cannot be easily achieved. Therefore, there is a need for a control means for better packet transfer for realizing a low-cost and high-performance data processing system.

[0003]

2. Description of the Related Art FIG. 16 is a diagram for explaining a conventional data processing system. In FIG. 16, CBUS indicates a common bus, 1, 2, and 3 indicate devices, respectively, and 9 indicates a use request signal from each of the devices 1, 2, and 3 to the common bus (CBUS). Indicates the bus arbiter to arbitrate.

[0004] BRQ1, BRQ2, and BRQ3 indicate use request signals for the common bus (CBUS) output from the device 1, the device 2, and the device 3, respectively. BGR1, BGR2, and BGR3 indicate the device 1, the device 2, and the device 2, respectively. 6 shows a signal for permitting use of the common bus (CBUS) for the device 3.

[0005] Reference numerals 10, 20, and 30 denote devices 1, 2, and 3, respectively.
A first transmission command packet buffer in the device 3 is shown, and 11, 21, and 31 denote second transmission command packet buffers in the device 1, the device 2 and the device 3, respectively.
Reference numerals 22 and 32 denote first received command packet buffers in the device 1, the device 2 and the device 3, respectively.
Indicates the buffers for the second received command packets in the devices 1, 2, and 3, respectively, and 14, 24, and 34 indicate the buffers for the first received reply packets in the devices 1, 2, and 3, respectively. And 15, 25, and 35 are devices 1,
The buffers for the second reception reply packet in the device 2 and the device 3 are shown, and 16, 26, and 36 indicate the device 1, the device 2, and the device, respectively.
Indicates the reply packet transmission buffer in 3, 100, 200
, 300 denote received packet buffers in the device 1, device 2, and device 3, respectively, where both the received command packet and the received reply packet are temporarily stored in the received packet buffer, and the packet type is analyzed.

[0006] Each of the devices 1, 2, and 3 is a common bus.
The data processing operation is performed by transmitting and receiving packets to and from each other using (CBUS). For example, device 1
Is a CPU, device 2 is a channel, and device 3 is a storage device.

[0007] The above device 1, device 2 and device 3 are
First, to obtain the right to use the common bus (CBUS),
BUS) request signal BRQ1, BRQ2, BRQ3 to the bus arbiter 9
Output to Bus arbiter 9 is BRQ1, BRQ2, BRQ3
Are output simultaneously, according to a predetermined priority, the highest priority common bus (CBUS)
A use permission signal of the common bus (CBUS) is output in response to the use request signal of. In this conventional example, (high) BRQ1>BRQ2> BRQ3 (low). For example, if BRQ1, BRQ2, and BRQ3 are output simultaneously, the common bus (CBUS) use permission signal BGR for BRQ1 is output.
Only 1 is output.

[0008] The device that has received the use permission signal of the common bus (CBUS) transmits a packet to the partner device. For example, device 1 has its own send command packet buffer.
The transmission command prepared in 10 is transmitted to the partner device, for example, the device 3.

FIG. 17 is a diagram showing an example of a packet format. FIG. 17A shows an example of a write command packet, FIG. 17B shows an example of a read command packet, and FIG. c) shows an example of a write reply packet, FIG. 17 (d) shows an example of a read reply packet,
FIG. 17E shows an example of the busy reply packet.
Each packet has fields indicating a packet type, a packet number, an own device number, and a partner device number.

The destination device 3 receives the transmitted command packet in the received command packet buffer 32 or 33. And analyze the command type,
If it is a read command packet, the data corresponding to the address indicated in the address field in the packet is read out from the self-device, and a read reply packet corresponding to the read command packet is generated on the reply packet transmission buffer 36, and the command transmission source device is read. Reply the read reply packet to

If the result of analyzing the command type is a write command, data corresponding to the address indicated in the address field in the packet is written into a memory or a register (not shown) in the apparatus. Then, a write reply packet corresponding to the write command packet is generated on the reply packet transmitting buffer 36, and the write reply packet is returned to the command transmission source device.

Here, if a command packet transmitted from another device has already been received in the reception command packet buffers 32 and 33 of the destination device 3,
Until the destination device 3 returns a reply packet to them, the corresponding command packet must be held in the received command packet buffers 32 and 33, so that a new command packet is not accepted ( Buffer busy).

Therefore, in response to a command newly sent in such a state, an error return packet with a packet type of "buffer busy" is returned instead of a normal return packet. Upon receiving the error return packet, the command transmission source device analyzes the packet type, and if the packet type is “buffer busy”, retransmits the same command packet again. This is repeated until the reception command packet buffer of the partner device 3 becomes ready to receive the command packet.

[0014]

In the example of the conventional data processing system shown in FIG. 16, when the buffer busy state of the reception command packet buffer of the destination apparatus continues for a long time, the retry transmission of the transmission source is performed. Will be repeated. This causes the following problems.

Problem 1: Since the command packet of the transmission source device is not easily processed, the processing performance of the transmission source device is suppressed low. Problem 2: In particular, when a transmission source device is going to transmit a command packet for DMA transfer from an input / output device (I / O), if the command packet is not processed for a certain period of time or more, the input / output device (I / O) O) causes overrun on the side.

Problem 3: When retry transmission of a transmission source is repeated, unnecessary bus occupation of the common bus (CBUS) increases, and the effective use efficiency of the common bus (CBUS) decreases. This also results in a decrease in the processing performance of another device.

In view of the above-mentioned conventional disadvantages, the present invention suppresses a reduction in processing performance due to repetition of retry transmission from a transmission source device, and as a result, occurrence of overrun on an input / output device (I / O) side. It is an object of the present invention to provide a data processing system capable of suppressing and improving an effective usage rate of a common bus (CBUS).

[0018]

SUMMARY OF THE INVENTION The above problems are solved by a data processing system having the following means.

(1) A plurality of devices transmit and receive packets to and from each other using a common bus (CBUS), and each device transmits a common bus (CBUS) use request signal of a predetermined priority prior to packet transmission. And the bus arbiter outputs its common bus (C
BUS) is a data processing system provided with control means for arbitrating a use request signal, determining a common bus use device according to the priority, and giving permission, and each device outputs a common bus (CBUS) use request signal. And first means for outputting information indicating the transfer destination, the bus arbiter receiving second information indicating the transfer destination, and a packet receiving side device for receiving a command packet of the own device. Third means for transmitting information indicating the state of a buffer to the bus arbiter and / or all devices, and the bus arbiter and the plurality of devices receive information indicating the status of a buffer for a received command packet of another device. And a fourth means.

(2) A third means for providing the data processing system according to the item (1) with a predetermined operation mode, and transmitting information indicating a state of a reception command packet buffer of the own device to the bus arbiter. When the operation mode is the initial mode, a signal indicating that each device is mounted is transferred, and when the initial mode is terminated and a predetermined processing mode is set, the reception command packet It is configured to be means for transferring information indicating the state of the buffer.

(3) In the data processing system according to the above mode (2), the information indicating the status of the reception command packet buffer may include the number of reception command packet buffers provided in each packet reception device, or , The received command packet buffer is busy.

(4) A plurality of devices transmit and receive packets to and from each other using a common bus (CBUS), and each device normally sends a request signal for use of the common bus (CBUS) having a predetermined priority. The bus arbiter arbitrates the request signal for use of the common bus (CBUS), determines the device using the common bus, and grants the device. In the case of a busy state, the packet receiving side device has a packet transfer means for permitting the packet transmission source device to transfer the return packet to which the information indicating that the command packet needs to be retransmitted is returned. A data processing system comprising:
A retry counter is provided in each device to count the number of times a command packet has been retransmitted. The packet transmission source device sends out the same command packet again after a certain period of time after receiving the reply packet, and increments the retry counter. The above-mentioned command packet is repeatedly received until the counterpart device receives the command packet, and when the retry counter becomes equal to or more than a predetermined threshold value, a means for sending a use request signal of a high-priority common bus (CBUS) is provided. Configure.

(5) A plurality of devices transmit and receive packets to and from each other using a common bus (CBUS), and each device normally sends a request signal for use of the common bus (CBUS) having a predetermined priority. The bus arbiter arbitrates the request signal for use of the common bus (CBUS), determines the device using the common bus, and grants the device. In the case of a busy state, the packet receiving side device has a packet transfer means for permitting the packet transmission source device to transfer the return packet to which the information indicating that the command packet needs to be retransmitted is returned. A data processing system comprising:
A plurality of types of information indicating that the command packet needs to be retransmitted are provided, and the packet transmission source device changes the time until the same command packet is transmitted again after receiving the reply packet according to the type of the information. Configure to provide.

(6) A plurality of devices transmit and receive packets to and from each other using a common bus (CBUS), and each device normally sends a request signal for use of the common bus (CBUS) having a predetermined priority. The bus arbiter arbitrates the request signal for use of the common bus (CBUS), determines the device using the common bus, and grants the device. In the case of a busy state, the packet receiving side device has a packet transfer means for permitting the packet transmission source device to transfer the return packet to which the information indicating that the command packet needs to be retransmitted is returned. A data processing system comprising:
If the packet receiving device accesses a resource that cannot return a reply packet after a certain bus cycle, for example, data that takes time to process in the packet receiving device, a temporary reply packet is returned, and then the packet is returned. A means is provided for preparing a formal reply packet before the command packet transmitted by the transmitting device arrives.

(7) A plurality of devices transmit and receive packets to and from each other using a common bus (CBUS), and each device normally sends a use request signal of the common bus (CBUS) having a predetermined priority. And a bus arbiter which arbitrates a request signal for use of the common bus (CBUS), determines a device using the common bus, grants permission, and the permitted device transmits a packet. Wherein information of a buffer for a received command packet of another device is transferred to the common bus.
(CBUS) is configured to include means for monitoring by a packet on the (CBUS), and means for obtaining information relating to a received command packet buffer of another apparatus to which the own apparatus may transmit a command packet by the monitoring means.

(8) A plurality of devices transmit and receive packets to and from each other using a common bus (CBUS), and each device transmits a signal requesting use of a common bus (CBUS) having a predetermined priority prior to packet transmission. And the bus arbiter outputs its common bus (C
BUS) is a data processing system including a control means for arbitrating a use request signal, determining a common bus use device according to the priority, and giving permission, and controlling a plurality of received command packet buffers of a packet receiving side device. The number of receive command packet buffers exclusively used by each packet transmitting apparatus is determined in advance for each packet transmitting apparatus, and each packet transmitting apparatus determines a counterpart assigned to its own apparatus. It is configured to include means for controlling so that a packet exceeding the number of received command packet buffers of the side device is not transmitted to the partner device.

FIG. 1 shows (1) one of the above means of the present invention.
It is a principle block diagram of the data processing system provided with the means as described in (3). In the data processing system of the present invention, each of the devices 1, 2, and 3 outputs a request signal for use of the common bus (CBUS), and simultaneously outputs information indicating the transfer destination thereof. When the command packet buffer (hereinafter simply referred to as the command reception buffer) is busy and cannot receive a new packet,
The state is, for example, a dedicated one-to-one signal line or
The signal is transmitted to the bus arbiter 9 or all the devices (packet transmitting side devices) using a dedicated bus BBUS (in FIG. 1, indicated by a dotted line).

The bus arbiter 9 does not provide a common bus (CBUS) use permission signal to a device in which the command reception buffer is busy and cannot receive a new command packet. Thus, no command packet is sent to a device that cannot receive a new command packet, and the common bus (CBUS) can be effectively used.

Also, the packet receiving device informs all the devices that the command receiving buffer of the packet receiving device is busy by using a dedicated one-to-one signal line or a dedicated bus BBUS, thereby transmitting a command. Since the device which is going to send out the packet can always grasp the status of the command reception buffer of the partner device, the common bus for accessing the device whose command reception buffer is busy is available.
The use request signal of (CBUS) can be suppressed or the command packet can be switched to transmission of a command packet to another device, and unnecessary packets are not sent to the common bus (CBUS).

Further, the data processing system of the present invention is provided with an operation mode including an initial mode and a processing mode, so that in the initial mode at the time of power-on or the like, frequent access such that the command reception buffer becomes busy. In the initial mode, information indicating whether each device is mounted is transmitted to the bus arbiter using the dedicated one-to-one signal line or the dedicated bus BBUS.
9, when the transmission of the mounting information of each device is completed and a transition is made to the normal processing mode, the information for determining whether the command reception buffer is busy is transmitted. One-to-one signal line or dedicated bus
BBUS can be shared.

The information indicating the status of the command receiving buffer is, in addition to the information indicating whether the command receiving buffer is busy, the number of command receiving buffers (the number of stages) provided in each packet receiving apparatus. By doing so, it is possible to recognize in advance the state of the command reception buffer provided in each device, the information on the number of times of transmission and reception of the command reception buffer of the partner device obtained by the means described in claim 7,
By using this information (the number of command reception buffers), the device that intends to transmit a packet can always grasp the state of the reception buffer of the partner device, and therefore, the device that attempts to access the device whose command reception buffer is busy can be used. Request for use of the common bus (CBUS) can be suppressed, or transmission of command packets to other devices can be switched, and transmission packets are sent to devices whose command reception buffer is already busy. As a result, useless packet transfer such as that the receiving device returns a reply packet to which information indicating that the command receiving buffer is busy and cannot be received is eliminated.

FIG. 2 shows (4) of the above means of the present invention.
It is a principle block diagram of the data processing system provided with the means as described in (7). In the data processing system described in (4), a retry counter is provided in each device to count the number of times a command packet has been retransmitted.
While transmitting the same command packet again, incrementing the retry counter is repeated until the command packet is received by the partner device, and when the value of the retry counter becomes equal to or greater than a predetermined threshold,
By sending a request signal to use the high-priority common bus (CBUS), when the command reception buffer of the partner device becomes empty, another device sends a command packet to the same partner device at the same time. Common bus (C
BUS), a command packet can always be transmitted to the partner device by using the common bus (CBUS) by obtaining the common bus use permission.

In the data processing system described in the item (5), a plurality of types of information requiring retransmission of the command packet are provided, and if the command reception buffer is expected to be empty within a predetermined time, the data is re-transmitted. If it is expected that it takes more than a certain time for the command reception buffer to become empty, the second information is added to the reply packet. After receiving the reply packet, the packet transmission source device
If the first information has been added, the same command packet is transmitted within a certain time, and if the second information has been added, the same command packet is transmitted after a certain time has elapsed. I do. Since control can be performed in this manner, the frequency of useless packet transmission such as a response packet requesting retransmission when the command reception buffer is busy can be reduced.

In the data processing system described in the item (6), when a resource that cannot return a reply packet after a certain bus cycle, for example, a resource that takes a long time to process is accessed, a temporary reply packet is transmitted. After transmitting, a formal reply packet is prepared until the next command packet transmitted by the transmission source device arrives, and when the next command packet comes, the prepared formal reply packet is returned. As a result, packets do not stay in each device, and it is possible to reduce the possibility that the command reception buffer becomes busy.

Further, in the data processing system described in the item (7), each device is provided with a means for monitoring a packet transmitted / received by another device on a common bus (CBUS), so that each device can receive other data. Since the number of command receiving buffers of the device is recognized, it is possible to indirectly know which device's packet receiving buffer is currently busy by knowing the number of packets transmitted and received by each device. For example, when the device 3 has two command receiving buffers, the command packet is transmitted twice from the device 2 to the device 3, and the return packet has not been returned yet, the receiving buffer of the device 3 is busy and a new The device 1 can also know that the command packet cannot be received. Therefore, a device that is going to send a command packet can always grasp the status of the command reception buffer of the partner device, and thus a common bus (CBUS) for accessing a device whose command reception buffer is busy. Can be suppressed or a command packet can be switched to transmission of a command packet to another device, and useless packet transfer to the common bus (CBUS) is eliminated.

FIG. 3 shows (8) one of the above means of the present invention.
It is a principle block diagram of the data processing system provided with the means as described in an item. In this case, each transmission source device can control not to transmit a command packet exceeding the number of command reception buffers allocated to its own device among the command reception buffers of the partner device to the partner device. So
Useless packets such as sending a command packet to a device where the command reception buffer is already busy, or returning a reply packet to the command packet with information indicating that the command reception buffer is busy and cannot be received. No more transfers.

[0037]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 4 is a diagram showing an embodiment of the present invention, FIG. 5 is a diagram for explaining a busy signal of a command receiving buffer, and FIG. 6 is a diagram in which each device transmits a busy signal through a dedicated bus. FIG. 7 is a diagram in which each device transmits a busy signal to all other devices, showing an embodiment corresponding to claims 1 to 3, and FIG. 8 shows another embodiment of the present invention. FIG. 9 is a diagram for explaining an access request and packet processing of the present invention, and FIG. 10, FIG.
FIG. 13 is a diagram showing a modification of the other embodiment of the present invention. FIG. 13 is a flowchart of a command packet receiving process of the present invention. FIG. 14 is a flowchart of a reply packet receiving process of the present invention. 15 shows an embodiment corresponding to claims 4 to 7, and FIG. 15 is a diagram showing a modification of another embodiment of the present invention, and shows an embodiment corresponding to claim 8. ing.

The same reference numerals indicate the same objects throughout the drawings, and the common bus in the claims corresponds to the common bus (CBUS), and the use request signal of the common bus (CBUS) is BRQ1, BRQ2, B
RQ3 is supported, and permission to use the common bus (CBUS) is
(CBUS) use enable signals BGR1, BGR2, and BGR3 are provided.Received command packet buffers are command receive buffers 12, 13, 22, 23, 32, and 33.Received command packet buffers are busy. The information indicating whether or not
SY1, BSY2, and BSY3 correspond, and each device outputs a common bus (CBUS) use request signal and outputs information indicating its transfer destination.The means for transmitting signals DNOA, DNOB, and DNOC correspond to these devices. The information indicating that the command packet needs to be retransmitted and the provisional reply packet correspond to the case where the information in the packet type field of the reply packet is a predetermined value (= 101, 110, etc.). The means for monitoring the information of the packet buffer on the common bus (CBUS) is supported by the reception packet monitoring circuits 17, 27, and 37, and the number of reception command packet buffers exclusively used by each packet transmission side device is determined by: Holding means 18, 28, and 38 correspond to means for preliminarily holding each packet transmitting apparatus.

Hereinafter, the structure and operation of the data processing system according to the present invention will be described with reference to FIGS. In FIG. 4, BS
Y1, BSY2, and BSY3 are signals that notify the bus arbiter 9 that the command reception buffers of the devices 1, 2, and 3 are busy, respectively.

The signals DNOA, DNOB, DNOC are respectively
1. A means for transmitting information indicating the device number of the partner device to the bus arbiter 9, which is output by the device 1, the device 2 and the device 3 together with the use request signal of the common bus (CBUS).

In FIG. 4, a plurality of devices 1, 2, 3 are:
Packets are transmitted and received to and from each other using the common bus (CBUS) .Each of the devices 1, 2, and 3 transmits a request signal BRQ for use of the common bus (CBUS) having a predetermined priority prior to packet transmission.
After outputting 1, BRQ2 and BRQ3, the bus arbiter 9 existing in the data processing system arbitrates the use request signals BRQ1, BRQ2 and BRQ3 of the common bus (CBUS) and determines the bus using device according to the priority, The use permission signals BGR1, BGR2, and BGR3 of the corresponding common bus (CBUS) are supplied, and the apparatus which is permitted to control is transferred so as to transfer the packet.

At this time, in the data processing system of the present invention, each of the devices 1, 2, and 3 outputs the use request signals BRQ1, BRQ2, and BRQ3 of the common bus (CBUS), and outputs the signals DNOA,
The bus arbiter 9 receives the information indicating the transfer destination using DNOB and DNOC, and the packet arbiter 9 receives the information indicating the transfer destination. When a command packet cannot be received, the status is determined by the bus arbiter 9.
BSY1 signal (for device 1) or BSY2 signal
(For device 2) or BSY3 signal (for device 3). For example, when the use request signal BRQ1 of the common bus (CBUS) from the device 1 and the use request signal BRQ2 from the device 2 are issued at the same time, the bus arbiter 9
Signal DNOA that transmitted information indicating the transfer destination from
For example, if it is device 2 and that device 2 outputs the BSY2 signal and indicates that the packet cannot be received, even if device 1 is more normal than device 2, Even if the priority is high, the device 1 is not given permission in this case. Then, the signal content of the signal DNOB that has transmitted the information indicating the transfer destination from the device 2 is analyzed,
For example, when the device 3 is the device 3 and the device 3 does not output the BSY3 signal and is in a state in which a command packet can be received, the device 3 outputs the BGR2 signal and gives the device 2 a bus use permission.

FIG. 5 is a diagram for explaining the busy signal of the command receiving buffer, and shows an embodiment corresponding to claim 2. FIG. 5 (a) shows an example of the configuration on the device 1 side, and FIG.
(b) shows a configuration example of the bus arbiter 9 side. In FIG. 5, 1 indicates an apparatus, 9 indicates a bus arbiter, and is the same as that described in FIG. MODE indicates a mode register in the device 1 and the bus arbiter 9. The output is "0" in the initial mode and "1" in the normal processing mode. NOT1, NOT9 indicate knot gates, and AND1, AND91, A
ND92 indicates an AND gate, OR1 indicates an OR gate, and R91 indicates a pull-down means.

BUF.FULL is a signal indicating that the command receiving buffers 12, 13 in the device 1 are in a busy state.
BSY1 is a multi-use signal indicating that the device 1 is mounted in the initial mode, and that the command receiving buffers 12, 13 are busy in the normal processing mode.

D1.INSTALL is a signal indicating that the device 1 is mounted, and D1BUF.FULL is a signal indicating that the command receiving buffers 12, 13 of the device 1 are busy.

In FIG. 5A, the output of the mode register MODE in the device 1 is "0" at the time of the initial mode, becomes "1" by passing through the NOT gate NOT1, and is input to the OR gate OR1. You. Regardless of the value of the other input in OR1, its output is "1", and in the initial mode, the BSY1 signal is "1", and the bus arbiter
9 and instructs bus arbiter 9 that device 1 is installed. The same applies to BSY2 of device 2 and BSY3 of device 3.

In the arbiter 9 shown in FIG. 5 (b), if the device outputting these BSY1, BSY2, and BSY3 signals is not connected, the logic of these signals becomes invalid. If the device 1 to output the BSY1 signal is not mounted, the bus arbiter 9
Internally, pull-down means that BSY1 = "0"
1 is provided for each signal, and D1.
Set INSTALL to "0". Whether the mode is the initial mode or the processing mode is transmitted to the arbiter 9 and the devices 1, 2, and 3 by another means (not shown). In the initial mode, the arbiter 9
Analyzes the BSY1 to BSY3 signals and determines the mounting status of each device (D1.
INSTALL = 1 etc.).

The output of the mode register MODE in the device 1 in the processing mode becomes "1" and is input to the AND gate AND1. The other input BUF.FULL signal of AND1 is
When both the command receiving buffers 12 and 13 in FIG. 4 are busy, they become "1". At this time, the output of AND1 becomes "1" and the BSY1 signal outputs "1". 13 is empty, the BUF.FULL signal outputs "0", the output of the AND1 gate becomes "0", the BSY1 signal outputs "0", and is transmitted to the bus arbiter 9. . apparatus
The same applies to BSY2 of 2 and BSY3 of device 3.

As described above, the BSY1, BSY2, and BSY3 signals are used as signals indicating that each device is mounted in the initial mode, and the initial settings in the initial mode, for example, the setting of the mounting state and the like are performed. When the processing is completed and the processing shifts to the normal processing mode, the command reception buffers 12 and 13 are used as signals indicating that the command reception buffers 12 and 13 are busy and a new command packet cannot be received.

FIG. 6 shows a modification of the embodiment corresponding to claim 1 of the present invention, in which signals BSY1, BSY2, BSY indicating that the command receiving buffers of the devices 1, 2, 3 are busy.
3 is transmitted to each device via a dedicated bus BBUS.

In FIG. 6, each device changes the state of its command reception buffer 12 or 13 at a specific timing after receiving a command packet to its own device by using a dedicated bus BBUS.
And coded using. For example, the dedicated BB
The US has a 3-bit configuration, the first 2 bits are the number of the own device, the last 1 bit is buffer busy information (“0” is empty, “1” indicates busy), or the dedicated The bus arbiter 9 monitors the field of the destination device number of the command packet on the common bus (CBUS), and after transmitting the command packet to the device 3, for example, sets the bus BBUS to the dedicated bus BBUS. When "1" is output, it can be recognized that the buffer of the device 3 has become busy.

In this way, each device can transmit the status of its own command receiving buffer to the bus arbiter 9 using the dedicated bus BBUS. In the embodiment shown in FIG. 4, the use request signal B of the common bus (CBUS) is used.
In this example, signals RQ1, BRQ2, and BRQ3 and signals DNOA, DNOB, and DNOC for transmitting information indicating the device number of the destination device to the bus arbiter 9 are transmitted through separate signal lines. There is no special means to output information indicating
Each device may transmit information indicating the transfer destination to the bus arbiter 9 by using one common bus (CBUS) use request signal BRQ1, BRQ2, BRQ3 from each device.

More specifically, the device n accesses the device m (m = 1 to 3), and the device n uses the common bus (CBUS) request signal BRQn.
When outputting (n = 1 to 3, m ≠ n), BRQn is turned on in the first cycle, and a fixed code is output to BRQn in the second and third cycles according to the destination device number. That is, when the other device is the device 1, “0” is set in the second cycle,
"1" in the third cycle If the destination device is device 2, "1" in the second cycle,
"0" in the third cycle If the destination device is device 3, "1" in the second cycle,
Serial transmission that outputs “1” in the third cycle may be used.

In the data processing system according to the present invention, the bus arbiter 9 is a signal indicating that the command reception buffer from the packet receiving side device is busy and cannot receive a new command packet. When (BSYm, m = 1 to 3) is received, a common bus (CBUS) use request signal indicating an access request to the receiving side device
Requests access to another device whose command reception buffer is not busy without giving the common bus (CBUS) use permission signal BGRn (n = 1 to 3) to BRQn (n = 1 to 3, m ≠ n). To the corresponding device, the use permission signal of the common bus (CBUS) is given.

That is, as shown in FIG. 4, the device 1 requests the use of the common bus (CBUS) to access the device 3.
BRQ1 is output, and device 2 outputs command request buffer 1 of device 3 on the other side of device 1 while outputting request signal BRQ2 for use of the common bus (CBUS) to access device 1.
If the signal BSY3 indicating the status of 2 or 13 is not "0" and not busy, and the signal BSY1 indicating the status of the command reception buffer of the other device 1 of the device 2 is "1" and busy.
Although the specific priority of the request signal for use of the common bus (CBUS) itself is higher for signal BRQ1 than for signal BRQ2, bus arbiter 9 may control to provide use permission signal BGR2 for signal BRQ2. it can.

FIG. 7 shows that each device does not transmit the signals BSY1, BSY2, BSY3 indicating that the command reception buffer is busy to the bus arbiter 9, but to all other devices the signals BSY1, BSY2, BSY.
FIG. 9 is a diagram showing a case where SY3 is transmitted.

7 and 4 show signals BSY1 and BS indicating that the command reception buffer from each device is busy.
The difference is that Y2 and BSY3 are not input to the bus arbiter 9 but are input to all devices other than the own device.

As shown in FIG. 7, a plurality of devices 1, 2, 3
Using a common bus (CBUS), packets are transmitted and received between each other.Each of the devices 1, 2, and 3 sends a use request signal BRQ1, BRQ2, BRQ3 is output, and the bus arbiter 9 arbitrates the common bus (CBUS) use request signal BRQ1, BRQ2, BRQ3, determines the common bus use device according to the priority order, and uses the corresponding common bus (CBUS) use enable signal. BGR1, BGR2, BGR3
A data processing system in which a device that is permitted to use is controlled to transmit a command packet, and each of the devices 1, 2, and 3 uses a common bus (CBUS) use request signal BRQ1,
At the same time that BRQ2 and BRQ3 are output, when the command reception buffer of the own device is busy and a new command packet cannot be received, the status is sent to all other devices as BSY1 signal (for device 1). And to device 3 or as a BSY2 signal (for device 2) to device 1 or device 3 or as a BSY3 signal (for device 3) to device 1 or device 2.

In FIG. 6 described above, the dedicated bus BBUS is connected to the bus arbiter 9. However, corresponding to FIG. 7, the dedicated bus BBUS is not connected to the bus arbiter 9 and each device is connected. May be configured to input the information output to the dedicated bus BBUS only to all other devices.

Also in this case, each of the devices 1, 2, and 3 encodes and outputs the status of the command reception buffer using a dedicated bus BBUS at a specific timing after receiving the command packet to the own device. . For example, the dedicated bus BBUS has a 3-bit configuration, the first 2 bits are the number of the own device, the last 1 bit is a busy signal of the command reception buffer (“0” is empty, and “1” is busy). Or the dedicated bus BBUS is only 1 bit,
Each device monitors the destination device number of the command packet on the common bus (CBUS). For example, after transmitting a command packet to the device 3, if "1" is output to the dedicated bus BBUS, the device 3 By configuring the command reception buffers 32 and 33 so that they can be recognized as being in a busy state, each device can change the status of its own command reception buffer to the dedicated bus.
All devices can be communicated using BBUS.

FIG. 8 is a view showing another embodiment of the present invention, and shows an embodiment corresponding to claims 4 to 7.
FIG. 8 shows the busy signals BSY1, BSY2, BSY3 of the command receiving buffer from each of the devices 1, 2, 3 and the device numbers of the destination devices output from each device, as compared with FIGS. There is no means to transmit the signals DNOA, DNOB, DNOC, which provides a means for transmitting the information to the bus arbiter 9, and instead, all devices on the common bus (CBUS) are always stored in each device 1, 2, 3. Received packet monitoring circuit that receives and analyzes packets 17,27,3
7 is essentially different.

First, referring to FIG. 8 and FIG.
An embodiment corresponding to FIG. In FIG. 8, the reception packet monitoring circuit 17 or 27 or 37 in each device monitors transmission information of a packet transmission buffer of another device, and there is a possibility that the own device transmits a packet based on the monitoring information. This is to indirectly obtain the status of the command reception buffers of all the devices on the other side.

That is, the destination of the command packet transmitted on the common bus (CBUS) and the source of the return packet are monitored. As shown in FIGS. 17A to 17E, the command packet and the reply packet have the own device number and the destination device number fields, and thus can be obtained by monitoring the numbers of the fields. It is possible to know whether or not the destination command reception buffer is currently busy from the information and the number of stages of the destination command reception buffer obtained via the common bus (CBUS) described later.

That is, in the reception packet monitoring circuit 17 in the device 1, first, the other device which may transmit a command packet, for example, the device 2 and the device 3
The information that the number of command reception buffers is 2 is stored in the reception packet monitoring circuit 17.

The destination of the command packet transmitted on the common bus (CBUS) and the source of the return packet are constantly monitored, and for example, it is detected that two command packets addressed to the device 2 have been transmitted. Then, at that time the device
It can be determined that the second command reception buffers 22, 23 are busy.

When one reply packet from the device 2 is detected, it can be determined that one of the command receiving buffers 22, 23 of the device 2 is free. Further, when a command packet to the device 2 is further detected, it can be determined at that time that the command reception buffer of the device 2 has become busy again. The same applies to the device 3. In this way, the reception packet monitoring circuit 17 uses the common bus (C
By monitoring only the packets on the BUS), the busy state of the command reception buffer of another device can be determined.

In FIG. 8, reference numerals 18, 28, and 38 denote holding registers for holding information on the number of reception buffers in the device 1, the device 2, and the device 3, respectively, which can be read from other devices. .

In FIG. 8, reference numeral 18 denotes a holding register for holding information on the number of reception buffers in the device 1;
In the case of (1), in this figure, since there is one command reception buffer indicated by 12, information "1" is held. This is read out by the device 2 and the device 3 and stored in the received packet monitoring means 27 and 37 in the own device as information on the number of stages of the command reception buffer of the device 1.

Similarly, reference numeral 28 denotes a holding register for holding information on the number of command reception buffers in the device 2;
In the case of 2, in this figure, since there are two command receiving buffers indicated by 22 and 23, information "2" is held. This is read out by the device 1 and the device 3 and held as received command buffer stage number information of the device 2 in the received packet monitoring circuits 17 and 37 in the device itself.

Similarly, reference numeral 38 denotes a holding register for holding information on the number of command reception buffers in the device 3;
In the case of 3, in this figure, the reception buffer 1 indicated by 32
Since the number is “1”, information “1” is held. This is read out by the device 1 and the device 2 and stored in the received packet monitoring circuits 17 and 27 in the device itself as the command receiving buffer stage number information of the device 3.

As described above, based on the information on the number of stages of the command receiving buffer of each device, the common bus (C
By monitoring the packets on the BUS), it is possible to determine whether the command reception buffer of another device is busy.

FIG. 9 is a diagram for explaining an access request and packet processing of the present invention. FIG. 9 (a) shows a data processing system having no means for transmitting a busy signal of a command reception buffer to each device. 8 shows a configuration example of a means for controlling a use request signal of a common bus (CBUS) in the packet transmission device, and shows a specific example of an access request unit 105 to another device in the device 1 of FIG. Indicates an access request generation unit for device 2, 102 indicates a command reception buffer busy detection unit of device 2, 103 indicates an access request generation unit for device 3, and 104 indicates a command reception buffer busy detection unit of device 3. , AND3 and AND4 indicate AND gates, and OR2 indicates an OR gate.

In FIG. 9, even if an access request to the device 2 is generated from the access request generator 101 inside the device 1, a signal indicating that the command reception buffers 22, 23 of the device 2 are busy ( (“0” in the busy state) is received from the command reception buffer busy detection unit 102, and is gated by the AND gate AND3,
Not output as common bus (CBUS) use request signal BRQ1. Similarly, even if an access request to the device 3 is generated from the access request generation unit 103 inside the device 1, a signal indicating that the command reception buffer of the device 3 is busy (“0” when busy). Is received from the command reception buffer busy detection unit 104, it is gated by the AND gate AND4 and is not output as the common bus (CBUS) use request signal BRQ1. Using this means,
If the command reception buffer of the destination device to which the packet is to be transmitted is busy, the packet transmission source device does not send a request signal for use of the common bus (CBUS) and leaves the reception buffer empty. Common bus
(CBUS) use request signal can be transmitted.

That is, when the device 1 wants to send a command packet to the device 2, when the BSY2 signal is "1", that is, when the command receiving buffers 22, 23 of the partner device 2 are busy, the common bus (CBUS) When the transmission of the use request signal BRQ1 is suspended and the BSY2 signal is “0”, that is, when the command reception buffers 22, 23 of the partner device 2 become empty, the use request signal BRQ1 of the common bus (CBUS) is transmitted. To

Further, based on the information indicating the number of stages of the command reception buffer of the destination device obtained by the above-described received packet monitoring circuit 17 or 27 or 37, the packet transmission source device determines that the destination If the command reception buffer of the previous device is busy,
Do not send a request signal to use the common bus (CBUS).
BUS) is transmitted.

Next, an embodiment corresponding to claim 4 will be described with reference to FIG. In FIG. 8, BRE1, BRE2, BRE3
Indicates a use request signal of a common bus (CBUS) having a predetermined higher priority, which is output from the device 1, the device 2, and the device 3, respectively, and indicates 105, 205, and 105 shown in FIG.
305 is the device 1, device 2, and device 3, respectively.
106, 206, and 306 indicate access request signal switching units in the device 1, the device 2, and the device 3, respectively. 107, 207, and 307 indicate
3 shows a retry counter in a device 1, a device 2, and a device 3.

A plurality of devices 1, 2, and 3 are connected to a common bus (CBUS)
To send and receive packets to and from each device 1,
2 and 3 output use request signals BRQ1, BRQ2, and BRQ3 of the common bus (CBUS) having a predetermined priority, and the bus arbiter 9 existing in the data processing system uses the common bus (CBUS). Arbitrate the request signals BRQ1, BRQ2, and BRQ3, determine the device that uses the common bus according to the priority order, and provide the use permission signals BGR1, BGR2, and BGR3 for the corresponding common bus (CBUS),
When the command receiving buffer of the partner device is in a busy state (command packet unreceivable state) at the time of transmission of the command packet by the permitted device, the packet receiving device transmits the packet to the packet transmission source device as shown in FIG. e) A data processing system that allows transfer such as returning a reply packet to which information (packet type = 100) indicating that a command packet needs to be retransmitted as shown in e). The retry counters 107, 207, and 307 for counting the number of retransmissions are provided, and the packet transmission source device sends out the same command packet again after a certain time has elapsed after receiving the return packet,
The above-described increment of the retry counters 107, 207, and 307 is repeated until the command packet is received by the partner device. When the retry counter 107, 207, or 307 exceeds a predetermined threshold, the information is switched to an access request signal. By transmitting the signals to the units 106, 206, and 306, the request signals BRQ1 and BR
Control is performed so that the use request signals BRE1, BRE2, and BRE3 of the high priority common bus (CBUS) are transmitted instead of Q2 and BRQ3.

Next, an embodiment corresponding to claim 5 will be described with reference to FIGS. 8 and 9B. In the data processing system of the present invention, the retransmission time of the packet is changed according to the contents of the field indicating the packet type of the return packet shown in FIG.

In the present invention, for example, in the first case (first packet) of information (depending on the packet type) indicating that retransmission is required for a reply packet (busy reply packet) when the command reception buffer is busy. The second case (at the time of the second busy reply) of the information (depending on the packet type) indicating that the retransmission is required in the return packet (busy reply packet) when the command reception buffer is in the busy state. ).

FIG. 9 (b) is a flowchart showing a reply packet receiving processing method by changing the retransmission reply time of the present invention in each of the devices 1, 2, and 3. A plurality of devices transmit and receive packets to and from each other using a common bus (CBUS), and each of the devices 1, 2, and 3 normally outputs a request signal for use of the common bus (CBUS) having a predetermined priority. Then, the bus arbiter 9 existing in the data processing system arbitrates the use request signal of the common bus (CBUS), determines a device using the common bus, and gives a permission. The command reception buffer of the device is busy (command cannot be received)
If the packet receiving side device is a data processing system that allows the packet transmission source device to transfer the packet transmission device to return a reply packet to which information indicating that the packet needs to be retransmitted, If the other device receives a new command packet while the command reception buffer is busy but a return packet for the received command packet can be returned within a predetermined time, the command reception buffer is in a busy state. As a reply packet (busy reply packet) at the time of (1), information indicating the first case (at the time of the first busy reply) of information indicating that retransmission is required, for example, packet type = “101” is used for reply packet transmission. Generate on buffer.

Further, the other party expects that the command reception buffer is busy and it takes a certain time or longer to return a reply packet for the received command packet (for example, the processing time is required until the return packet is generated). In such a case, if a new command packet is received, the second case of information indicating that retransmission is required in a reply packet (busy reply packet) when the command reception buffer is in a busy state (busy reply packet) (When the second busy reply)
, For example, a packet type = “110” is generated on the reply packet transmission buffer.

At the time of command transmission, the command transmission source device
When a reply packet is received from the destination device,
As shown in (b), if the packet type is "101" as a result of analyzing the packet type, a reply packet is returned within a certain period of time even if the packet is currently busy, Since the receiving buffer should be empty, the command packet is retransmitted after the first time has elapsed. {See processing steps 300 to 302 in FIG. 9 (b)} As a result of analyzing the packet type, the packet type =
When the value is “110”, the command receiving buffer of the partner device is in a busy state and is expected to be in a busy state for a predetermined time or more, so the second time is longer than the first time. After the time elapses, the command packet is retransmitted. {See Processing Steps 303 and 304 in FIG. 9B} Next, another modified embodiment will be described with reference to FIG. In FIG. 10, 170, 270, and 370 are devices, respectively.
1, a reply packet monitoring circuit of the partner device in the device 2, device 3 is shown, and 19, 29, 39 show a bus use request output control circuit in the device 1, device 2, and device 3, respectively.

A plurality of devices 1, 2, and 3 are connected to a common bus (CBUS)
To send and receive packets to and from each device 1,
2 and 3 output use request signals BRQ1, BRQ2, and BRQ3 of the common bus (CBUS) having a predetermined priority, and the bus arbiter 9 existing in the data processing system uses the common bus (CBUS). Arbitrate the request signals BRQ1, BRQ2, and BRQ3, determine the device that uses the common bus according to the priority order, and provide the use permission signals BGR1, BGR2, and BGR3 for the corresponding common bus (CBUS),
If the command receiving buffer of the partner device is in a busy state (packet unreceivable state) when the permitted device transmits a packet, the packet receiving device transmits the packet to the packet transmission source device as shown in FIG. Is a data processing system that allows transfer of returning a reply packet to which information (packet type = 100) to the effect that packet retransmission is required, wherein the packet receiving side device has a command reception buffer Is busy, and the transmitting apparatus receiving the information that the new packet cannot be received, the reply packet monitoring circuits 170, 270, and 370 monitor the reply packet of the packet receiving apparatus by the reply packet monitoring circuits 170, 270, and 370. If it is confirmed that at least one normal reply packet of the device has been issued, the reply packet monitoring circuit 170,
Common bus use request output control circuit 19, 2 from 270, 370
By notifying 9, 39, the use request signal of the common bus (CBUS) can be output again.

Next, another modified embodiment of the present invention will be described with reference to FIG. In FIG. 11, as described above, BRE1, BRE2, and BRE3 are device 1, device
2.The higher priority common bus (CB
US).

In this modified example, the common bus transmitted by the transmitting side device which has obtained the information that the packet receiving side device has changed from the state in which a new packet cannot be received to the state in which the packet can be received again.
(CBUS) use request signals BRQ1, BRQ2, and BRQ3 are not permitted by the bus arbiter 9 and the common bus (CBU
When permission is given to the use request signal of (S), the device for which permission has not been given is sent to the common bus (CUBS) by the bus use request output control circuits 19, 29, and 39 of the common bus (CBUS).
Instead of the use request signals BRQ1, BRQ2, and BRQ3, the use request signals BRE1, BRE2, and BRE3 of the high-priority common bus (CBUS) are output.

The common bus (CBUS) transmitted by the transmitting device
When the use request signals BRQ1, BRQ2, and BRQ3 are not granted by the bus arbiter 9 and the use request of the common bus (CBUS) is given from another device, for example, the use of the common bus (CBUS) is performed. Monitors the response of the common bus (CBUS) to the request signal BRQ1, BRQ2, and BRQ3.Monitors the response of the BGR1, BGR2, and BGR3.
Even if the time for obtaining BGR1, BGR2, and BGR3 elapses, it can be easily recognized from the fact that the use permission signals BGR1, BGR2, and BGR3 for the common bus (CBUS) are not obtained.

Next, FIG. 12, FIG. 13 and FIG.
An embodiment corresponding to claim 6 will be described. The configuration example shown in FIG. 12 has the same basic configuration as the configuration example of FIG. 8 described above, specifically, the configuration in which the state of the reception buffer is not sent to another device. The description focuses on the components.

In the figure, reference numerals 121, 221 and 321 denote data sequence control circuits in the device 1, the device 2 and the device 3, respectively. Multiple devices 1, 2, 3
In a data processing system that transmits and receives packets to and from each other using a common bus (CBUS), a data sequence control circuit in each device controls the return timing of a return packet in response to a command packet received by each device. In such a case, it is possible to control so that a reply packet is always returned after a certain bus cycle after receiving a command packet.

As a result, it is guaranteed that a return packet is always returned within a certain period of time. Therefore, it is not necessary to hold the command packet in the command receiving buffer, and the command receiving buffer needs only one stage. Also, the command receiving buffer cannot be in a busy state.

FIGS. 13 and 14 are flowcharts showing a method of receiving a return packet in this embodiment. In the above-described data processing system, when a resource that cannot return a reply packet after a certain bus cycle, for example, data that takes a long time to process is accessed,
A return packet in a format as shown in FIG. 17 (e) is returned with a provisional return packet in which the packet type is data indicating the provisional return packet. Until the next transmission packet transmitted by the transmission source arrives, An official reply packet is prepared in a reply packet transmission buffer. ｛Figure 13
Refer to the processing steps 400, 401, and 406 to 409. The command transmission source analyzes the type of the reply packet, and if a temporary reply packet is returned, retransmits the command packet as shown in FIG. The destination replies with the formal reply packet prepared. ｛Figure 1
Refer to processing steps 500 to 502 in step 4. In the reception processing of the command packet in FIG.
After a certain time, if a reply packet can be returned,
When the reply data is prepared, a formal reply packet is created in the reply packet transmission buffer, and after the above-mentioned predetermined time has elapsed, the created formal reply packet is returned. << Refer to processing steps 400 to 409 in FIG. 13. >> By performing such a command packet receiving process, even if a resource that cannot return a reply packet after a certain bus cycle is accessed, the common bus (CBUS)
In addition, unnecessary packet transfer can be reduced.

Next, an embodiment corresponding to the eighth aspect of the present invention will be described with reference to FIG. In this figure, 32,3
Reference numeral 3 denotes a command reception buffer of the device 3, 32 is allocated as a command reception buffer for receiving a command packet from the device 1, and 33 is allocated as a command reception buffer for receiving a command packet from the device 2. And device 1 and device 2 are devices
(3) The number of command reception buffers allocated on the device is changed via a common bus (CBUS) or a dedicated signal line,
Alternatively, the number of command reception buffers can be read from the holding register 38 set via the dedicated bus BBUS and held in its own holding means 161 and 261.

The holding means 161 in the device 1 for holding the information on the number of command reception buffer stages of each destination device includes the device 3 read from the holding register 38 for holding the information on the number of command reception buffers from the destination device 3. By storing the information on the number of command reception buffer stages and transmitting this information to the transmission command packet buffers 10 and 11, for example, the number of command packets transmitted from the device 1 to the device 3 is limited to a maximum of only one packet. Further, for example, the number of command packets transmitted from the device 2 to the device 3 is limited to a maximum of only one packet.

Similarly, regarding the command transmission of the device 2 and the device 3, the number of command packets to be transmitted is limited by the number of stages of the command receiving buffer of the partner device. In this way, for a plurality of command receiving buffers of the receiving apparatus, the number of command receiving buffers exclusively used by each transmitting apparatus is determined in advance for each transmitting apparatus, and each transmitting apparatus determines itself. By having a means for controlling so that a command packet exceeding the number of command reception buffers of the partner device assigned to the device is not sent to the partner device,
Transmission of useless packets to the common bus (CBUS) can be suppressed.

[0094]

As described above in detail, according to the data processing system of the present invention, according to the first aspect of the present invention, the bus arbiter can immediately respond to the device whose command reception buffer is busy. Control can be performed so as not to give a use permission signal for the common bus (CBUS), and effective use of the common bus (CBUS) can be achieved. In addition, since the packet receiving side device can always grasp the busy state of the command receiving buffer of the partner side device, there is no need to send useless packets to the common bus (CBUS).

According to the second aspect of the present invention, the dedicated busy signal line or the dedicated bus BBUS can be shared with the transmission of the mounting information. According to the third aspect of the present invention, the state (busy state and number) of the command receiving buffer provided in each device can be recognized in advance,
According to the input / output state of the command reception buffer obtained by the means for monitoring a packet on the shared bus (CBUS) according to the invention of claim 7, a device in which the command reception buffer is busy is recognized, and the common bus (CBUS) is recognized. ) Can be eliminated.

According to the fourth aspect of the present invention, when the value of the retry counter exceeds a predetermined threshold, the common bus (C
By transmitting a use request signal having a high priority to the BUS), the use of the common bus (CBUS) is always permitted and a command packet can be transmitted to the partner device.

According to the fifth aspect of the present invention, there are a plurality of types of information that require retransmission of a command packet. Can be recognized, and it is possible to suppress the transmission of a useless command packet indicating that a reply packet requesting retransmission is returned when the command reception buffer is busy.

When a resource that cannot return a reply packet after a certain bus cycle according to claim 6 is accessed, for example, when a resource that takes a long time to process is accessed, a temporary reply packet is transmitted to allow a command in each device to be transmitted. It is possible to eliminate the accumulation of packets and reduce the possibility that the command reception buffer becomes busy.

According to the eighth aspect of the present invention, each source device transmits a command packet that exceeds the number of command reception buffers allocated to its own device among the command reception buffers of the other device. Can be controlled so as not to send the command packet to a device having a busy command reception buffer, and the common bus (CBUS) can be effectively used.

In particular, according to the invention corresponding to claims 4 to 6, since the frequency of the command packet processing of the transmission source device being waited for a predetermined time or more occurs, the command packet of the transmission source device is not easily processed and transmitted. This solves the problem that the processing performance of the original device is suppressed low.

At the same time, especially when the transmission source device is to transmit a command packet for DMA transfer from the input / output device (I / O), the command packet is not processed for a certain period of time or longer, and the input / output device ( Overrun does not occur on the I / O) side. Claim 1
The invention corresponding to No. 8 eliminates the retransmission of the sender,
Since the number of buses is reduced, unnecessary bus occupation due to retransmission is eliminated or reduced, and a decrease in the effective use efficiency of the common bus (CBUS) can be prevented. This also prevents a decrease in the processing performance of another device, and a high-performance data processing system can be constructed.

[Brief description of the drawings]

FIG. 1 is a diagram showing the principle configuration of the present invention (part 1).

FIG. 2 is a block diagram showing the principle of the present invention (part 2);

FIG. 3 is a diagram illustrating the principle of the present invention (part 3);

FIG. 4 shows an embodiment of the present invention.

FIG. 5 is a diagram illustrating a busy signal of a command reception buffer.

FIG. 6 is a diagram in which each device transmits a busy signal through a dedicated bus.

FIG. 7 is a diagram in which each device transmits a busy signal to all other devices.

FIG. 8 is a diagram showing another embodiment of the present invention.

FIG. 9 is a diagram illustrating an access request and packet processing according to the present invention.

FIG. 10 is a diagram showing a modification of another embodiment of the present invention (part 1).

FIG. 11 is a view showing a modification of the other embodiment of the present invention (part 2);

FIG. 12 is a view showing a modification of the other embodiment of the present invention (part 3).

FIG. 13 is a flowchart of a command packet receiving process of the present invention.

FIG. 14 is a flowchart of a reply packet receiving process according to the present invention;

FIG. 15 is a view showing a modification of the other embodiment of the present invention (part 4);

FIG. 16 illustrates a conventional data processing system.

FIG. 17 is a diagram showing a format example of a packet;

[Explanation of symbols]

1,2,3 Device 10,20,30 First transmission command packet buffer in each device 11,21,31 Second transmission command packet buffer in each device 12,22,32 Second transmission command packet buffer in each device 1 received command packet buffer, command received buffer 13,23,33 second received command packet buffer, command received buffer 14,24,34 in each device first received reply packet buffer in each device 15 , 25,35 Second received reply packet buffer in each device 16,26,36 Reply packet transmit buffer in each device 100,200,300 Receive packet buffer in each device CBUS Common bus (CBUS) BRQ1, BRQ2, BRQ3 Use request signal of common bus (CBUS) from device BSY1, BSY2, BSY3 Signal indicating that receive buffer of each device is busy DNOA, DONB, DONC Transmit information indicating device number of destination device to bus arbiter MODE MODE REGISTER NOT1, NOT gate AND1, AND2, AND gate OR1, OR gate BUF.FULL Signal indicating that the receiving buffer in each device is busy BBUS Dedicated bus indicating the busy status of the command receiving buffer in each device 18, 28, 38 Holding registers 101, 103 for holding information on the number of reception buffers in each device Access request generation unit for each device 102, 104 Receiving buffer busy detection unit for each device BRE1, BRE2, BRE3 Output priority of each device Use request signal for higher common bus (CBUS) 105,205,305 Access request unit to other devices in each device 106,206,306 Access request signal switching unit in each device 107,207,307 Retry counter in each device 17,27,37 Received packet monitoring in each device Circuit 19,29,39 Bus use request output control circuit in each device 121,221,321 Data sequence control circuit in each device 161,261,361 Each device Holding means 170, 270, 370 reply packet monitoring circuit 300-305,400-409,500-503 of destination device

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Isao Sasazaki 4-1-1, Kamidadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Takanori Kato 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa No. 1 Fujitsu Co., Ltd. (72) Shingo Iguchi 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture 1-1. Inside Fujitsu Co., Ltd. (72) Tatsuya Yamaguchi 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture No. 1 Fujitsu Co., Ltd. (72) Inventor Hiroyuki Imoto 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture 1-1 Inside Fujitsu Co., Ltd. (72) Inventor Junji Hirooka 4-chome, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa No. 1 Fujitsu Limited (72) Inventor Yumi Hirasawa 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu In the formula company (72) inventor Fukuoka Hideo Kawasaki City, Kanagawa Prefecture Nakahara-ku, Kamikodanaka 4 chome No. 1 Fujitsu within Co., Ltd.

Claims (8)

[Claims] A plurality of devices transmit and receive packets to and from each other using a common bus, each device outputs a request signal for use of a common bus having a predetermined priority prior to packet transmission, and a bus arbiter outputs the request signal. A data processing system comprising a control means for arbitrating a common bus use request signal, deciding a common bus use device in accordance with a priority order and giving permission, wherein each device outputs a common bus use request signal and outputs the common bus use request signal. First means for outputting information indicating the transfer destination; second means for the bus arbiter to receive the information indicating the transfer destination; and the state of the received command packet buffer of the own apparatus. A third means for transmitting information representing the following to the bus arbiter or all other devices; and the bus arbiter and the plurality of devices are provided with a reception command parameter of another device. And a fourth means for receiving information indicating the state of the packet buffer. 2. The data processing system according to claim 1, wherein said data processing system has a predetermined operation mode, and said third means for transmitting information indicating a status of a reception command packet buffer of said data processing system to said bus arbiter includes: , Transfer a signal indicating that each device is mounted, and transfer the information indicating the state of the reception command packet buffer when the initial mode is ended and the processing is shifted to a predetermined processing mode. The data processing system according to claim 1, wherein the data processing system is a means. 3. The information indicating the status of the reception command packet buffer is information indicating the number of packet reception buffers provided in each packet reception device, and whether or not the reception command packet buffer is busy. The data processing system according to claim 1, wherein: 4. A plurality of devices transmit and receive packets to and from each other using a common bus, each device normally outputs a request signal for use of a common bus having a predetermined priority, and a bus arbiter transmits the request signal to the common bus. Arbitrates the bus use request signal to determine the device using the common bus and grants permission. If the permitted device receives a packet and the received command packet buffer of the partner device is busy at the time of packet transmission, the packet receiving side The apparatus is a data processing system including a packet transfer unit that allows a packet transmission unit to transmit a return packet to which a command packet is added with information indicating that the command packet needs to be retransmitted. A retry counter is provided in the device to count the number of times a command packet has been retransmitted. After that, sending the same command packet again and incrementing the retry counter are repeated until the command packet is received by the partner device. When the retry counter becomes equal to or more than a predetermined threshold, the high priority common bus A data processing system comprising: means for sending a use request signal. 5. A plurality of devices transmit and receive packets to and from each other using a common bus, each device normally outputs a request signal for use of a common bus having a predetermined priority, and the bus arbiter transmits the request signal to the common bus. Arbitrates the bus use request signal to determine the device using the common bus and grants permission. If the permitted device receives a packet and the received command packet buffer of the partner device is busy at the time of packet transmission, the packet receiving side The apparatus is a data processing system including a packet transfer unit that allows a transfer to return a reply packet to which information indicating that a command packet needs to be retransmitted to a packet transmission source apparatus, A plurality of types of information indicating that the command packet needs to be retransmitted are provided, and the type of the information causes the packet transmission source device to repeat the same after receiving the return packet. A data processing system comprising means for changing a time until the command packet is transmitted. 6. A plurality of devices transmit and receive packets to and from each other using a common bus. Each device normally outputs a request signal for use of a common bus having a predetermined priority, and a bus arbiter transmits the request signal to the common bus. Arbitrates the bus use request signal to determine the device using the common bus and grants permission. If the permitted device receives a packet and the received command packet buffer of the partner device is busy at the time of packet transmission, the packet receiving side The apparatus is a data processing system including a packet transfer unit that allows a packet transmission apparatus to transfer a return packet to which information indicating that a command packet needs to be retransmitted is transmitted. If the receiving device accesses a resource that cannot return a reply packet after a certain bus cycle,
A data processing system comprising means for returning a temporary reply packet and preparing a formal reply packet until a command packet transmitted by the packet transmission side device arrives next time. 7. A plurality of devices transmit and receive packets to and from each other using a common bus. Each device normally outputs a request signal for use of a common bus having a predetermined priority, and the bus arbiter transmits the request signal to the common bus. A data processing system comprising a packet transfer means for arbitrating a bus use request signal, deciding a common bus using device and giving a permit, and permitting the device to transmit a packet. Means for monitoring the information of the receiving buffer by a packet on the common bus, and means for obtaining information relating to the received command packet buffers of all the apparatuses on the other side to which the own apparatus may transmit command packets by the monitoring means. A data processing system comprising: 8. A plurality of devices transmit and receive packets to and from each other using a common bus, each device outputs a request signal for use of a common bus having a predetermined priority prior to packet transmission, and a bus arbiter outputs the request signal. A data processing system comprising a control means for arbitrating a use request signal of a common bus, determining a bus use device according to a priority order, and granting a permission, wherein The number of receive command packet buffers exclusively used by each packet transmitting apparatus is predetermined for each of the packet transmitting apparatuses, and each packet transmitting apparatus has a counterpart assigned to its own apparatus. Means for controlling so that a packet exceeding the number of received command packet buffers of the device is not transmitted to the partner device. Data processing system.