JP2007095089A - Bus arbiter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bus arbiter for arbitrating a bus acquirement request form a plurality of bus masters so that definite data transfer efficiency of the first bus master is assured. <P>SOLUTION: A scanner 3 of a device equivalent to the first bus master scans a draft at constant speed and sequentially transfers the prescribed quantity of picture data to a memory 2 on a system bus in a raster system. A system control part 4 performs communication with a scanner 3 and with IEEE1394 (5) being a communication system device and transfers each command on an operation state and statuses. When the bus acquirement request from the first bus master, which is generated by the occurrence of a specified event in a device to which the bus arbiter is applied, exists, the occurrence of the event is detected and it is outputted as an event generation signal. The event generation signal is received, and frequency for giving bus use right is restricted much more than a regular case where the specified event is not generated with respect to the bus acquirement request from bus masters except for the first bus mater. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a bus arbiter, for example, a bus arbiter in a memory utilization technique of a device that performs digital processing of image information.

  Conventionally, a bus arbiter is generally applied and configured in an image processing apparatus in general, in particular, a digital copying machine, a scanner, a printer, a FAX, and the like.

  As described in Japanese Patent Application Laid-Open No. 8-149241, which is an example of a prior invention similar to the present invention in the technical field, each functional device such as a scanner, a printer, a controller having an image memory for storing an image is connected with a general-purpose bus. By connecting and sharing the interface, a system has been devised that suppresses the increase of useless circuits and control software for connecting different devices and makes the system highly scalable. .

  In such a system, when reading from the scanner and outputting an image to the plotter, in a system in which the scanner and the plotter operate at a constant speed, a certain amount of data is transferred between the image memory of the controller via the bus. Because it needs to be transferred, the bus traffic temporarily increases dramatically, and this becomes more noticeable as it becomes faster.

  By the way, it is also possible to connect a communication system interface such as IEEE1394 or USB to such a general-purpose bus, and data transmission / reception with an external device is generally performed via such an interface ( For example, see Patent Document 1).

As described above, in a configuration in which a plurality of bus masters such as a scanner, a plotter, and a communication interface device exist on the general-purpose bus, the bus arbitration method becomes important. Commonly known bus arbitration methods include a fixed priority method and a round robin method.
The former fixed priority method is a method in which a bus use right is given to a higher one according to a priority set in a fixed manner in advance when bus requests occur simultaneously. The latter round robin method is a method in which the priority is not fixed, but immediately after the right to use the bus is obtained, the priority becomes the lowest and arbitration is performed fairly as a whole.
Japanese Patent Laid-Open No. 5-46540

  However, each of the conventional arbitration methods has advantages and disadvantages. The former fixed-priority method is superior in that the device with higher priority is guaranteed to acquire the bus, but the lower device has the disadvantage that the bus cannot be acquired as long as there is a request from a device higher than itself. . In addition, the latter round robin method has the advantage that arbitration for bus acquisition is performed fairly, but conversely, when it is desired to vary the bus usage rate according to the transfer data amount and density for each device. Has the disadvantage of being unsuitable.

In the round robin method, the data transfer capability inherent to the bus itself (bus width x data transfer time per predetermined) is closer to the limit for the amount of data that devices such as scanners and plotters must transfer during operation. Even more unsuitable.
However, when the fixed priority method is adopted, when a device such as a scanner or plotter is operating, there is a situation in which other devices such as a communication interface cannot acquire a bus within the necessary period, and a communication error occurs. There is a possibility that.

  The present invention has been made in view of the above-described problems of the prior art. By having the configuration according to claim 1, the bus use of other bus masters in response to the generation of a first bus master request accompanying the occurrence of a specific event. To provide a bus arbiter that can temporarily reduce the frequency and can arbitrate so that the data transfer efficiency of the first bus master is assured without ignoring requests from a bus master having a low priority. With the goal.

  With the configuration according to claim 2, the occurrence of the event can be determined by regarding the occurrence of a certain period of time after the bus use right is given as the occurrence of the bus for the first bus master requesting the bus acquisition request accompanying the occurrence of the specific event. An object of the present invention is to provide a bus arbiter that does not require an external signal other than the arbitration relationship, and can perform arbitration so that the data transfer efficiency of the first bus master is guaranteed with a simple configuration.

  In order to solve the above-mentioned problem, the invention according to claim 1 is a bus arbiter that arbitrates bus acquisition requests from a plurality of bus masters connected to a common bus, and a specific event occurs in a device to which the bus arbiter is applied. An event detection unit that detects the occurrence of the event and outputs it as an event generation signal when there is a bus acquisition request from the first bus master that is generated, and an event occurrence from the event detection unit A bus acquisition that receives a signal and controls the bus acquisition request from a bus master other than the first bus master so as to limit the frequency of giving the bus use right compared to a normal case where a specific event has not occurred. And a frequency control unit.

  According to a second aspect of the present invention, in the first aspect of the present invention, the event detecting unit performs an event within a predetermined period after a bus use right is given to the bus acquisition request from the first bus master. It is determined that an occurrence has occurred, and an event occurrence signal is output to the bus acquisition frequency control unit.

  In response to a request from the first bus master accompanying the occurrence of a specific event, the bus usage frequency of other bus masters can be temporarily reduced, and the request from the bus master with a low priority can be ignored without ignoring the first bus master. It is possible to provide a bus arbiter capable of arbitrating so that the data transfer efficiency of the bus master is guaranteed.

  Next, an embodiment of a bus arbiter according to the present invention will be described in detail with reference to the accompanying drawings. Referring to FIGS. 1-3, one embodiment of the bus arbiter of the present invention is shown.

  Embodiments of the present invention will be described below. FIG. 1 is a system configuration diagram showing an example of an embodiment of a bus arbiter 1 according to the present invention, and shows a system configuration example in which three devices that can be a bus master and a memory 2 are connected on a system bus. . A dotted line portion in the figure is a request signal for acquiring a bus master output from each master. The bus arbiter arbitrates these request signals and grants the bus use permission to one of the three bus masters.

  The device corresponding to the first bus master according to claim 1 of the present invention is the scanner 3 in this embodiment. When reading a document, the scanner 3 scans the document at a constant speed and successively transfers a certain amount of image data to the memory 2 on the system bus in a raster format. The system control unit 4 communicates with the scanner 3 and the IEEE 1394 (5) which is a communication system device, and exchanges commands and status regarding the operation state.

  FIG. 2 shows the internal configuration of the bus arbiter 1 and the connection state of each master device. The bus arbiter 1 is composed of hardware logic, and the function will be described for each block below.

<Description of 2-1 (arbitration circuit)>
The arbitration circuit 11 is a circuit that performs round-robin arbitration, and receives a request signal for acquiring a bus from each master, and outputs a permission signal in response thereto.

<Description of 2-2 (event detection unit)>
The event detection unit 12 is configured by a counter that starts time measurement by a permission signal of the master device 1 and stops after a predetermined time measurement. During the fixed time measurement, an event occurrence signal is output to the mask time measurement unit. The master device 1 corresponds to the scanner 3 in FIG. In a state where the scanner operation is not performed, the master device 1 does not output a bus acquisition request to the bus arbiter, and therefore does not output a permission signal and does not output an event generation signal. Further, when the permission signal of the master device 1 is input during the counter measurement, the counter is initialized, and an operation for further measuring a certain time from that point is performed.

<Description of 2-3 (Mask Time Measurement Unit)>
When the permission signal is input from the arbitration circuit while the event occurrence signal from the event detection unit 12 is active, the time measurement is started, and the counter is configured to stop after the predetermined time measurement. A request mask signal is output to the request mask unit during the measurement for a certain time. The time measurement value measured by this counter can be directly rewritten by the system control unit 4 at initialization, and the bus acquisition frequency can be changed according to the type of the master device.

<Description of 2-4 (Request Mask Unit)>
While the request mask signal output from the mask time measurement unit is active, the mask acquisition circuit is configured by a gate circuit that masks the bus acquisition request signal so that the bus acquisition request from the master device is not transmitted to the arbitration circuit.
The above is the description of the configuration of the bus arbiter.

  FIG. 3 shows the bus arbitration. When there is no bus acquisition request from the bus master 1, the other bus masters 2 and 3 are not subjected to request masking and acquire the bus without any special restriction on the use of the bus. However, when the bus master 1 generates a bus acquisition request and detects the occurrence of an event, the bus masters 2 and 3 are masked for a certain period of time, thereby limiting the frequency of bus use. As a result, the bus usage frequency of other bus masters can be temporarily reduced, and arbitration is performed so that the data transfer efficiency of the first bus master is guaranteed without ignoring requests from bus masters with lower priorities. can do.

  In this embodiment, the specific event detection is performed from the permission signal for arbitration. However, it is also possible to adopt a configuration in which a device such as a scanner directly inputs to the bus arbiter.

  The above-described embodiment shows an example of a preferred embodiment of the present invention, and the present invention is not limited thereto, and various modifications can be made without departing from the scope of the invention. is there.

[Function and effect]
The bus arbiter of the present invention detects the occurrence of an event as an event occurrence signal when there is a bus acquisition request from the first bus master that occurs when a specific event occurs in a device to which the bus arbiter is applied. In response to this event occurrence signal, the frequency of giving a bus use right is limited in response to a bus acquisition request from a bus master other than the first bus master, compared to a normal case where a specific event has not occurred.

  By having this configuration, it is possible to temporarily reduce the bus usage frequency of other bus masters in response to the occurrence of a request from the first bus master accompanying the occurrence of a specific event, and to ignore requests from bus masters with low priority Without arbitration, arbitration can be performed to ensure the data transfer efficiency of the first bus master.

  According to the second aspect of the present invention, a certain period after the bus use right is given to the occurrence of the bus acquisition request of the first bus master accompanying the occurrence of the specific event is regarded as the occurrence of the event. This eliminates the need for an external signal other than the arbitration relationship when determining the occurrence of an event, and it is possible to perform arbitration so that the data and transfer efficiency of the first bus master can be guaranteed with a simple configuration.

1 is a system configuration diagram to which an embodiment of a bus arbiter of the present invention is applied. FIG. It is a figure which shows the internal structure of a bus arbiter, and the connection state of each master device. It is a figure which shows the mode of bus arbitration.

Explanation of symbols

1 Bus Arbiter 2 Memory 3 Scanner 4 System Controller 5 IEEE1394
11 Arbitration circuit 12 Event detector

Claims (2)

In the bus arbiter that arbitrates bus acquisition requests from multiple bus masters connected to a common bus,
When there is a bus acquisition request from the first bus master that occurs when a specific event occurs in the device to which the bus arbiter is applied,
An event detector that detects the occurrence of the event and outputs it as an event occurrence signal;
Frequency at which a bus use right is given to the bus acquisition request from a bus master other than the first bus master in response to an event occurrence signal from the event detection unit, compared to a normal case where no specific event has occurred A bus arbiter comprising: a bus acquisition frequency control unit that controls to limit the number of buses.   In response to the bus acquisition request from the first bus master, the event detection unit determines that an event has occurred within a certain period after giving the right to use the bus, and sends an event generation signal to the bus acquisition frequency control unit The bus arbiter according to claim 1, wherein the bus arbiter is configured to output as:

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