JP2004013395A - Dma controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To detect an overrun error of vanishing transfer data when transferring DMA to a memory from an input-output module. <P>SOLUTION: The input-output module is provided with the shortest time setting register for setting the shortest time required for preparing the next transfer data, a counter timer and a comparing circuit for measuring elapsed time from reception of a DMA transfer request signal from the input-output module. The comparing circuit compares measuring time of the counter timer with the shortest time in the shortest register, and informs the occurrence of the overrun error by sending an interrupt signal to a CPU when the measuring time of the counter timer exceeds the shortest time. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a DMA controller which controls DMA transfer of data between a memory and an input / output module of a microcomputer system, for example.
[0002]
[Prior art]
For example, in a microcomputer system, high-speed data transfer called DMA (abbreviation of Direct Memory Access) transfer between a memory and an external input / output module has been widely adopted. This is a method in which data is directly transferred between a memory and an input / output module without passing through a CPU. A circuit that controls this data transfer is called a DMA controller.
[0003]
FIG. 5 is a block diagram showing an example of the internal configuration of such a DMA controller 100, and FIG. 6 is an example of the configuration of a DMA transfer circuit using the DMA controller 100. The DMA transfer circuit includes a CPU 200, a memory 300, a DMA controller 100, a bus arbiter 400, a bus 500, input / output modules 600 and 700, and the like. The input / output modules 600 and 700 are, for example, serial communication devices, and transmit and receive data to and from an external device (not shown) by serial communication. FIG. 6 illustrates a case where the number of input / output modules is two.
[0004]
The DMA controller 100 that controls the DMA transfer includes a DMA transfer request / permission determination circuit 101, a bus right request / permission determination circuit 102, an activation control circuit 103, an address counter 104, a transfer count control circuit 105, a bus interface 106, and the like. It is configured.
[0005]
The operation of the DMA transfer under such a circuit configuration will be described by taking as an example a case where data is transferred from the input / output module 600 to the memory 300.
First, the CPU 200 prepares a write area in the memory 300 for receiving transfer data. Then, the start address of the write area is set in the address counter 104 in the DMA controller 100, and the number of transfer data is set in the transfer count control circuit 105. Then, transfer control information such as the transfer direction, the transfer source, and the transfer permission is activated. It is set in the control circuit 103.
[0006]
When the control information necessary for these transfers is set, the DMA controller 100 waits for the input of the DMA transfer request signal DREQ0 from the input / output module 600. Next, the CPU 200 sends a reception start permission signal to the input / output module 600 via the bus 500. The bus 500 includes an address bus, a data bus, and a control signal line.
[0007]
The input / output module 600 that has received the reception start permission signal starts receiving data from an external device (not shown) and sets the first received data in an internal output register. Then, a DMA transfer request signal DREQ0 is output to the DMA transfer request / permission determination circuit 101 in the DMA controller 100 so that the DMA transfer to the memory 300 is started. The DMA transfer request / permission determination circuit 101 that has received the DREQ0 signal confirms that the received DREQ signal is a request signal from the transfer source that has previously received the setting of the transfer control information from the CPU.
[0008]
After the confirmation, the DMA transfer request / permission determination circuit 101 outputs a bus right request signal BREQ to the bus arbiter 400 through the bus right request / permission determination circuit 102 to acquire the bus right. Here, the acquisition of the bus right generally means that the use permission of the bus 500 is obtained from the CPU 200 using the bus 500 (the switch 800 in FIG. 6 is switched from the CPU 200 to the DMA controller 100 and the bus 500 is transferred to the DMA controller 100). It is the bus arbiter 400 that performs arbitration (control of the switch 800) by connecting to the bus arbiter 400.
[0009]
The bus arbiter 400 that has received the bus right request signal BREQ notifies the CPU 200 that the use of the bus 500 has been requested. Then, the bus right is transferred to the DMA controller 100 by a predetermined arbitration logic (switch 800 is switched to the DMA controller 100 side, and bus 500 is connected to the DMA controller 100). To the bus right request / permission determination circuit 102 in the DMA controller 100.
[0010]
The bus right request / permission determination circuit 102 that has received the bus right permission signal BACK reports this to the DMA transfer request / permission determination circuit 101, and the DMA transfer request / permission determination circuit 101 that has received the notification sends the input / output module 600 Output a DMA transfer permission signal DACK0.
[0011]
The input / output module 600 receives the DACK0 signal and outputs the first transfer data prepared in the internal output register onto the data bus in the bus 500. Then, the DMA controller 100 operates the address bus and control lines in the bus 500 via the bus interface 106, and transfers the transfer data output on the data bus 500 to the write area in the memory 300 set in the address counter 104. Write to the start address of
[0012]
When the transfer of the first data is completed, the top address in the address counter 104 is incremented by one, and the number of data transferred in the transfer number control circuit 105 is decremented by one. Subsequently, the input / output module 600 sets the second received data in the internal output register, and then sends the DMA transfer request signal DREQ0 again so as to start the next DMA transfer. Output to the request / permission determination circuit 101.
[0013]
Thereafter, the same series of operations as described above are repeatedly performed, and when the contents of the transfer number control circuit 105 become zero, that is, when the data transfer of the initially set transfer data number is completed, a series of DMAs is performed. The transfer ends. As can be understood from the above description, in the DMA transfer, the CPU 200 simply sets the control information necessary for the DMA transfer in the DMA controller 100 and the input / output module 600 and starts the operation. Thereafter, a series of data transfer until the transfer of the designated number of data is completed is performed under the control of the DMA controller 100. Since the data transfer is performed by direct transfer between the memory 300 and the input / output module 600 without passing through the CPU 200, the data transfer by the DMA transfer has an advantage that the transfer speed is extremely high and the load on the CPU 200 is reduced. .
[0014]
[Problems to be solved by the invention]
However, during such a high-speed DMA transfer, a data transfer error may occur. One of them is a transfer error due to occurrence of an overrun error in the input modules 600 and 700. This means that, in the above example, before the transfer of the data prepared in the output register of the input / output module 600 is completed, the input / output module 600 completes the reception of the next data, and that data is used as the content of the output register. Is a transfer error that occurs when the data is updated.
[0015]
This will be described with reference to the timing charts of FIGS. The input / output module 600 sets the initially received data A in an internal output register. At the same time, it outputs a DMA transfer request signal DREQ0 to the DMA controller 100, and starts receiving the next data B itself. The DMA controller 100 acquires the bus right, sets the DMA transfer permission signal DACK0 to the “High” level, and outputs the signal to the input / output module. When the input / output module 600 that has received the DACK0 signal puts the data A in the output register onto the bus 500, the DMA controller 100 operates the address bus and control lines in the bus 500 to write the data A into the memory 300. At the end of the writing, the DMA controller 100 returns the DACK0 signal to the “Low” level.
[0016]
Here, the time required for the input / output module 600 to receive the next data B is T1, and the time from the rising of the DREQ0 signal “High” to the return of the DACK0 signal to “Low” is T2. As shown in FIG. 3, if T1> T2, the data A is normally written in the memory 300 because the data A is held in the output register during the period when the DACK0 signal is at the “High” level. .
[0017]
However, it is assumed that when the DMA transfer request signal DREQ0 is output and the DMA controller 100 outputs the BREQ signal to the bus arbiter 400 to request the bus right, the load on the bus 500 is high. Then, the bus arbiter 400 cannot immediately return the bus right grant signal BACK. In such a case, as shown in FIG. 4, the timing at which the DACK0 signal is output may be delayed, so that T1 <T2.
[0018]
When such a situation occurs, the contents of the output register are replaced with data B to be transmitted next before DACK0 goes to the “High” level or during the period of the “High” level. Then, the data A, which should have been transferred earlier, disappears without being transferred to the memory 300, and the next data B is erroneously transferred to the memory 300. This is a transfer error due to the occurrence of an overrun error.
[0019]
When the input / output module 600 sets the reception data B in the output register, it confirms that the DMA transfer of the previous data A has been completed. That is, it is confirmed that the DACK0 signal corresponding to the previous data A has once become "High" level and then returned to "Low". If this cannot be confirmed, it is determined that an overrun error has occurred, and an interrupt signal is sent to the CPU 200 to notify it. If this is the case, the CPU 200 can take a corresponding measure. However, some input / output modules do not have such a function in order to simplify circuits and reduce costs. In that case, the CPU 200 cannot recognize the occurrence of the overrun, and a problem occurs that the subsequent processing is continued based on the erroneous transfer data.
[0020]
SUMMARY OF THE INVENTION The present invention has been made in order to cope with such a problem, and it is an object of the present invention to provide a DMA controller having a function of detecting the occurrence of the overrun error as described above in place of the input / output module and reporting the occurrence to the CPU. It is an issue.
[0021]
[Means for Solving the Problems]
In order to achieve the above object, in the DMA controller of the present invention, a minimum time setting register for setting a minimum time required for the input / output module to prepare the next transfer data, a DMA transfer request from the input / output module. A counter timer for measuring an elapsed time from the reception of the signal and a comparison circuit for comparing the measured time of the counter timer with the shortest time are provided. Then, an interrupt signal is sent to the CPU when the measurement time of the counter timer exceeds the minimum time.
[0022]
As a result, the CPU can recognize that a state has occurred in which an overrun error of loss of transfer data can occur with a high probability. Therefore, it is possible to avoid an abnormal situation in which the CPU does not notice the occurrence of the overrun error and proceeds with subsequent processing based on erroneous transfer data.
[0023]
Preferably, the counter timer resets the counter timer once upon receiving a DMA transfer request signal from the input / output module. Then, the counting of the clock pulse is started immediately, and the counting is preferably stopped when the DMA transfer of one data from the DMA controller to the input / output module is completed.
[0024]
As described above, if the counter timer is reset immediately before the counting of the clock pulse for clocking is started, the previous count number is reset and accurate clocking can be performed. The counting after the end of the DMA transfer is meaningless, so it is preferable to stop counting.
[0025]
Preferably, the contents of the counter timer may be read into the CPU.
With this configuration, the CPU can recognize the time required from the start of the DMA transfer request to the end of the DMA transfer of one data.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described based on an example with reference to FIGS.
FIG. 1 is an example of an internal circuit configuration of a DMA controller 1 according to the present invention. The DMA controller 1 includes a DMA transfer request / permission determination circuit 2, a bus right request / permission determination circuit 3, an activation control circuit 4, an address counter 5, a transfer count control circuit 6, a bus interface 7, and an overrun detection circuit 8. I have. The overrun detection circuit 8 includes a shortest time setting register 8a, a counter timer 8b, and a comparison circuit 8c.
[0027]
FIG. 2 shows a configuration example of a DMA transfer circuit using the DMA controller 1. This DMA transfer circuit includes a DMA controller 1, a CPU 10, a memory 11, a bus arbiter 12, a bus 13, input / output modules 14, 15, and the like, as in the case of FIG. Here, the input / output modules 14 and 15 are external input / output devices such as a serial communication device and a floppy disk device, and FIG. 2 illustrates a case where there are two input / output modules.
[0028]
Hereinafter, an operation when the input / output module 14 performs DMA transfer of the data received (prepared) to the memory 11 under such a circuit configuration will be described.
First, the CPU 10 prepares a writing area for receiving the transfer data in the memory 11. Then, the start address of the write area is set in the address counter 5 in the DMA controller 1, the number of transfer data is set in the transfer count control circuit 6, and the control information such as the transfer direction, transfer source and transfer permission is set in the start control circuit 4. I do.
[0029]
Subsequently, the CPU 10 determines the shortest time that the input / output module 14 is expected to receive (prepare) to receive the transfer data (for example, when the input / output module 14 is a serial communication module, it receives one data from an external device). Is set in the shortest time setting register 8 a in the overrun detection circuit 8. The shortest time T1min is the expected minimum value of the data B reception time T1 in the timing chart shown in FIG. The value is stored in the memory 11 in advance for each input / output module.
[0030]
When these pieces of control information are set, the DMA controller 1 waits for the input of the DMA transfer request signal DREQ0 from the input / output module 14. Next, the CPU 10 sends a reception start permission signal to the input / output module 14 via the bus 13. The bus 13 includes an address bus, a data bus, and a control signal line.
[0031]
The input / output module 14, which has received the reception start permission signal, starts receiving data from an external device, and sets the first received data in an internal output register. Then, a DMA transfer request signal DREQ0 is output to the DMA transfer request / permission determination circuit 2 in the DMA controller 1 so that the DMA transfer to the memory 11 is started. Thereafter, the input / output module 14 starts receiving (preparing) the next data to be transferred.
[0032]
The DMA transfer request / permission determination circuit 2 that has received the DREQ0 signal outputs the bus right request signal BREQ to the bus arbiter 12 through the bus right request / permission determination circuit 3 in order to acquire the bus right from the CPU 10.
[0033]
At the same time, the DMA transfer request / permission determination circuit 2 sends a transfer request acceptance signal to the counter timer 8b, resets the counter timer 8b in the overrun detection circuit 8 once to zero, and starts counting. . The counter timer 8 counts a clock pulse (not shown) for counting a time, and measures an elapsed time from the start of counting, that is, an elapsed time Tel from when the input / output module 14 outputs the DREQ0 signal.
[0034]
The elapsed time Tel measured by the counter timer 8b is compared with the shortest time T1min previously set in the shortest time setting register 8a by the comparison circuit 8c. When it is determined that Tel ≧ T1min (1), an interrupt signal is sent from the comparison circuit 8c to the CPU 10 through the bus interface 7 and the control line in the bus 13.
It is preferable that the contents of the counter timer 8b can be read by the CPU 10.
[0035]
Subsequent operations are divided into a case where the condition of the above expression (1) is satisfied and a case where the condition is not satisfied during the first data DMA transfer. First, the operation when the condition of the above equation (1) is not satisfied during transfer will be described.
The bus arbiter 12 that has received the bus right request signal BREQ notifies the CPU 10 that the use of the bus 13 has been requested. Then, the bus right is transferred to the DMA controller 1 by a predetermined arbitration logic (switch 16 is switched to the DMA controller 1 side, and bus 13 is connected to the DMA controller 1). To the bus right request / determination circuit 3.
[0036]
The bus right request / permission determination circuit 3 that has received the bus right permission signal BACK reports this to the DMA transfer request / permission determination circuit 2. The DMA transfer request / permission determination circuit 2 that has received the notification outputs the DMA transfer permission signal DACK0 to the input / output module 14.
[0037]
The input / output module 14 receives the DACK0 signal and outputs the first transfer data prepared in the internal output register onto the data bus in the bus 13. Then, the DMA controller 1 operates the address bus and the control line in the bus 13 via the bus interface 7 to transfer the transfer data output on the data bus to the head address of the write area set in the address counter 5. Write.
When the writing is completed, the DMA transfer request / permission determination circuit 2 returns the DACK0 signal to the “Low” level. At the same time, that is, simultaneously with the end of the transfer of the first data, a transfer permission end signal is sent to the counter timer 8b to stop counting.
[0038]
When the transfer of the first data is completed in this way, the top address in the address counter 5 is incremented by one, and the number of transfer data in the transfer number control circuit 6 is decremented by one. The input / output module 14 prepares data to be transferred next in an internal output register, and sends a DMA transfer request signal DREQ0 again to start the next DMA transfer, to the DMA transfer request / permission determination circuit in the DMA controller 1. Output to 2. The above series of operation timings are the same as those shown in FIG. 3 described above.
Thereafter, by repeating such a series of operations, data transfer is performed for the number of transfer data initially set in the transfer number control circuit 6, and a series of DMA transfer ends.
[0039]
Next, the operation when the condition of the above equation (1) is satisfied during the transfer will be described. This is a case corresponding to the timing chart shown in FIG.
The input / output module 14 sets the first transfer data in an internal output register. Then, a DMA transfer request signal DREQ0 is output to the DMA transfer request / permission determination circuit 2 in the DMA controller 1 so as to start the DMA transfer. Thereafter, the input / output module 14 starts receiving (preparing) the next data to be transferred.
[0040]
The DMA transfer request / permission determination circuit 2 that has received the DREQ0 signal sends the bus right request signal BREQ to the bus arbiter 12 through the bus right request / permission determination circuit 3 to acquire the bus right from the CPU 10. Then, it acquires the bus right and returns the DACK0 signal to the input / output module 14. However, in this case, the condition of the above expression (1) is satisfied until the output of the DACK0 signal is completed, that is, after the DACK0 signal once becomes the “High” level and before returning to the “Low” level.
[0041]
It is assumed that the operation is continued as it is when the condition of the expression (1) is satisfied. Then, as shown in the timing chart of FIG. 4, at the moment when the data is written to the memory 11 by the DACK0 signal, the contents of the output register of the input / output module 14 are not the data A to be transferred but the data to be transferred next. There is a high possibility that the data A has been replaced with the data B to be set. (Since the set time T1min is the shortest expected time of T1, the data A may remain in the output register even if the elapsed time Tel exceeds T1min. obtain).
[0042]
As soon as the condition of the expression (1) is satisfied, an interrupt signal is sent to the CPU 10 from the comparison circuit 8c. As a result, the CPU 10 can recognize that data has been lost due to abnormal transfer, that is, a state in which an overrun error has a high probability has occurred.
[0043]
If the CPU 10 proceeds with the subsequent processing without recognizing the occurrence of such a state, an irreversible situation may occur in which processing based on incorrect transfer data is performed. However, according to the configuration of the present invention, the CPU 10 can recognize in advance that such a situation has occurred. Accordingly, it is possible to take measures such as aborting the subsequent processing or discarding the transfer data and generating a transfer request again to the input / output module 14, thereby avoiding an irreversible situation. .
[Brief description of the drawings]
FIG. 1 is a configuration block diagram of a DMA controller of the present invention.
FIG. 2 is a configuration example of a DMA transfer circuit using a DMA controller of the present invention.
FIG. 3 is a timing chart when DMA transfer is performed normally.
FIG. 4 is a timing chart when an overrun error occurs in a DMA transfer.
FIG. 5 is a diagram corresponding to FIG. 1 showing a conventional technique.
FIG. 6 is a diagram corresponding to FIG. 2, showing a conventional technique.
[Explanation of symbols]
In the drawing, 1 is a DMA controller, 8 is an overrun detection circuit, 8a is a shortest time setting register, 8b is a counter timer, 8c is a comparison circuit, 10 is a CPU, 11 is a memory, 12 is a bus arbiter, and 14 and 15 are input / output. Module.

Claims (3)

A DMA controller for controlling DMA transfer of data between an input / output module and a memory,
A minimum time setting register that sets the minimum time required for the input / output module to prepare the next transfer data;
A counter timer for measuring an elapsed time since receiving the DMA transfer request signal from the input / output module;
A comparison circuit that compares the measurement time of the counter timer with the minimum time and sends an interrupt signal to the CPU when the measurement time exceeds the minimum time;
A DMA controller comprising: After receiving the DMA transfer request signal from the input / output module and resetting the counter timer, the counter timer immediately starts counting clock pulses for clocking, and outputs one data from the DMA controller to the input / output module. 2. The DMA controller according to claim 1, wherein counting is stopped when the DMA transfer is completed. 3. The DMA controller according to claim 1, wherein the content of the counter timer can be read into a CPU.

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