JP4152387B2 - Bus system - Google Patents

Description

  The present invention relates to a bus system, and more particularly, to a bus system and a retry method for optimizing a retry interval when a transfer request from a master device is rejected by a slave so as to avoid occurrence of a live lock.

  FIG. 12 shows an example of a conventional bus system. The first master device composed of the master unit 1-1 and the master interface 91-1 and the second master device composed of the master unit 1-2 and the master interface 91-2 transfer commands, addresses, write data, and the like. Connected to the CW bus 3. A slave device including the slave unit 5 and the slave interface 92 is connected to the CW bus 3. The master interface 91-1 of the first master device, the master interface 91-2 of the second master device, and the slave interface 92 of the slave device are connected to the RD bus 6 that transfers read data.

  Transfer request REQm1, command CMDm1, address ADm1, and write data WDm1 are sent from master unit 1-1 of the first master device to master interface 91-1. In the reverse direction, the command acknowledge CACKm1 and the bus error signal BERm1 are sent from the master interface 91-1 to the master unit 1-1. Also, a transfer request REQb, a command CMDb, and address / write data AD / WDb are sent from the master interface 91-1 to the slave interface 92 of the slave device via the CW bus 3. In the reverse direction, a confirmation response ACKb and a negative response NACKb are sent from the slave interface 92 to the master interface 91-1 via the CW bus 3.

  Similarly, a transfer request REQm2, a command CMDm2, an address ADm2, and write data WDm2 are sent from the master unit 1-2 of the second master device to the master interface 91-2. In the reverse direction, the command acknowledge CACKm2 and the bus error signal BERm2 are sent from the master interface 91-2 to the master unit 1-2. Also, a transfer request REQb, a command CMDb, and multiplexed address / write data AD / WDb are sent from the master interface 91-2 to the slave interface 92 of the slave device via the CW bus 3. In the reverse direction, a confirmation response ACKb and a negative response NACKb are sent from the slave interface 92 to the master interface 91-2 via the CW bus 3.

  A transfer request REQs, a command CMDs, an address ADs, and write data WDs are sent from the slave interface 92 of the slave device to the slave unit 5. In the reverse direction, command acknowledge CACKs are sent from the slave unit 5 to the slave interface 92.

  As for the read data, read data RDs is sent from the slave unit 5 to the slave interface 92. Read data RDb is sent from the slave interface 92 to the master interface 91-1 of the first master device or the master interface 91-2 of the second master device via the RD bus 6. In the first master device, read data RDm1 is sent from the master interface 91-1 to the master unit 1-1, and in the second master device, read data RDm2 is sent from the master interface 91-2 to the master unit 1-2.

  An arbitration circuit 7 is provided to determine the right to use the CW bus 3. A bus usage right request AREQm1 is sent from the master interface 91-1 of the first master device to the arbitration circuit 7, and a bus usage right request AREQm2 is sent from the master interface 91-2 of the second master device to the arbitration circuit 7. When the arbitration circuit 7 gives the right to use the CW bus 3 to the first master device, the arbitration circuit 7 sends a grant signal AGNTm1 to the master interface 91-1. When the arbitration circuit 7 gives the right to use the CW bus 3 to the second master device, the arbitration circuit 7 sends a grant signal AGNTm2 to the master interface 91-2.

  FIG. 13 is an internal block diagram of a portion related to the CW bus 3 of the master interface 91. In FIG. 13, a portion related to the RD bus 6, that is, a portion related to reception of read data is omitted. The master protocol control circuit 11 receives a transfer request and a command from the master unit 1 and controls communication between the master unit 1 and the slave device based on the protocol. The retry interval value register 12 stores a preset retry interval value RIN. The retry interval counter 13 resets the count value when receiving a negative response NACKb, and then increments the count value every time a clock CLK pulse is input to count the number of clock pulses. The comparator 14 detects that the count value of the retry interval counter 13 matches the retry interval value RIN, and sets the retry time notification signal RT to the active level. The retry number register 15 stores an allowable retry number PRC in advance. The retry number counter 16 is incremented every time a negative response NACKb is received after the count value is reset by the transfer request REQm from the master unit 1. The comparator 17 detects that the count value has become larger than the allowable retry count PRC in the retry count register 15, and sets the overflow signal OF to the active level. When the retry request circuit 18 detects that the retry time notification signal RT has changed to the active level when the overflow signal OF is at the inactive level, the retry request circuit 18 sends a retry activation request signal RRQ to the master protocol control circuit 11. When the retry activation request signal RRQ is received, the master protocol control circuit 11 retransmits the transfer request REQb, the command CMDb, and the address (AD / WD address part). The bus error determination circuit 19 detects that the overflow signal OF has changed to the active level, and outputs a bus error signal BERm.

  FIG. 14A is an operation sequence diagram of the conventional bus system shown in FIGS. FIG. 14A shows the operation when two master devices send and receive a read transfer request to one slave device before and after, referring to this, the conventional bus system of FIG. The operation of will be described.

  At time T11, the transfer request REQm1 is sent from the master unit 1-1 to the master interface 91-1. At the same time, the address ADm1, the command CMDm1, etc. are simultaneously passed to the master interface 91-1.

  The master interface 91-1 requests the arbitration circuit 7 to use the right to use the CW bus 3. When the right to use the bus is granted and the CW bus 3 becomes unused, the transfer request REQb on the CW bus 3. Put out. The retry counter 16 in the master interface 91-1 is reset to zero.

  The slave interface 92 receives the transfer request REQb, the address / write data AD / WDb, and the command CMDb from the master unit 1-1 via the CW bus 3, and according to the received command CMDb and the status of the slave unit 5, It is determined whether the transfer request REQb is received or rejected. Since the slave unit 5 is in a receivable state, the slave interface 92 outputs an acknowledgment ACKb on the CW bus 3 and transmits a transfer request REQs to the slave unit 5.

  When receiving the acknowledgment ACKb, the master interface 91-1 sends a command acknowledge CACKm1 to the master unit 1-1. At the same time, data phase transfer is started. In the data phase, the master interface 91-1 requests write data from the master unit 1-1 if it is a write, and outputs the received data to the CW bus 3. Then, a predetermined time is waited until read data is prepared.

  On the other hand, assume that a transfer request REQm2 is sent from the master unit 1-2 to the master interface 91-2 at time T12. At the same time, the address ADm2, the command CMDm2, etc. are passed to the master interface 91-2.

  The master interface 91-2 requests the right to use the CW bus 3 from the arbitration circuit 7, waits until the CW bus 3 is released because it is in use, and if the right to use the bus is granted, A transfer request REQb is issued. The retry counter 16 of the master interface 91-2 is reset to zero.

  The slave interface 92 receives the transfer request REQb, address ADb, and command CMDb from the master unit 1-2 via the CW bus 3. However, since the slave unit 5 is busy with the transfer request processing from the master unit 1-2, the slave interface 92 determines to reject the transfer request REQb and returns a negative response NACKb.

  When the master interface 91-2 receives the negative response NACKb, the master interface 91-2 opens the CW bus 3 and then increments the count value of the retry counter 16 and is greater than the allowable retry count PRC stored in the retry count register 15 or not. Determine whether. When the count value exceeds the allowable retry count PRC, the bus error determination circuit 19 outputs the bus error signal BERm1, but in the case of FIG. 14A, the count value is smaller than the allowable retry count PRC. Therefore, the master interface 91-2 waits for a time (retry interval time) Tri until the retry interval counter 13 counts the number of clock pulses corresponding to the number of retry interval values RIN stored in the retry interval value register 12.

  The slave interface 92 receives the read data RDs from the slave unit 5 and outputs the read data RDb to the RD bus 6 when read data transfer preparation for the transfer request from the master interface 1-1 is completed.

  The master interface 91-1 receives the read data RDb via the RD bus 6 and transmits the read data RDm1 to the master unit 1-1. At time T13, the master unit 1-1 receives the read data RDm1, and completes the read transfer request processing of the master unit 1-1.

  On the other hand, in the master interface 1-2, when the count value of the retry interval counter 13 reaches the retry interval value RIN, the protocol control circuit 11 requests the arbitration circuit 7 for the right to use the CW bus 3 again. When the bus use right is granted, a transfer request REQb is output on the bus.

  The slave interface 92 receives the transfer request REQb, the address ADb, and the command CMDb from the master unit 1-2 via the CW bus 3, and this time the slave unit 5 is in a receivable state. An acknowledgment ACKb is output on the bus 3 and a transfer request REQs is transmitted to the slave unit 5.

  When the master interface 91-2 receives the confirmation response ACKb, the master interface 91-2 sends a command acknowledge CACKm2 to the master unit 1-2, and waits for a predetermined time until the CW bus 3 is released and read data is prepared. The slave interface 92 receives the read data RDs from the slave unit 5 and outputs the read data RDb to the RD bus 6 when read data transfer preparation for the transfer request from the master interface 1-2 is completed. The master interface 91-2 receives the read data RDb via the RD bus 6 and transmits the read data RDm2 to the master unit 1-2. At time T14, the master unit 1-2 receives the read data RDm2, and completes the read transfer request processing of the master unit 1-2.

  The timing chart of FIG. 14B shows the operation described above with reference to FIG. 14A. In FIG. 14B, the bus use right request AREQm1 from the master interface 91-1 to the arbitration circuit 7, the grant signal AGNTm1 for granting the bus use right from the arbitration circuit 7 to the master interface 91-1, and the master interface 91. 2 also shows a bus use right request AREQm2 from -2 to the arbitration circuit 7 and a bus use right grant signal AGNTm2 from the arbitration circuit 7 to the master interface 91-2.

  In the conventional bus system, even when transfer requests are concentrated from a plurality of master units to one slave unit, a plurality of transfer requests can be adjusted and responded.

  However, for example, in FIG. 12, a transfer request ACKb from the master unit 1-1 to the slave unit 5 is periodically generated, and this is a cycle of the transfer request ACKb generated by the master unit 1-2 based on the retry interval value RIN. May coincide with a situation in which the transfer request from the master unit 1-2 continues to be rejected and not executed. This is called live lock, and the transfer efficiency of the bus is remarkably lowered. Therefore, it is necessary to prevent the occurrence and to quickly eliminate it when it occurs.

  FIG. 15 is an operation sequence diagram showing the occurrence of live lock. At time T1, the transfer request REQm1 is transmitted from the master unit 1-1, and at time T2, the transfer request REQm2 is transmitted from the master unit 1-2. Is received and the slave unit 5 is in a busy state, the transfer request from the master unit 1-2 is rejected by the slave interface 92, and a negative response NACKb is returned to the master interface 91-2. The slave interface 92 receives the negative response NACKb and starts measuring the retry interval time Tri.

  On the other hand, read data RDm1 corresponding to the transfer request of the master unit 1-1 is transferred from the slave unit 5 to the master unit 1-1 via the RD bus 6 at time T3, and the read process is completed. Immediately after that, the master unit 1-1 transmits the next transfer request REQm1, so that the transfer request from the master unit 1-1 is accepted and the slave unit 5 becomes busy again.

  The master interface 91-2 detects that the retry interval time Tri has elapsed and resends the transfer request REQb to the slave interface 92, but is rejected because the slave unit 5 is busy, and the negative response NACKb is the master response. It is returned again to the interface 91-2. The master interface 91-2 receives the negative response NACKb and starts again the retry interval time Tri.

  In the case of FIG. 15, since the transmission cycle of the transfer request from the master unit 1-1 coincides with the cycle of retransmission of the transfer request of the master interface 91-2, the transfer request from the master unit 1-1 is thereafter performed. Only runs continuously. Since the transfer request from the master unit 1-2 continues to be rejected, the live lock state is entered.

  In order to eliminate this when the live lock occurs, the transfer request of the master device (master unit 1-1 in FIG. 15) that periodically issues the transfer request is suspended, or the live It is necessary to change either the retry interval time until the master device in the locked state (master interface 91-2 in FIG. 15) retransmits the transfer request.

  As a method of temporarily stopping a master device that periodically requests transfer, JP 2000-315188 A discloses a master device in a live lock state when a bus lock is monitored and a live lock is detected. Discloses a technique for controlling the bus to be used exclusively. Although it is possible to reliably cancel live lock by using this technology, each of the live lock detection circuits for detecting whether or not the live lock state is present in the bus use right arbitration circuit. Since it is necessary to provide a circuit for setting the exclusive use of the bus for the master device that is provided corresponding to the master device and the live lock state is detected, the amount of hardware of the bus use right arbitration circuit is greatly increased. Resulting in.

  In order to change the retry interval time of the master device in the live lock state, in Japanese Patent Laid-Open No. 9-114750, the master device has a plurality of retry interval time registers and is set to the retry interval time of the first register. When a negative response is received continuously for a predetermined number of times, the second register is changed to a different retry interval, and when a predetermined number of negative responses are still received, it is changed to the third register. A technique for sequentially setting different retry interval times is disclosed. However, when multiple slave devices are connected to the bus, the time required for the slave device to read / write depends on the function of the slave device, such as whether the slave device is a high-speed memory or a low-speed peripheral device. Different. For this reason, an appropriate retry interval time is also different for each slave device to which a transfer request is made. Therefore, when a large number of slave devices are connected to the bus, a register group including a plurality of registers per slave device is formed in each master device, and a plurality of slave devices corresponding to the plurality of slave devices are provided. The number of register groups must be provided, which greatly increases the amount of hardware of the master device.

  Japanese Patent Laid-Open No. 2000-250850 includes a first time table in which basic retry interval times are stored in a slave device and a second time table in which a retry interval time shorter than this is stored. A technique for notifying the master device of the retry interval time of the first time table when returning a negative response, and notifying the master device of the retry interval time of the second time table when returning a negative response after the second time is disclosed. Has been. After receiving the first negative response, the master device retransmits the transfer request after the basic retry interval time of the first time table has elapsed, and after receiving the negative response for the second and subsequent times, Resend the transfer request after the retry interval has elapsed. In this technique, since the slave device stores a unique basic retry interval time, it is not necessary to store the retry interval time suitable for each slave device on the master side. However, there is a possibility that a live lock may occur when the retry interval time of the second time table coincides with the period of the transfer request from another master device. This is not a solution to the problem once the live lock is entered. However, in this technique, if the retry interval time of the second time table is set to an extremely short time, the right to occupy the bus can be substantially monopolized. Therefore, a transfer request from the master device that has received two or more negative responses is received. It is preferentially processed, and it is possible to prevent a live lock from occurring. However, since the bus is monopolized in this way, when the slave device to be transferred is a device that takes time to read / write like a peripheral device, other master devices and slave devices connected to the bus The transmission / reception between them is stopped for a long time, and the bus use efficiency is greatly reduced.

  The object of the present invention is to prevent the occurrence of live lock, and to eliminate this even when the live lock state occurs, and increase the amount of hardware for realizing this. An object of the present invention is to provide a bus system and a retry method that can be made smaller than before.

  A bus system according to a first aspect of the present invention includes a retry setting value storage circuit that is provided between a slave unit and a bus and stores a retry setting value uniquely determined for the slave unit, and a pseudo random number. A negative response including a retry setting value and a random value generated by the pseudo-random number generator and a negative response when rejecting a response to the transfer request from the master unit. A slave interface for transmitting incidental information to the master unit via the bus, and provided between the master unit and the bus, adds the retry setting value extracted from the negative acknowledgment incidental information and the random value. An adder and a retry interval value storage circuit for storing the addition result as a retry interval value, and transfer is required based on the retry interval value. And a master interface to determine a time before retransmitting, configured with a.

A bus system according to a second aspect of the present invention includes a retry setting value storage circuit that is provided between a slave unit and a bus and stores a retry setting value that is uniquely determined for the slave unit. A slave interface that transmits a negative response when rejecting a response to the master unit and transmits negative response-accompanying information including the retry setting value to the master unit via the bus, and is provided between the master unit and the bus. A pseudo-random number generator that generates random numbers, an adder that adds the generated random number value and the retry setting value extracted from the negative acknowledgment additional information, and a retry interval that stores the addition result as a retry interval value A master storage unit for determining a time until a transfer request is retransmitted based on the retry interval value. Configured to have and over the face, the.

A bus system according to a third aspect of the present invention is provided between a slave unit and a bus, receives a transfer request and an address from a master unit via the bus, and if it is a transfer request to the slave unit, an address condition detection signal An address decoder that outputs, and determines whether to respond to a transfer request from the master unit from the address condition detection signal, a command from the master unit, and an operation state of the slave unit, and confirms to the bus when a response is possible A response condition determination circuit that outputs a response and outputs a negative response to the bus when a response is impossible, a retry setting value storage circuit that stores a retry setting value uniquely determined for the slave unit, and the negative response When it is output, the information accompanying the negative response including the retry setting value is output to the bus. Retrieval information extraction provided between the bus and the master unit, inputting the negative response incidental information from the bus, extracting the retry setting value, and outputting the slave interface provided with a constant response incidental information generation circuit A circuit, a pseudo random number generator that is activated by a predetermined signal to generate pseudo random numbers, and adds the retry setting value and the random number value generated by the pseudo random number generator to calculate a retry interval value An adder, a retry interval counter that starts counting clock pulses by receiving the negative response, detects that the count value is equal to the retry interval value, and outputs a retry time notification signal; When the transfer request is received, counting of the number of times of negative acknowledgment is started, and the count value is larger than the preset allowable retry count. A retry request circuit that starts the retry count counting section for outputting an overflow signal, retransmits the detected and forwards the request to the overflow signal is the retry time notification signal at the inactive level becomes an active level out, and is configured with a, a master interface with a.

  By applying the present invention, it is possible to prevent the occurrence of a live lock, and it is possible to eliminate this even if the live lock state occurs very rarely. Further, since the retry setting value SRI is sent from the slave device that requested the transfer and is set to a value uniquely set in the slave device, when various slave devices having greatly different transfer preparation times are connected to the bus. In addition, the retry interval time can be set to an appropriate range for each slave device. Further, the amount of hardware added to avoid live lock can be significantly reduced as compared with the bus system according to the technique described in JP-A-9-114750, and the technique described in JP-A-2000-250850 is disclosed. It is also possible to avoid a decrease in bus use efficiency due to bus monopoly that occurs when live lock is avoided by using.

The present invention relates to a time until a transfer request is retransmitted from a master device to a slave device on the basis of a retry interval value obtained by adding a retry setting value uniquely determined for the slave device and a random value generated with a pseudo-random number. This point is common to the following embodiments. Hereinafter, the present invention will be described in detail with reference to the drawings.

  1, 2 and 3 are diagrams for explaining a first embodiment of the bus system of the present invention. In the first embodiment, random values are generated by the slave interface and added by the master interface. FIG. 1 is a block diagram of a master interface, FIG. 2 is a block diagram of a slave interface, and FIG. 3 is a diagram illustrating an example of a bus system.

  First, the entire bus system will be described with reference to FIG. The bus system according to the first embodiment includes a slave interface 4 that outputs negative response-accompanying information NAINFb in addition to input / output similar to the slave interface 92, instead of the slave interface 92 in the conventional bus system of FIG. . Further, the bus system of the first embodiment is replaced with the master interfaces 91-1 and 91-2, and the master interfaces 2-1 and 2- 2 is provided. Hereinafter, the configuration of the bus system will be described.

  The first master device comprising the master unit 1-1 and master interface 2-1 and the second master device comprising the master unit 1-2 and master interface 2-2 transfer commands, addresses, write data, etc. Connected to the CW bus 3. A slave device comprising the slave unit 5 and the slave interface 4 is connected to the CW bus 3. The master interface 2-1 of the first master device, the master interface 2-2 of the second master device, and the slave interface 4 of the slave device are connected to an RD bus 6 that transfers read data.

  A transfer request REQm1, a command CMDm1, an address ADm1, and write data WDm1 are sent from the master unit 1-1 of the first master device to the master interface 2-1. In the reverse direction, a command acknowledge CACKm1 and a bus error signal BERm1 are sent from the master interface 2-1 to the master unit 1-1. The command acknowledge CACKm1 notifies that the master interface 2-1 has received the confirmation response ACKb from the slave device. Further, a transfer request REQb, a command CMDb, and address / write data AD / WDb are sent from the master interface 2-1 to the slave interface 4 of the slave device via the CW bus 3. In the reverse direction, an acknowledgment ACKb, a negative response NACKb, and negative response supplementary information NAINFb are sent from the slave interface 4 to the master interface 2-1 via the CW bus 3.

  Similarly, a transfer request REQm2, a command CMDm2, an address ADm2, and write data WDm2 are sent from the master unit 1-2 of the second master device to the master interface 2-2. In the reverse direction, the command acknowledge CACKm2 and the bus error signal BERm2 are sent from the master interface 2-2 to the master unit 1-2. Also, a transfer request REQb, a command CMDb, and multiplexed address / write data AD / WDb are sent from the master interface 2-2 to the slave interface 4 of the slave device via the CW bus 3. In the reverse direction, acknowledgment response ACKb, negative response NACKb, and negative response supplementary information NAINFb are sent from slave interface 4 to master interface 91-2 via CW bus 3.

  A transfer request REQs, a command CMDs, an address ADs, and write data WDs are sent from the slave interface 4 of the slave device to the slave unit 5. In the reverse direction, command acknowledge CACKs are sent from the slave unit 5 to the slave interface 4. The command acknowledge CACKs notifies that the slave unit 5 can receive the next command.

  As for the read data, read data RDs is sent from the slave unit 5 to the slave interface 4. Read data RDb is sent from the slave interface 4 via the RD bus 6 to the master interface 2-1 of the first master device or the master interface 2-2 of the second master device. In the first master device, read data RDm1 is sent from the master interface 2-1 to the master unit 1-1, and in the second master device, read data RDm2 is sent from the master interface 2-2 to the master unit 1-2.

  An arbitration circuit 7 is provided to determine the right to use the CW bus 3. A bus use right request AREQm1 is sent from the master interface 2-1 of the first master device to the arbitration circuit 7, and a bus use right request AREQm2 is sent from the master interface 2-2 of the second master device to the arbitration circuit 7. When the arbitration circuit 7 gives the right to use the CW bus 3 to the first master device, the arbitration circuit 7 sends a grant signal AGNTm1 to the master interface 2-1. When the arbitration circuit 7 grants the right to use the CW bus 3 to the second master device, the arbitration circuit 7 sends a grant signal AGNTm2 to the master interface 2-2.

  Next, FIG. 1 will be described. FIG. 1 shows an internal block of a portion related to the CW bus 3 of the master interface 2a of the first embodiment, and a portion related to the RD bus 6, that is, a portion related to reception of read data is omitted.

  In the master interface 2a, the master protocol control circuit 11 receives the transfer request REQm and the command CMDm from the master unit 1, and controls communication between the master unit 1 and the slave device based on the protocol. The retry information extraction circuit 31 extracts the retry setting value SRI and the random value RN from the negative response supplementary information NAINFb transmitted from the slave interface 4a. When the retry setting value SRI is coded, decoding is also performed. For example, when the retry setting value SRI of each of four slave devices is 10, 50, 100, 200 in decimal, 10 is (00), 50 is (01), 100 from the slave device. (10) and 200 are encoded and transmitted as in (11), and the retry information extraction circuit 31 includes a decoding circuit (or a decoding reference table), each of which is set to the original retry setting value 10, 50, 100, Restore to 200. In this example, when decimal 200 is transmitted as it is, 8 bits are required, but in this example, it is possible to transmit with 2 bits by encoding. The adder 32 adds the retry setting value SRI and the random number value RN and outputs a retry interval value RIN.

  The retry interval counter 33 counts the pulses of the clock CLK after receiving the negative response NACKb, detects that the number of retry interval values RIN has been reached, and sets the retry time notification signal RT to the active level. For example, the retry interval counting unit 33 increments the count value every time a pulse of the clock CLK is input after resetting the count value when the retry interval value register 12 holding the retry interval value RIN and the negative response NACKb are received. A retry interval counter 13 that counts the number of clock pulses, and a comparator 14 that detects that the count value of the retry interval counter 13 matches the retry interval value RIN and sets the retry time notification signal RT to an active level. . For example, in consideration of a shift due to clock time consumption due to circuit operation such as addition, the value set in the retry interval value register is set as a value corrected by increasing / decreasing the predetermined number α with respect to the calculated retry interval value RIN. May be.

  The retry count counter 34 counts the number of times of negative acknowledgment NACKb received after receiving the transfer request REQm from the master unit 1, and detects that the count value is larger than the preset allowable retry count PRC. Then, the overflow signal OF is set to the active level. For example, the retry count counting unit 34 resets the count value in response to the retry count register 15 and the transfer request REQm from the master unit 1 when a predetermined allowable retry count PRC is stored in advance, and each time a negative response NACKb is received. And a comparator 17 that detects that the count value has become larger than the allowable retry count PRC of the retry count register 15 and sets the overflow signal OF to an active level.

  When the retry request circuit 18 detects that the retry time notification signal RT has changed to the active level when the overflow signal OF is at the inactive level, the retry request circuit 18 sends a retry activation request signal RRQ to the master protocol control circuit 11. When the retry activation request signal RRQ is received, the master protocol control circuit 11 retransmits the transfer request REQb, the command CMDb, and the address (AD / WD address part). The bus error determination circuit 19a detects that the overflow signal OF has changed to an active level, and outputs a bus error signal BERm. Further, the bus error determination circuit 19a determines the negative response cause information portion of the negative response incidental information NACKb, and the bus error signal is used even when the retry is useless because the command is not supported by the slave device. BERm is output.

  Next, FIG. 2 will be described. FIG. 2 shows an internal block of a portion related to the CW bus 3 of the slave interface 4a of the first embodiment, and a portion related to the RD bus 6, that is, a portion related to reception of read data is omitted.

  In the slave interface 4a, the address decoder 21 receives from the master unit 1 via the master interface 2a and the CW bus 3 and the address portion of the address / write data AD / WD multiplexed with the transfer request REQb. If it is a transfer request to itself, an address condition detection signal ACD is output. The slave protocol control circuit 22 receives the address condition detection signal ACD and the command CMDb from the master device, and controls communication between the master device and the slave unit 5 based on the protocol.

  The slave state holding circuit 23 inputs and holds slave state information indicating whether the slave unit 5 is in a state where it can process a transfer request or is in a busy state where it cannot be processed. The response condition determination circuit 24 determines whether or not to respond to the transfer request REQb from the address condition detection signal ACD, the command CMDb, and the slave state information held in the slave state holding circuit 23, and when the response is possible, the CW bus 3 The confirmation response ACKb is output to the terminal, and when the response is impossible, the negative response NACKb is output.

  The negative response cause information generation circuit 25 refers to the slave state information held in the slave state holding circuit 23 and generates information related to the cause of returning the negative response NACKb. For example, information such as that the slave unit is busy or that the received command is not supported by the slave device is encoded and generated.

  A retry setting value register 41, which is a retry setting value storage circuit, stores retry setting values SRIs that are uniquely determined for the slave unit. When the retry setting value is encoded and sent from the slave unit, the retry setting value SRIs is stored in the encoded state.

  The pseudo random number generator 42 is activated by a predetermined signal to generate pseudo random numbers. In FIG. 2, the negative response NACKb is used as the predetermined signal, but the address condition detection signal ACD that is the output of the address decoder 21 may be used instead of the negative response NACKb. When the address condition detection signal ACD is used, since the random number value RNs can be generated prior to the transmission of the negative response NACKb from the response condition determination circuit 24, the pseudo random number generator 42 operates at high speed. There is an advantage that it is not required. When the response determination result is the confirmation response ACKb, the generated random number value RNs is discarded as it is.

  When the negative response NACKb is output, the negative response incidental information generation circuit 43 multiplexes the negative response cause information NAI, the retry setting value SRIs, and the random value RNs to generate negative response additional information NAINFb, and generates the CW bus 3 Output to. The negative response-accompanying information generation circuit 43 is configured by using, for example, a multiplexer 44 whose output is selected and controlled by a slave protocol control device. In the transfer of the negative response supplementary information NAINF, the negative response cause information NAI, the retry set value SRIs, and the random value RNs are sequentially transferred according to the order set by the slave protocol control circuit 22 by a single signal line or signal line group. The

  Alternatively, the negative response cause information NAI, the retry setting value SRIs, and the random value RNs constituting the negative response incidental information NAINF may be separately transferred by a plurality of signal lines or signal line groups. When configured, the negative response incidental information generation circuit 43 can be omitted.

  Next, the operation of the first embodiment of the present invention will be described with reference to FIGS. FIG. 4 is an operation sequence diagram of the first embodiment. As in the case of FIG. 15 where live lock occurs in the conventional example, a transfer request ACKb from the master unit 1-1 to the slave unit 5 is periodically generated, and this is set to the retry interval value RIN by the master unit 1-2. A case will be described as an example in which the initial setting is made to coincide with the cycle of the transfer request ACKb generated based on the above.

  At time T1, a transfer request REQm1 is generated from the master unit 1-1 to the master interface 2-1. At the same time, the address ADDm1, the command CMDm1, and the like are passed to the master interface 2-1.

  The master interface 2-1 requests the arbitration circuit 7 for the right to use the bus. When the right to use the bus is granted and the CW bus 3 becomes unused, the master interface 2-1 issues a transfer request REQb on the CW bus 3. At the same time, the multiplexed address / write data AD / WDb and command CMDb are output to the CW bus 3. The retry counter 16 of the master interface 2-1 is reset to zero.

  When the address decoder 21 in the slave interface 4 decodes the address portion of the address / write data AD / WD and detects that it is a slave device designated by the address, the slave interface 4 receives the CW bus 3. Then, transfer request REQb, address / write data AD / WDb, and command CMDb are fetched.

  The response condition determination circuit 24 of the slave interface 4 receives or rejects the transfer request REQb from the master unit 1-1 according to the received command CMDb and the state of the slave unit 5 held by the slave state holding circuit 23. Determine. Since it is determined in FIG. 4 that processing is possible, an acknowledgment response ACKb is output on the CW bus 3 and a transfer request REQb is transmitted to the slave unit 5.

  When the master interface 2-1 receives the confirmation response ACKb, the master interface 2-1 sends a command acknowledge CACKm1 (see FIG. 3) to the master unit 1-1. At the same time, data phase transfer is started. In the data phase, the master interface 2-1 requests write data from the master unit 1-1 if it is a write and outputs the received data to the CW bus 3, but in FIG. Wait for a predetermined time until it is released and read data is prepared.

  On the other hand, assume that a transfer request REQm2 is sent from the master unit 1-2 to the master interface 2-2 at time T2. At the same time, the address ADm2, the command CMDm2, etc. are passed to the master interface 2-2.

  The master interface 2-2 requests the arbitration circuit 7 for the right to use the CW bus 3, waits for the CW bus 3 to be released because it is in use, and if the right to use the bus is granted, A transfer request REQb is issued. The retry counter 16 of the master interface 2-2 is reset to zero.

  The address decoder 21 in the slave interface 4 decodes the address portion of the address / write data AD / WD, and if it detects that it is a slave device designated by the address, the slave interface 4 uses the CW bus 3. Then, the transfer request REQb, address / write data AD / WDb, and command CMDb from the master unit 1-2 are fetched.

  The response condition determination circuit 24 of the slave interface 4 receives or rejects the transfer request REQb from the master unit 1-1 according to the received command CMDb and the state of the slave unit 5 held by the slave state holding circuit 23. Determine. Since the slave unit 5 is busy in processing the transfer request from the master unit 1-2, the response condition determination circuit 24 in the slave interface 4 determines to reject the transfer request REQb from the master unit 1-2, and A response NACKb is returned via the CW bus 3. Further, negative response supplementary information NAINFb is output from the negative response supplementary information generation circuit 43 to the CW bus 3. The first negative acknowledgment accompanying information NAINFb includes negative response cause information NAI, a retry setting value SRI, and a random value RN (referred to as a first random number value RN1).

  When the master interface 2-2 receives the negative response NACKb and the negative response incidental information NAINFb, the master interface 2-2 counts up the retry number counter 16 and determines whether or not it is larger than the allowable retry number PRC stored in the retry number register 15. . Since the count value of the retry counter is 1, the overflow signal maintains an inactive level.

  In the master interface 2-2, the retry information extraction circuit 31 extracts the retry setting value SRI and the random value RN (first random number value RN1) from the first negative acknowledgment incidental information NAINFb. The retry interval value RIN (first retry interval value RIN1 = SRI + RN1) is calculated and stored in the retry interval value register 12. The bus use right is released. The count value of the retry interval counter 13 is once reset to 0 by a negative response NACKb and then incremented for each clock pulse.

  On the other hand, read data RDm1 corresponding to the transfer request of the master unit 1-1 is transferred from the slave unit 5 to the master unit 1-1 via the RD bus 6 at time T3, and the read process is completed. Immediately after, the master unit 1-1 transmits the next transfer request REQm1, so that the transfer request is accepted and the slave unit 5 is again busy.

  In the master interface 2-2, when the count value of the retry interval counter 13 becomes equal to the first retry interval value RIN1 stored in the retry interval value register 12, the comparator 14 determines that the first retry interval time Tri1 has elapsed. The retry time notification signal RT is sent to the retry request circuit 18 and the retry activation request signal PRQ is output, and the master protocol control circuit 11 retransmits the transfer request REQb to the slave interface 4.

  However, the transfer request REQb retransmitted from the master interface 2-2 is rejected because the slave unit 5 is busy, and a negative response NACKb and second negative response supplementary information NAINFb are transmitted. The second negative acknowledgment accompanying information NAINFb includes negative response cause information NAI, a retry setting value SRI, and a random value RN (referred to as a second random value RN2). The master interface 2-2 stores the second retry interval value RIN2 = SRI + RN2 in the retry interval value register 12, receives the negative acknowledgment NACKb, and starts counting the second retry interval time Tri2.

  When the first random number value RN1 and the second random number value RN2 are different from each other, the second retry interval time Tri2 is different from the second retry interval time Tri2. Even if the first retry interval time Tr1 coincides with the transmission cycle of the transfer request from the master unit 1-1, the second retry interval time Tr2 is different from the first retry interval time Tri1 (in a pseudo manner). Since it is determined independently, there is a high possibility that it is different from the first retry interval time Tr1. Further, since the retry interval time after the third time is determined independently of any retry interval time before that, the retry interval time of the master interface 2-2 and the transfer request from the master unit 1-1 are also determined. It can be easily understood that the state in which the transmission period is consistent cannot be continued for a long time. Therefore, in the present embodiment, it is possible to prevent the occurrence of live lock and to eliminate this even when the live lock state is entered.

  FIG. 4 shows an example in which the retry interval time has occurred as Tri1 <Tri2 <Tri3, but the slave interface at time T4 in response to the transfer request REQb from the master interface 2-2 after the third retry interval time Tri3. 4 is returned as a confirmation response ACKb, and the read data RDm2 corresponding to the read transfer request from the master unit 1-2 is received by the master unit 1-2 at time T5.

  As described above, in this embodiment, the occurrence of live lock can be prevented, and this can be solved even when the live lock state occurs. Further, since the retry setting value SRI is sent from the slave device that requested the transfer and is set to a value uniquely set in the slave device, when various slave devices having greatly different transfer preparation times are connected to the bus. In addition, the retry interval time can be set to an appropriate range for each slave device.

  For example, if the retry setting value is 8 bits and the generated random number value is 4 bits, the pseudo random number generator can be composed of a 4-bit flip-flop and an exclusive OR gate, and the adder has an 8-bit retry setting. Since the value and a 4-bit random value can be added, the amount of hardware added to configure the present embodiment is small. In particular, when many types of slave devices are connected to the bus, the amount of additional hardware can be significantly reduced as compared with a bus system based on the technique described in Japanese Patent Laid-Open No. 9-114750.

  Further, as in the case of avoiding live lock using the technique described in Japanese Patent Laid-Open No. 2000-250850, a bus is occupied by a specific master device for a long time, and other master devices cannot use the bus. There are no side effects.

In FIG. 1, the retry interval counter 33 is connected to the retry interval value register 12,
The retry interval counter 13 and the comparator 14 are configured. A decrement type retry interval that presets a retry interval value from the adder 32 and decrements every clock pulse when a negative response NACKb is received instead of the retry interval counter 13. A counter may be used instead of the comparator 14 to detect that the count value of the decrement counter is 0 and output a retry time notification signal RT. By configuring the retry interval counting unit 33 in this way, the retry interval value register becomes unnecessary, and the circuit of the zero comparator can be simplified.

Similarly, in FIG. 1, the retry number counting unit 34 is connected to the retry number register 15,
The retry count counter 16 and the comparator 17 are configured, but when the transfer request REQm from the master unit is received instead of the retry interval counter 13, a value obtained by adding 1 to the predetermined allowable retry count PRC is preset and negated. A decrementing retry counter that decrements every time a response NACKb is received may be used, and a zero comparator that outputs an overflow signal OF by detecting that the count value of the decrementing counter has become 0 may be used instead of the comparator 17. By configuring the retry number counting unit 34 in this way, the retry number register becomes unnecessary, and the circuit of the zero comparator can be simplified.

  Next, a second embodiment of the present invention will be described. FIG. 5 is a block diagram of the master interface 2b of the bus system of the second embodiment, and FIG. 6 is a block diagram of the slave interface 4b of the bus system of the second embodiment. Although the overall configuration of the bus system is the same as that of FIG. 3 of the first embodiment, in the second embodiment, pseudorandom numbers are generated in the master interface 2b and added to the retry setting value.

  In the master interface 4b of FIG. 5, the master protocol control circuit 11 receives a transfer request and a command from the master unit 1, and controls communication between the master unit 1 and the slave device based on the protocol. The retry information extraction circuit 31a extracts the retry setting value SRI from the negative response supplementary information NAINFb transmitted from the slave interface 4b. When the retry setting value SRI is coded, the decoding is performed in the same manner as the retry information extraction circuit 31 in the first embodiment of FIG.

The pseudo-random number generator 51 receives a predetermined signal, generates a random value RN, and outputs it.
In FIG. 5, the negative response NACKb is used as the predetermined signal, but the transfer request REQb output from the master protocol control circuit 11 to the CW bus 3 may be used instead of the negative response NACKb. When the transfer request REQb is used, since the random number RN can be generated prior to the reception of the negative response NACKb, there is an advantage that the pseudo random number generator 51 is not required to operate at high speed. When the confirmation response ACKb is received, the generated random number value RN is discarded as it is. The adder 32 adds the retry setting value SRI and the random value RN to calculate a retry interval value RIN and outputs it.

  The retry interval counter 33 counts the pulses of the clock CLK after receiving the negative response NACKb, detects that the number of retry interval values RIN has been reached, and sets the retry time notification signal RT to the active level. For example, the retry interval counting unit 33 increments the count value every time a pulse of the clock CLK is input after resetting the count value when the retry interval value register 12 holding the retry interval value RIN and the negative response NACKb are received. A retry interval counter 13 that counts the number of clock pulses, and a comparator 14 that detects that the count value of the retry interval counter 13 matches the retry interval value RIN and sets the retry time notification signal RT to an active level. .

  The retry count counter 34 counts the number of times of negative acknowledgment NACKb received after receiving the transfer request REQm from the master unit 1, and detects that the count value is larger than the preset allowable retry count PRC. Then, the overflow signal OF is set to the active level. For example, the retry count counting unit 34 resets the count value in response to the retry count register 15 and the transfer request REQm from the master unit 1 when a predetermined allowable retry count PRC is stored in advance, and each time a negative response NACKb is received. And a comparator 17 that detects that the count value has become larger than the allowable retry count PRC of the retry count register 15 and sets the overflow signal OF to an active level.

  When the retry request circuit 18 detects that the retry time notification signal RT has changed to the active level when the overflow signal OF is at the inactive level, the retry request circuit 18 sends a retry activation request signal RRQ to the master protocol control circuit 11. When the retry activation request signal RRQ is received, the master protocol control circuit 11 retransmits the transfer request REQb, the command CMDb, and the address (AD / WD address part). The bus error determination circuit 19a detects that the overflow signal OF has changed to an active level, and outputs a bus error signal BERm. Further, the bus error determination circuit 19a determines the negative response cause information portion of the negative response incidental information NACKb, and the bus error signal is used even when the retry is useless because the command is not supported by the slave device. BERm is output.

  Next, FIG. 6 will be described. In the slave interface 4b, the address decoder 21 receives from the master unit 1 the master interface 2b and the address part of the address / write data AD / WD multiplexed with the transfer request REQb via the master interface 2b and the CW bus 3, and receives the slave unit 4b. If it is a transfer request to itself, an address condition detection signal ACD is output. The slave protocol control circuit 22 receives the address condition detection signal ACD and the command CMDb from the master device, and controls communication between the master device and the slave unit 5 based on the protocol.

  The slave state holding circuit 23 inputs and holds slave state information indicating whether the slave unit 5 is in a state where it can process a transfer request or is in a busy state where it cannot be processed. The response condition determination circuit 24 determines whether or not to respond to the transfer request REQb from the address condition detection signal ACD, the command CMDb, and the slave state information held in the slave state holding circuit 23, and when the response is possible, the CW bus 3 The confirmation response ACKb is output to the terminal, and when the response is impossible, the negative response NACKb is output.

  The negative response cause information generation circuit 25 refers to the slave state information held in the slave state holding circuit 23 and generates information related to the cause of returning the negative response NACKb.

  A retry setting value register 41, which is a retry setting value storage circuit, stores retry setting values SRIs that are uniquely determined for the slave unit. When the retry setting value is encoded and sent from the slave unit, storing the retry setting value SRIs in the encoded state is the same as the retry setting value register 41 in the first embodiment of FIG. .

  When the negative response NACKb is output, the negative response-accompanying information generation circuit 43a multiplexes the negative response cause information NAI and the retry setting value SRIs to generate negative response-accompanying information NAINFb and outputs it to the CW bus 3. The negative response-accompanying information generation circuit 43a is configured by using, for example, a multiplexer 61 whose output is selected and controlled by a slave protocol control device. In the transfer of the negative response supplementary information NAINF, the negative response cause information NAI and the retry set value SRIs are sequentially transferred in accordance with the order set by the slave protocol control circuit 22 by one signal line or signal line group.

  Alternatively, the negative response cause information NAI and the retry set value SRIs constituting the negative response incidental information NAINF may be separately transferred by a plurality of signal lines or signal line groups. The negative response incidental information generation circuit 43a can be omitted.

  In the second embodiment, negative response supplementary information NAINFb including the retry set value SRI is sent from the slave interface 4b to the master interface 2b, and the random value RN generated by the pseudo random number generator 51 in the master interface 2b and the negative response supplementary information are provided. The retry interval time until the transfer request REQb is retransmitted is determined based on the retry interval value RIN calculated by adding the retry setting value SRI extracted from the information NAINFb. The second embodiment is also the same as the first embodiment in that the retry setting value SRI and the random value RN are added to obtain the retry interval value SRI. The occurrence of a live lock can be prevented, and even if a live lock state occurs, this can be eliminated. Further, since the retry setting value SRI is sent from the slave device that requested the transfer and is set to a value uniquely set in the slave device, when various slave devices having greatly different transfer preparation times are connected to the bus. In addition, the retry interval time can be set to an appropriate range for each slave device.

  In the second embodiment, since the pseudo random number generator and the adder are provided only in the master interface, the bus system having a configuration in which the number of master devices connected to the bus is small and the number of slave devices is large is compared with the first embodiment. However, the increase in the amount of hardware can be suppressed.

  Next, a third embodiment of the present invention will be described. FIG. 7 is a block diagram of the master interface 2c of the bus system of the third embodiment, and FIG. 8 is a block diagram of the slave interface 4c of the bus system of the third embodiment. The overall configuration of the bus system is the same as that of FIG. 3 of the first embodiment. In the third embodiment, a random value is generated in the slave interface 4c and added to the retry setting value to calculate a retry interval value. The retry interval value is sent to the master interface 2c.

  In the master interface 4c of FIG. 7, the master protocol control circuit 11 receives a transfer request and a command from the master unit 1, and controls communication between the master unit 1 and the slave device based on the protocol. The retry information extraction circuit 71 extracts the retry interval value RIN from the negative response supplementary information NAINFb transmitted from the slave interface 4c.

  The retry interval counter 33 counts the pulses of the clock CLK after receiving the negative response NACKb, detects that the number of retry interval values RIN has been reached, and sets the retry time notification signal RT to the active level. For example, the retry interval counting unit 33 increments the count value every time a pulse of the clock CLK is input after resetting the count value when the retry interval value register 12 holding the retry interval value RIN and the negative response NACKb are received. A retry interval counter 13 that counts the number of clock pulses, and a comparator 14 that detects that the count value of the retry interval counter 13 matches the retry interval value RIN and sets the retry time notification signal RT to an active level. .

  The retry count counter 34 counts the number of times of negative acknowledgment NACKb received after receiving the transfer request REQm from the master unit 1, and detects that the count value is larger than the preset allowable retry count PRC. Then, the overflow signal OF is set to the active level. For example, the retry count counting unit 34 resets the count value in response to the retry count register 15 and the transfer request REQm from the master unit 1 when a predetermined allowable retry count PRC is stored in advance, and each time a negative response NACKb is received. And a comparator 17 that detects that the count value has become larger than the allowable retry count PRC of the retry count register 15 and sets the overflow signal OF to an active level.

  When the retry request circuit 18 detects that the retry time notification signal RT has changed to the active level when the overflow signal OF is at the inactive level, the retry request circuit 18 sends a retry activation request signal RRQ to the master protocol control circuit 11. When the retry activation request signal RRQ is received, the master protocol control circuit 11 retransmits the transfer request REQb, the command CMDb, and the address (AD / WD address part). The bus error determination circuit 19a detects that the overflow signal OF has changed to an active level, and outputs a bus error signal BERm. Further, the bus error determination circuit 19a determines the negative response cause information portion of the negative response incidental information NACKb, and the bus error signal is used even when the retry is useless because the command is not supported by the slave device. BERm is output.

  Next, FIG. 8 will be described. In the slave interface 4c, the address decoder 21 receives from the master unit 1 via the master interface 2c and the CW bus 3 the address / write data AD / WD multiplexed with the transfer request REQb, and receives the slave unit 4c. If it is a transfer request to itself, an address condition detection signal ACD is output. The slave protocol control circuit 22 receives the address condition detection signal ACD and the command CMDb from the master device, and controls communication between the master device and the slave unit 5 based on the protocol.

  The slave state holding circuit 23 inputs and holds slave state information indicating whether the slave unit 5 is in a state where it can process a transfer request or is in a busy state where it cannot be processed. The response condition determination circuit 24 determines whether or not to respond to the transfer request REQb from the address condition detection signal ACD, the command CMDb, and the slave state information held in the slave state holding circuit 23, and when the response is possible, the CW bus 3 The confirmation response ACKb is output to the terminal, and when the response is impossible, the negative response NACKb is output.

  The negative response cause information generation circuit 25 refers to the slave state information held in the slave state holding circuit 23 and generates information related to the cause of returning the negative response NACKb.

  A retry setting value register 41, which is a retry setting value storage circuit, stores retry setting values SRIs that are uniquely determined for the slave unit. In the third embodiment, the retry setting value SRIs is an actual numerical value, and the coded value is not used.

  The pseudo random number generator 42 is activated by a predetermined signal to generate a random value RNs. In FIG. 8, the negative response NACKb is used as the predetermined signal, but the address condition detection signal ACD that is the output of the address decoder 21 may be used instead of the negative response NACKb. When the address condition detection signal ACD is used, since the random number value RNs can be generated prior to the transmission of the negative response NACKb from the response condition determination circuit 24, the pseudo random number generator 42 operates at high speed. There is an advantage that it is not required. The adder 81 adds the retry setting value SRIs and the random value RNs to generate a retry interval value RINs.

  When the negative response NACKb is output, the negative response-accompanying information generation circuit 82 multiplexes the negative response cause information NAI and the retry interval value RINs to generate negative response-accompanying information NAINFb and outputs it to the CW bus 3. The negative response-accompanying information generation circuit 82 is configured using, for example, a multiplexer 83 whose output is selected and controlled by a slave protocol control device. In the transfer of the negative response supplementary information NAINF, the negative response cause information NAI and the retry interval value RINs are sequentially transferred according to the order set by the slave protocol control circuit 22 by a single signal line or signal line group.

  Alternatively, the negative response cause information NAI and the retry interval value RINs constituting the negative response incidental information NAINF may be separately transferred by a plurality of signal lines or signal line groups. The negative response incidental information generation circuit 82 can be omitted.

  In the third embodiment, the retry interval value RIN is calculated by adding the random value RN and the retry setting value SRI in the slave interface 4c, and is sent to the master interface 2c, and is transferred to the transfer request REQb based on the retry interval value RIN. The retry interval time until retransmission is determined. The third embodiment is the same as the first embodiment in that the retry setting value SRI and the random number value RN are added to obtain the retry interval value SRI. Therefore, the effect is the same as that of the first embodiment. -It is possible to prevent the occurrence of lock, and even if it falls into a live lock state, it can be eliminated. In addition, since the retry setting value SRI uses a value uniquely set in the slave device, even when various slave devices having greatly different preparation times for transfer are connected to the bus, the retry interval time is set for each slave device. An appropriate range can be set for the device.

  In the third embodiment, since the pseudo random number generator and the adder are provided only in the slave interface, the bus system having a configuration in which the number of slave devices connected to the bus is small and the number of master devices is large than that in the first embodiment. However, the increase in the amount of hardware can be suppressed.

  In FIG. 5 and FIG. 7, the retry interval counter 33 is constituted by the retry interval value register 12, the retry interval counter 13, and the comparator 14. However, as in the case of FIG. When the negative response NACKb is received instead, the retry interval value is preset from the adder 32 and decremented every clock pulse, and the count value of the decrement counter becomes 0 instead of the comparator 14 And a zero comparator that outputs a retry time notification signal RT. By configuring the retry interval counting unit 33 in this way, the retry interval value register becomes unnecessary, and the circuit of the zero comparator can be simplified.

  Similarly, in FIG. 5 and FIG. 7, the retry number counting unit 34 is configured by the retry number register 15, the retry number counter 16 and the comparator 17, but in the same manner as in FIG. Instead, when a transfer request REQm from the master unit is received, a value obtained by adding 1 to a predetermined allowable retry count PRC is preset, and a decrement type retry count counter is decremented each time a negative response NACKb is received. Alternatively, it may be a zero comparator that detects that the count value of the decrement counter is 0 and outputs the overflow signal OF. By configuring the retry number counting unit 34 in this way, the retry number register becomes unnecessary, and the circuit of the zero comparator can be simplified.

  FIG. 9 is a diagram showing an example of a semiconductor integrated circuit equipped with the bus system of the present invention. The semiconductor integrated circuit 101 includes the bus system 100 of the present invention therein. In the bus system 100, a bus master 1-1, which is a CPU, is connected to a CW bus 3 via a master interface 2-1, and a DMA (Direct Memory Access). ) Is connected to the CW bus 3 via the master interface 2-2, and the slave unit 5-1 is connected to the CW bus 3 via the slave interface 4-1, A slave unit 5-2 that is a communication I / O is connected to the CW bus 3 via a slave interface 4-2. 7 is an arbitration circuit, and 6 is an RD bus. By providing the bus system 100, in the semiconductor integrated circuit 101, the occurrence of live lock can be prevented in advance, and even if a live lock state occurs, this can be eliminated.

  FIG. 10 is a diagram showing an example of an information processing apparatus having the bus system of the present invention. The information processing apparatus 110 includes a bus system 100 a according to the present invention. The bus system 100 a includes a microcomputer chip 111 including a master interface 2-1 connected to the CW bus 3 and a master interface 2 connected to the CW bus 3. -2 including a DMA chip 112, a memory chip 113 including a slave interface 4-1 connected to the CW bus 3, and a communication I / O chip including a slave interface 4-2 connected to the CW bus 3. Configured. As in FIG. 9, 7 is an arbitration circuit, and 6 is an RD bus. By providing the bus system 100a, the information processing apparatus 110 can prevent the occurrence of a live lock and can eliminate the occurrence of a live lock state.

  FIG. 11 is a diagram showing an example of an information processing apparatus having a semiconductor integrated circuit on which the bus system of the present invention is mounted. The information processing apparatus 120 includes a semiconductor integrated circuit 101a on which the bus system 100 of the present invention is mounted, an external bus 122, and an external memory 123. The bus system 100 is connected to an external bus 122 via a bus bridge 121, and a CPU (see FIG. 9) in the bus system 100 is connected to the CW bus 3 and the RD bus 6, the bus bridge 121, and the external bus 122 in the bus system. The external memory 123 can be accessed via Also in this information processing apparatus 120, since the semiconductor integrated circuit 101a includes the bus system 100a, the occurrence of a live lock can be prevented in advance, and even if a live lock state occurs, this can be eliminated. can do.

It is a block diagram of the master interface of 1st Embodiment of this invention. It is a block diagram of the slave interface of 1st Embodiment of this invention. It is a figure which shows an example of the bus system of this invention. It is an operation | movement sequence diagram of 1st Embodiment. It is a block diagram of the master interface of 2nd Embodiment of this invention. It is a block diagram of the slave interface of 2nd Embodiment of this invention. It is a block diagram of the master interface of 3rd Embodiment of this invention. It is a block diagram of the slave interface of 3rd Embodiment of this invention. It is a figure which shows an example of the semiconductor integrated circuit carrying this invention. It is a figure which shows an example of the information processing apparatus which has this invention. It is a figure which shows an example of the information processing apparatus which has a semiconductor integrated circuit carrying this invention. It is a figure which shows an example of the conventional bus system. It is a block diagram of the master interface in the conventional bus system. (A) is an operation | movement sequence diagram of the conventional bus system, (b) is an operation | movement timing diagram. It is an operation | movement sequence diagram which shows generation | occurrence | production of a live lock.

Explanation of symbols

1 Master unit 2, 2a, 2b, 2c Master interface 3 CW bus 4, 4a, 4b, 4c Slave interface 5 Slave unit 6 RD bus 7 Arbitration circuit 11 Master protocol control circuit 18 Retry request circuit 19, 19a Bus error determination circuit 21 Address decoder 22 Slave protocol control circuit 23 Slave state holding circuit 24 Response condition determination circuit 25 Negative response cause information generation circuit 31, 31a, 71 Retry information extraction circuit 32, 81 Adder 33 Retry interval counter 34 Retry count counter 41 Retry Set value register 42, 51 Pseudo random number generator 43, 43a, 82 Negative response supplementary information generation circuit 100, 100a Bus system 101, 101a Semiconductor integrated circuit 110, 120 Information processing device 111 Microphone Computer chips 112 DMA chip 113 memory chips 114 communication processing chip 121 bus bridge 122 external bus 123 external memory REQm, REQb, REQs transfer request ACKb acknowledgment NACKb negative acknowledgment NAINFb negative acknowledgment supplementary information

Claims (9)

A master unit, which is provided between a slave unit and a bus and includes a retry setting value storage circuit that stores a retry setting value that is uniquely determined by the slave unit, and a pseudo-random number generator that generates pseudo-random numbers. A negative response is transmitted when a response to a transfer request from is rejected, and a negative response supplementary information including the retry setting value and a random value generated by the pseudo random number generator is transmitted to the master unit via the bus. Slave interface to
An adder that is provided between the master unit and the bus and adds the retry setting value extracted from the negative response supplementary information and the random number value, and a retry interval value storage that stores the addition result as a retry interval value A master interface for determining a time until a transfer request is retransmitted based on the retry interval value;
A bus system comprising:   2. The bus system according to claim 1, wherein the random number value is updated by a pseudo random number generator every time a negative response is generated in the slave interface. Provided between the slave unit and the bus and provided with a retry setting value storage circuit for storing a retry setting value uniquely determined for the slave unit, and a negative response when refusing a response to a transfer request from the master unit And a slave interface for transmitting negative acknowledgment incidental information including the retry setting value to the master unit via the bus, and
A pseudo-random number generator that is provided between the master unit and the bus and generates a pseudo-random number; and an adder that adds the generated random number value and the retry setting value extracted from the negative response supplementary information; A master interface that determines a time until a transfer request is retransmitted based on the retry interval value, and a retry interval value storage circuit that stores the addition result as a retry interval value;
A bus system comprising: 4. The bus system according to claim 3 , wherein the random number value is updated by a pseudo random number generator every time a negative response is received in the master interface. 4. The bus system according to claim 3 , wherein the random number value is updated by a pseudo random number generator every time a transfer request is output from a master interface to a slave unit. Provided between the slave unit and the bus,
An address decoder that receives a transfer request and an address from the master unit via the bus and outputs an address condition detection signal if the transfer request is to the slave unit;
Determine whether to respond to the transfer request from the master unit based on the address condition detection signal, command from the master unit and the operating state of the slave unit. A response condition determination circuit that outputs a negative response to the bus,
A retry setting value storage circuit for storing a retry setting value uniquely determined for the slave unit;
A slave interface comprising a negative response incidental information generation circuit for outputting negative acknowledgment incidental information including the retry setting value to the bus following the negative response output;
Provided between the bus and the master unit,
A retry information extraction circuit that inputs the negative response supplementary information from the bus, extracts the retry setting value, and outputs the retry setting value;
A pseudo random number generator that is activated by a predetermined signal to generate a pseudo random number;
An adder for calculating a retry interval value by adding the retry setting value and the random value generated by the pseudo-random number generator;
A retry interval counter that starts counting clock pulses by receiving the negative response, detects that the count value is equal to the retry interval value, and outputs a retry time notification signal;
A retry count counter that starts counting the number of times the negative response is received upon reception of a transfer request from the master unit, detects that the count value is greater than a preset allowable retry count, and outputs an overflow signal;
A retry request circuit that detects that the retry time notification signal has become an active level when the overflow signal is in an inactive level, and a retry request circuit that activates retransmission of a transfer request; and
A bus system comprising: The retry setting value is a coded retry setting value,
7. The bus system according to claim 6, wherein the retry information extraction circuit has a decoding function of the coded retry setting value. A predetermined signal for activating the pseudo-random number generator is
8. The bus system according to claim 6, wherein the master interface is a negative response received by the master interface. A predetermined signal for activating the pseudo-random number generator is
8. The bus system according to claim 6, wherein the master interface is a transfer request to a slave unit output to the bus.

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