JP6339331B2 - Information processing apparatus and interface control method for controlling interface - Google Patents

Description

  The present invention relates to a technique for controlling an interface, and more particularly to a technique for connecting apparatuses via an asynchronous interface.

  The demand for improving the memory transfer performance in computers and servers is increasing year by year. Therefore, various related techniques are shown in order to satisfy the memory transfer performance.

  For example, Non-Patent Document 1 shows a standard of FB-DIMM (Fully Buffered Dual Inline Memory Module) for connecting a memory via a high-speed signal line. The FB-DIMM interface is an interface that connects a processor-side memory controller and its FB-DIMM with a point-to-point serial interface (asynchronous interface) similar to PCI (Peripheral Components Interconnect bus) Express. . On the FB-DIMM, a chip called AMB (Advanced Memory Buffer) for temporarily storing all of the commands, addresses, and data exchanged with the memory chip is mounted, and all signals of the FB-DIMM interface are here. Via. The AMB is not a mere buffer but a memory controller on the memory chip side, and performs protocol conversion from the FB-DIMM interface (interface with the memory controller on the processor side).

  For example, Patent Document 1 discloses an example of a memory controller in a storage system. The memory controller of Patent Document 1 connects the memory module formed of the above-described FB-DIMM and the memory controller with a duplex serial interface (FB-DIMM interface).

JP 2006-065697 A

Download from FBDIMM ARCHITECTURE and PROTOCOL, JESD206, Jan 2007, URL "http://www.jedec.org/standards-documents/results/jESD206"

  However, the technique described in the above-mentioned prior art document has a problem that the versatility of the asynchronous interface is insufficient when various devices to be accessed are connected via the asynchronous interface.

  The reason is that the FB-DIMM interface described in the above-mentioned prior art document is an interface specialized for FB-DIMM that accesses a memory chip via AMD as an accessed device.

  Specifically, the memory access request defined by the FB-DIMM interface is different from, for example, a general-purpose DRAM (Dynamic Random Access Memory) interface, and has a format for sending a write command and write data at the same timing. Because.

  An object of the present invention is to provide a data transfer circuit and a data transfer method with improved versatility that can solve the above-described problems.

  The information processing apparatus of the present invention includes an access request transmission unit that is connected to each other through an asynchronous interface and operates at a first clock, and an access request reception unit that operates at a second clock. The access request transmission unit includes: Based on the input first access request, a request packet including a second access request corresponding to the accessed device is generated, and between the first clock and the second clock between the request packets. The access request data inserted with the skip code for absorbing the frequency difference is output to the asynchronous interface, the access request receiving means receives the access request data input from the asynchronous interface, and the access request data The frequency difference is absorbed using the skip code included in Outputting the second access request contained in the serial access request data to said target access device.

  The data transfer method according to the present invention is an information processing apparatus including a first interface control means connected to each other through an asynchronous interface and operating with a first clock, and a second interface control means operating with a second clock. The first interface control means generates a request packet including a second access request corresponding to the accessed device based on the input first access request, and the first interface control means generates the request packet between the request packets. Access request data into which a skip code for absorbing a frequency difference between a clock and the second clock is inserted is output to the asynchronous interface, and the second interface control means is input from the asynchronous interface The access request data is received and included in the access request data Using the serial skip code, the absorbing frequency difference, and outputs the second access request contained in the access request data to said target access device.

  In the present invention, when the processor and the accessed device are directly connected, the processor and the accessed device are connected via the asynchronous interface without changing the respective interface portions on the processor side and the accessed device side. There is an effect that it becomes possible to connect.

FIG. 1 is a block diagram illustrating a configuration of the memory control device according to the first embodiment. FIG. 2 is a block diagram illustrating a configuration of an information processing system including the memory control device according to the first embodiment. FIG. 3 is a block diagram showing the configuration of the access request unit in the first embodiment. FIG. 4 is a block diagram illustrating a configuration of the access request receiving unit in the first embodiment. FIG. 5 is a diagram illustrating an example of the first access request according to the first embodiment. FIG. 6 is a diagram illustrating an example of the second access request according to the first embodiment. FIG. 7 is a diagram illustrating an example of a request packet according to the first embodiment. FIG. 8 is a diagram illustrating an example of the first access request according to the first embodiment. FIG. 9 is a diagram illustrating an example of the second access request according to the first embodiment. FIG. 10 is a diagram illustrating an example of a request packet in the first embodiment. FIG. 11 is a diagram illustrating an example of access request data according to the first embodiment. FIG. 12 is a block diagram illustrating a configuration of the memory control device according to the second embodiment. FIG. 13 is a block diagram illustrating a configuration of an information processing system including a memory control device according to the second embodiment. FIG. 14 is a block diagram illustrating a configuration of a reply transmission unit according to the second embodiment. FIG. 15 is a block diagram illustrating a configuration of a reply receiving unit according to the second embodiment. FIG. 16 is a diagram illustrating an example of read data according to the second embodiment. FIG. 17 is a diagram illustrating an example of a reply packet according to the second embodiment. FIG. 18 is a diagram illustrating an example of reply data according to the second embodiment. FIG. 19 is a diagram illustrating an example of read data according to the second embodiment. FIG. 20 is a block diagram illustrating a configuration of an interface control unit according to the third embodiment. FIG. 21 is a block diagram illustrating a configuration of an interface control unit according to the third embodiment.

  Embodiments for carrying out the present invention will be described in detail with reference to the drawings. In each embodiment described in each drawing and specification, the same reference numerals are given to the same components, and the description thereof is omitted as appropriate.

<<<< first embodiment >>>>
FIG. 1 is a block diagram showing the configuration of the memory control device 210 according to the first embodiment of the present invention.

  As shown in FIG. 1, the memory control device 210 according to the present embodiment includes an access request transmission unit 310 and an access request reception unit 520.

  FIG. 2 is a block diagram showing a configuration of an information processing system including the memory control device 210 according to the first embodiment of the present invention.

  As shown in FIG. 2, the information processing system includes an access request transmission unit 310, an access request reception unit 520, a processor unit 100, a memory unit 700, and an asynchronous interface unit 400.

  First, the overall operation of the information processing system shown in FIG. 2 will be described.

  The processor unit 100 outputs the first access request 810 to the access request transmission unit 310.

  The access request transmission unit 310 receives the first access request 810 output from the processor unit 100. Next, the access request transmission unit 310 outputs the access request data 840 to the asynchronous interface unit 400 based on the received first access request 810.

  The access request receiving unit 520 receives the access request data 840 input from the asynchronous interface unit 400. Next, the access request receiving unit 520 outputs the second access request 820 to the memory unit 700 based on the received access request data 840.

  The memory unit 700 receives the second access request 820 output from the access request receiving unit 520. Next, the memory unit 700 executes the received second access request 820.

  Asynchronous interface unit 400 is connected to processor unit 100 side (access request transmission unit 310 side) operating at clock 891 (first clock) and memory unit 700 side (access request reception) operating at clock 892 (second clock). This is an interface for transferring data to the unit 520 side without synchronizing the clock 891 and the clock 892.

  The above is the description of the overall operation of the information processing system shown in FIG.

  Next, each component of the memory control device 210 will be described.

=== Access Request Transmission Unit 310 ===
Based on the input first access request 810, the access request transmission unit 310 sequentially generates request packets including the second access request 820 corresponding to the accessed device (not shown). Next, the access request transmission unit 310 outputs access request data 840 in which a skip code is inserted between the generated request packets to the asynchronous interface unit 400.

  Here, the skip code is inserted to absorb the frequency difference between the clock 891 and the clock 892 when one request packet is processed. In other words, the skip code is inserted to absorb a frequency difference between the processor unit 100 side (access request transmission unit 310 side) and the memory unit 700 side (access request reception unit 520 side).

  For example, assume that the cycle of the clock 891 on the access request transmission unit 310 side is 6 unit hours and the cycle of the clock 892 on the access request reception unit 520 side is 9 unit hours. That is, it is assumed that the frequency of the clock 891 has a frequency difference that is 1.5 times the frequency of the clock 892. In each of the processor unit 100 and the memory unit 700, it is assumed that the number of clocks required to execute the write request is two clocks. In the processor unit 100, it is assumed that the number of clocks required to execute the skip code is 2 clocks.

  In this case, the access request transmission unit 310 includes, for example, two consecutive write requests in one request packet. Then, one skip code is inserted following the request packet. That is, on the access request transmission unit 310 side, the execution time for one skip code (6 unit times × 2 clocks) is added to the execution time of two write requests (6 unit times × 2 clocks × 2 times). The total is 36 unit hours. This 36 unit time corresponds to the execution time of two write requests on the access request receiving unit 520 side (9 unit times × 2 clocks × 2 times).

=== Access Request Receiving Unit 520 ===
The access request receiving unit 520 receives the access request data 840 input from the asynchronous interface unit 400. Next, the access request receiving unit 520 outputs the second access request 820 included in the access request data 840 to the memory unit 700 (accessed device). At that time, the access request receiving unit 520 absorbs the frequency difference between the clock 891 and the clock 892 by using the skip code included in the access request data 840. For example, the access request receiving unit 520 absorbs the frequency difference by deleting the skip code and operating as if the skip code does not exist.

  This completes the description of each component of the memory control device 210.

  Next, a specific configuration of the access request transmission unit 310 will be described. FIG. 3 is a block diagram illustrating an example of the configuration of the access request transmission unit 310.

  As illustrated in FIG. 3, the access request transmission unit 310 includes a memory busy control circuit 311, a request issuance control circuit 312, a packet generation circuit 313, and a skip code insertion circuit 314.

=== Memory Busy Control Circuit 311 ===
The memory busy control circuit 311 monitors the access status to the memory unit 700 and manages whether or not the second access request 820 is issued. Here, the access status to the memory is the output status of the issue permission 801 and the presence / absence of input of a request issue suppression instruction 803 described later. Here, the output status of the issue permission 801 is information indicating the issue status of the second access request 820.

  The memory busy control circuit 311 accepts the input of the first access request 810, and when the output status of the issue permission 801 is the output enabled status and the request generation suppression instruction 803 is not input from the packet generation circuit 313, the second It is determined that the access request 820 can be issued. Next, the memory busy control circuit 311 outputs the issue permission 801 of the second access request 820 corresponding to the first access request 810 to the request issue control circuit 312. Here, “the output status of the issue permission 801 is an output enabled status” means that the amount that the second access request 820 can include in one request packet 830 when the issue permission 801 is further output, The situation is not exceeded.

  Further, the memory busy control circuit 311 cannot issue the second access request 820 when the output status of the issue permission 801 is an output impossible status or when the request generation suppression instruction 803 is input from the packet generation circuit 313. Judge that there is. Then, the memory busy control circuit 311 stops the output of the issue permission 801. The request issue control circuit 312 stops the output of the second access request 820 corresponding to the first access request 810 when the output of the issue permission 801 is stopped.

  When a request issuance suppression instruction 803 is input from the packet generation circuit 313, the memory busy control circuit 311 further outputs a skip insertion permission 802 to the packet generation circuit 313. In other words, the memory busy control circuit 311 outputs the skip insertion permission 802 when the issuance of the second access request 820 is actually suppressed.

  The access request transmission unit 310 may output information (not shown) indicating that the memory busy control circuit 311 permits and inhibits the issuance of the second access request 820 to the processor unit 100. The processor unit 100 may execute busy management of the memory unit 700 based on information input from the access request transmission unit 310.

=== Request Issuing Control Circuit 312 ===
The request issuance control circuit 312 outputs the second access request 820 to the packet generation circuit 313 based on the issuance permission 801 notified from the memory busy control circuit 311.

=== Packet Generation Circuit 313 ===
The packet generation circuit 313 adds a start delimiter and an end delimiter to a series of second access requests 820 input from the request issuance control circuit 312 from one skip insertion permission 802 to the next skip insertion permission 802. To generate a request packet 830. Next, the packet generation circuit 313 outputs the generated request packet 830 to the skip code insertion circuit 314.

  Further, the packet generation circuit 313 monitors the timing for inserting the skip code, and when detecting the timing, sends a request issuance suppression instruction 803 to the memory busy control circuit 311. In other words, the packet generation circuit 313 of the access request transmission unit 310 suppresses including a new second access request 820 in the request packet 830 preceding the skip code based on the timing at which the skip code is inserted.

  When the skip insertion permission 802 is input from the memory busy control circuit 311, the packet generation circuit 313 outputs a skip insertion instruction 804 to the skip code insertion circuit 314.

  For example, the packet generation circuit 313 includes a counter 3131, a comparison circuit 3132, and a delimiter generation circuit 3133 as shown in FIG.

  The counter 3131 is a free-running counter, for example, and always outputs a count value. The counter 3131 counts up based on the clock 891. Further, when the skip insertion permission 802 is input, the counter 3131 resets the count value (0).

  The comparison circuit 3132 compares the count value input from the counter 3131 with a predetermined threshold value, and if they match (when the skip code insertion timing is reached), the memory busy control circuit 311 is inhibited from issuing a request. An instruction 803 is output. In other words, the request issuance suppression instruction 803 is information for instructing to temporarily suppress the issuance of the second access request 820 for skip insertion.

  The delimiter generation circuit 3133 generates a request packet 830 by adding a start delimiter and a stop delimiter to the second access request 820.

  The predetermined threshold for determining the skip code insertion interval is preferably set to the maximum value within a range in which the frequency difference between the clock 891 and the clock 892 can be absorbed. By doing so, it is possible to minimize the influence on the access performance when the processor unit 100 and the memory unit 700 are connected via the asynchronous interface unit 400.

=== Skip Code Insertion Circuit 314 ===
Based on the request packet 830 and the skip insertion instruction 804 input from the packet generation circuit 313, the skip code insertion circuit 314 converts the access request data 840 with the skip code inserted between the request packets 830 into the asynchronous interface unit 400. To the access request receiving unit 520.

  The specific configuration of the access request transmission unit 310 has been described above. The configuration of the access request transmission unit 310 is not limited to the above example. For example, the access request transmission unit 310 may be configured to execute the addition of the start delimiter and the stop delimiter and the insertion of the skip code in parallel. In other words, the delimiter generation circuit 3133 of the packet generation circuit 313 may include the skip code insertion circuit 314.

  Next, a specific configuration of the access request receiving unit 520 will be described. FIG. 4 is a block diagram illustrating an example of the configuration of the access request receiving unit 520.

  As shown in FIG. 4, the access request receiving unit 520 includes a skip code processing circuit 524 and a delimiter removal circuit 523.

=== Skip Code Processing Circuit 524 ===
The skip code processing circuit 524 includes an elastic buffer. Here, the elastic buffer is a buffer circuit that temporarily holds the access request data 840 in order to absorb the frequency difference. The skip code processing circuit 524 deletes the skip code from the access request data 840 and outputs the request packet 830 to the delimiter removal circuit 523.

=== Delimiter Removal Circuit 523 ===
The delimiter removal circuit 523 deletes the start delimiter and the stop delimiter from the request packet 830 and outputs the second access request 820 to the memory unit 700.

  The specific configuration of the access request receiving unit 520 has been described above. The configuration of the access request receiving unit 520 is not limited to the above example. For example, the access request receiving unit 520 may be configured to delete the skip code, the start delimiter, and the stop delimiter in the order of detection.

  Next, the operation of this embodiment will be described with an example of an access request.

  FIG. 5 is a diagram illustrating an example of the first access request 810 output from the processor unit 100. As illustrated in FIG. 5, for example, the processor unit 100 outputs three first access requests 810 including a write request 811, a read request 812, and a read request 813.

  The access request transmission unit 310 receives the first access request 810 output from the processor unit 100 by the memory busy control circuit 311 and the request issue control circuit 312.

  FIG. 6 is a diagram illustrating an example of the second access request 820. As shown in FIG. 6, the second access request 820 includes a write request 821, a read request 822, and a read request 823 corresponding to the write request 811, the read request 812, and the read request 813, respectively. For example, the write request 821 has a format conforming to the specification of the memory unit 700 in which the write data is delayed by the write latency. In other words, the memory unit 700 can accept an input of the second access request 820.

  Based on the first access request 810 that is permitted to be issued by the issue permission 801, the request issuance control circuit 312 sequentially sends the second access request 820 in a format that conforms to the specifications of the memory unit 700 to the packet generation circuit 313. Output.

  In other words, the request issuance control circuit 312 that outputs the “second access request 820 that can be accepted by the memory unit 700” is an interface part on the processor side when the accessed device is directly connected.

  FIG. 7 is a diagram illustrating an example of the request packet 830. As shown in FIG. 7, the request packet 830 includes a series of second access requests 820, a start delimiter at the beginning, and an end delimiter at the end.

  The packet generation circuit 313 generates a request packet 830 based on the second access request 820 input from the request issuance control circuit 312.

  The packet generation circuit 313 generates and outputs a start delimiter as an output of the request packet 830 to the skip code insertion circuit 314, outputs a second access request 820 following the start delimiter, and finally generates an end delimiter. And output. Further, the packet generation circuit 313 generates a start delimiter in the next cycle of the end delimiter, and immediately starts outputting the next request packet 830.

  FIG. 8 is a diagram illustrating another example of the first access request 810 output from the processor unit 100. As illustrated in FIG. 8, for example, the processor unit 100 outputs six first access requests 810 including a write request 811, a read request 812, a read request 813, a read request 814, a read request 815, and a write request 816.

  FIG. 9 is a diagram showing another example of the second access request 820 corresponding to the first access request 810 shown in FIG. As shown in FIG. 9, the second access request 820 includes a write request 821, a read request 822, a read request 823, and a read request 824 corresponding to the write request 811, the read request 812, the read request 813, and the read request 814, respectively. including.

  FIG. 10 is a diagram showing a request packet 830 corresponding to the second access request 820 shown in FIG.

  The request packet 830 illustrated in FIG. 10 includes the second access request 820 corresponding to the read request 815 and the write request 816 because the memory busy control circuit 311 determines that “the output status of the issue permission 801 is an output impossible status”. Absent. On the other hand, in the request packet 830 shown in FIG. 7, the memory busy control circuit 311 has determined that “the output status of the issue permission 801 is the output enabled status”, but the request generation suppression instruction 803 is input from the packet generation circuit 313. Thus, the request packet 830 has been generated.

  FIG. 11 is a diagram illustrating an example of the access request data 840. As shown in FIG. 11, the access request data 840 includes a skip code 841 inserted between the request packet 830 and the request packet 830.

  The skip code insertion circuit 314 of the access request transmission unit 310 inserts the skip code 841 between the request packets 830 input from the packet generation circuit 313 to obtain access request data 840, and the access request is transmitted via the asynchronous interface unit 400. Data 840 is output to access request receiver 520.

  The skip code processing circuit 524 of the access request receiving unit 520 receives the access request data 840 via the asynchronous interface unit 400. Next, the skip code processing circuit 524 outputs the request packet 830 shown in FIG. 7 or 10 included in the access request data 840 to the delimiter removal circuit 523.

  The delimiter removing circuit 523 removes the start delimiter and the end delimiter from the request packet 830 and outputs the second access request 820 shown in FIG. 6 or 9 to the memory unit 700.

  The first effect of the present embodiment described above is that the interface portions on the processor unit 100 side and the memory unit 700 side are changed when the processor unit 100 and the memory unit 700 (accessed device) are directly connected. The processor unit 100 and the memory unit 700 can be connected to each other via the asynchronous interface unit 400.

  This is because the following configuration is included. That is, first, the access request transmission unit 310 transmits the access request data 840 in which the skip code 841 is inserted between the request packets 830 including the second access request 820 corresponding to the accessed device. Second, the access request receiving unit 520 absorbs the frequency difference between the clock 891 and the clock 892 using the skip code 841 included in the received access request data 840 and is included in the received access request data 840. The second access request 820 is output to the memory unit 700.

  The second effect of the present embodiment described above is that it is possible to suppress an increase in cost for connection via the asynchronous interface unit 400.

  The reason is the same as the reason for the first effect. Specifically, in the FB-DIMM shown in the related art, the AMD includes a buffer that holds a plurality of write data in order to control the transmission timing of the write data to the next-stage FB-DIMM. Therefore, when the FB-DIMM interface is used, an increase in circuit scale and a corresponding increase in heat generation occur on the accessed device side. On the other hand, the buffer included in the memory control device 210 of this embodiment is at most one packet.

  The third effect of the present embodiment described above is that the influence on the access performance from the processor unit 100 to the memory unit 700 can be minimized.

  The reason is that the predetermined threshold for determining the skip code insertion interval is set to the maximum value within the range in which the frequency difference between the clock 891 and the clock 892 can be absorbed.

<<< Second Embodiment >>>
Next, a second embodiment of the present invention will be described in detail with reference to the drawings. Hereinafter, the description overlapping with the above description is omitted as long as the description of the present embodiment is not obscured.

  FIG. 12 is a block diagram showing a configuration of the memory control device 220 according to the second embodiment of the present invention.

  As shown in FIG. 12, the memory control device 220 in this embodiment includes an interface control unit 300 (first interface control means) including an access request transmission unit 310 and a reply reception unit 330, an access request reception unit 520, and a reply. And an interface control unit 500 (second interface control means) including a transmission unit 540.

  FIG. 13 is a block diagram showing a configuration of an information processing system including the memory control device 220 according to the second embodiment of the present invention.

  As shown in FIG. 13, the information processing system includes an interface control unit 300, an interface control unit 500, a processor unit 100, a memory unit 700, and an asynchronous interface unit 400.

  First, the overall operation of the information processing system shown in FIG. 13 will be described.

  The operation related to the write request of the first access request 810 is as described in the first embodiment. Of the operations related to the read request of the first access request 810, the operation until the second access request 820 is output to the memory unit 700 is the same as described in the first embodiment.

  Next, of the operations related to the read request of the first access request 810, the operation related to the read data 850 from the memory unit 700 will be described.

  The memory unit 700 outputs the read data 850 to the reply transmission unit 540 of the interface control unit 500.

  The reply transmission unit 540 receives the read data 850 output from the memory unit 700. Next, the reply transmission unit 540 outputs reply data 870 to the asynchronous interface unit 400 based on the received read data 850.

  The reply receiving unit 330 receives the reply data 870 input from the asynchronous interface unit 400. Next, the reply receiving unit 330 outputs the read data 880 to the processor unit 100 based on the received reply data 870.

  The processor unit 100 receives the read data 880 output from the reply receiving unit 330.

  The above is the description of the overall operation of the information processing system shown in FIG.

  Next, each component of the memory control device 220 will be described.

=== Memory Unit 700 ===
The memory unit 700 executes processing corresponding to the read request of the second access request 820 input from the access request receiving unit 520 of the interface control unit 500, and outputs the read data 850 to the reply transmission unit 540 of the interface control unit 500. To do.

=== Reply Transmitter 540 ===
The reply transmission unit 540 sequentially generates reply packets including a set of read data 850 corresponding to the second access request 820 of the read request included in one request packet 830. Next, the reply transmission unit 540 outputs reply data 870 in which a skip code is inserted between the generated reply packets to the asynchronous interface unit 400.

=== Reply Receiving Unit 330 ===
The reply receiving unit 330 receives the reply data 870 input from the asynchronous interface unit 400. Next, the reply receiving unit 330 outputs the read data 880 included in the reply data 870 to the processor unit 100. At that time, the access request receiving unit 520 absorbs the frequency difference between the clock 891 and the clock 892 by using the skip code included in the access request data 840.

  This completes the description of each component of the memory control device 210.

  Next, a specific configuration of the reply transmission unit 540 will be described. FIG. 14 is a block diagram illustrating an example of the configuration of the reply transmission unit 540.

  As illustrated in FIG. 14, the reply transmission unit 540 includes a packet generation circuit 543 and a skip code insertion circuit 544.

=== Packet Generation Circuit 543 ===
The packet generation circuit 543 generates a reply packet 860 by adding a start delimiter and an end delimiter to a set of read data 850 corresponding to a read request included in a certain request packet 830. At this time, the packet generation circuit 543 may add data valid to each read data 850. Next, the packet generation circuit 543 outputs the generated reply packet 860 to the skip code insertion circuit 544.

=== Skip Code Insertion Circuit 544 ===
The skip code insertion circuit 544 inserts a skip code between the reply packets 860 input from the packet generation circuit 543, and outputs it as reply data 870 to the reply receiving unit 330 via the asynchronous interface unit 400.

  The specific configuration of the reply transmission unit 540 has been described above. The configuration of the reply transmission unit 540 is not limited to the above example. For example, the reply transmission unit 540 may be configured to execute the addition of the start delimiter and the stop delimiter and the insertion of the skip code in parallel. In other words, the packet generation circuit 543 may include a skip code insertion circuit 544.

  Next, a specific configuration of the reply receiving unit 330 will be described. FIG. 15 is a block diagram illustrating an example of the configuration of the reply receiving unit 330.

  As shown in FIG. 15, the reply receiving unit 330 includes a delimiter removing circuit 333 and a skip code processing circuit 334.

=== Skip Code Processing Circuit 334 ===
Similar to the skip code processing circuit 524 shown in FIG. 4, the skip code processing circuit 334 includes an elastic buffer that is a buffer circuit that temporarily holds reply data 870 in order to absorb a frequency difference. The skip code processing circuit 524 deletes the skip code from the access request data 840 and outputs the request packet 830 to the delimiter removal circuit 523. The skip code processing circuit 334 deletes the skip code from the reply data 870 and outputs the reply packet 860 to the delimiter removal circuit 333.

=== Delimiter Removal Circuit 333 ===
The delimiter removal circuit 333 deletes the start delimiter and the stop delimiter from the reply packet 860 and outputs read data 880 to the processor unit 100.

  The specific configuration of the reply receiving unit 330 has been described above. The configuration of the reply receiving unit 330 is not limited to the above example. For example, the reply receiving unit 330 may be configured to delete the skip code, the start delimiter, and the stop delimiter in the order of detection.

  Next, the operation of this embodiment will be described with reference to an example of read data.

  FIG. 16 is a diagram illustrating an example of read data 850 output from the memory unit 700. As shown in FIG. 16, for example, the memory unit 700 outputs two pieces of read data 850, that is, read data 851 and read data 852 corresponding to the read request 812 and the read request 813 shown in FIG.

  FIG. 17 is a diagram illustrating an example of the reply packet 860. As shown in FIG. 17, the reply packet 860 includes read data 881 and read data 882, a start delimiter at the beginning, and an end delimiter at the end. Here, each of the read data 881 and the read data 882 is the read data 851 and the read data 852 to which the data valid is given.

  The packet generation circuit 543 generates reply data 870 based on the read data 850 input from the memory unit 700.

  FIG. 18 is a diagram illustrating an example of the reply data 870. As shown in FIG. 18, the reply data 870 includes a reply packet 860 and a skip code 871 inserted between the reply packets 860.

  The skip code insertion circuit 544 of the reply transmission unit 540 inserts the skip code 871 between the reply packets 860 input from the packet generation circuit 543 to obtain reply data 870, and the reply data 870 is transmitted via the asynchronous interface unit 400. The data is output to the reply receiving unit 330.

  The skip code processing circuit 334 of the reply receiving unit 330 receives the reply data 870 via the asynchronous interface unit 400. Next, the skip code processing circuit 334 outputs the reply packet 860 shown in FIG. 17 included in the reply data 870 to the delimiter removing circuit 333.

  FIG. 19 is a diagram illustrating an example of the read data 880. Each of the two read data 880 of the read data 881 and the read data 882 shown in FIG. 19 corresponds to the read data 851 and the read data 852 shown in FIG.

  The delimiter removing circuit 333 of the reply receiving unit 330 removes the start delimiter and the end delimiter from the reply packet 860, and outputs the read data 880 shown in FIG.

  In addition to the effects of the first embodiment, the effects of the present embodiment described above can be obtained in the same manner as the effects of the first embodiment when frequency difference absorption is required for read data. Is a point.

  This is because the following configuration is included. That is, first, the reply transmission unit 540 transmits the reply data 870 in which the skip code 871 is inserted between the reply packets 860 including the read data 880. Second, the reply receiving unit 330 absorbs the frequency difference between the clock 891 and the clock 892 using the skip code 871 included in the received reply data 870, and the read data included in the received reply data 870. 880 is output to the processor unit 100.

<<< Third Embodiment >>>
Next, a third embodiment of the present invention will be described in detail with reference to the drawings. Hereinafter, the description overlapping with the above description is omitted as long as the description of the present embodiment is not obscured.

  FIG. 20 is a block diagram showing the configuration of the interface control unit 303 (first interface control means) according to the third embodiment of the present invention.

  As shown in FIG. 20, the interface control unit 303 in the present embodiment is different from the interface control unit 300 in the second embodiment in place of the access request transmission unit 310 and the reply reception unit 330, and the memory control unit 350 and Asynchronous interface control unit 360 is included.

=== Memory Control Unit 350 ===
The memory control unit 350 includes a memory busy control circuit 311, a request issuance control circuit 312, a packet generation circuit 313, and a delimiter removal circuit 333. Here, the memory busy control circuit 311, the request issuance control circuit 312, and the packet generation circuit 313 included in the memory control unit 350 are the same as the memory busy control circuit 310 (detailed in FIG. 3) shown in FIG. 12. The control circuit 311, the request issuance control circuit 312, and the packet generation circuit 313 are the same. The delimiter removal circuit 333 included in the memory control unit 350 is the same as the delimiter removal circuit 333 included in the reply reception unit 330 (details are shown in FIG. 15) shown in FIG.

=== Asynchronous Interface Control Unit 360 ===
Asynchronous interface control unit 360 includes a skip code insertion circuit 314 and a skip code processing circuit 334. Here, the skip code insertion circuit 314 included in the asynchronous interface control unit 360 is the same as the skip code insertion circuit 314 included in the access request transmission unit 310 (shown in detail in FIG. 3) shown in FIG. Further, the skip code processing circuit 334 included in the asynchronous interface control unit 360 is the same as the skip code processing circuit 334 included in the reply receiving unit 330 shown in FIG. 12 (details are shown in FIG. 15).

  FIG. 21 is a block diagram showing the configuration of the interface control unit 503 (second interface control means) according to this embodiment.

  As shown in FIG. 21, the interface control unit 503 in the present embodiment is different from the interface control unit 500 in the second embodiment in place of the access request reception unit 520 and the reply transmission unit 540, and the memory control unit 550 and Asynchronous interface control unit 560 is included.

=== Memory Control Unit 550 ===
The memory control unit 550 includes a delimiter removal circuit 523 and a packet generation circuit 543. Here, the delimiter removing circuit 523 included in the memory control unit 550 is the same as the delimiter removing circuit 523 included in the access request receiving unit 520 shown in FIG. 12 (details are shown in FIG. 4). The packet generation circuit 543 included in the memory control unit 550 is the same as the packet generation circuit 543 included in the reply transmission unit 540 illustrated in FIG. 12 (details are shown in FIG. 14).

=== Asynchronous Interface Control Unit 560 ===
The asynchronous interface control unit 560 includes a skip code processing circuit 524 and a skip code insertion circuit 544. Here, the skip code processing circuit 524 included in the asynchronous interface control unit 560 is the same as the skip code processing circuit 524 included in the access request receiving unit 520 shown in FIG. 12 (details are shown in FIG. 4). The skip code insertion circuit 544 included in the asynchronous interface control unit 560 is the same as the skip code insertion circuit 544 included in the reply transmission unit 540 shown in FIG. 12 (details are shown in FIG. 14).

  As described above, the present embodiment is a form in which the constituent elements gathered corresponding to the request and data flow in the second embodiment are gathered according to the stage of processing.

  Also by the configuration of the present embodiment described above, the same effect as that of the second embodiment can be obtained.

  The memory control device according to each of the embodiments described above does not change the existing interface using the second access request 820 or the read data 880 on the processor unit 100 side and the memory unit 700 side, but via the asynchronous interface unit 400. Thus, the processor unit 100 and the memory unit 700 are connected. Each of the above-described embodiments is not limited to the interface between the processor and the memory, but can be applied to the case where these devices are connected via an asynchronous interface while maintaining the unique interfaces of various devices.

  Each component described in each of the above embodiments does not necessarily have to be individually independent. For example, each component may be realized as a module with a plurality of components. In addition, each component may be realized by a plurality of modules. Each component may be configured such that a certain component is a part of another component. Each component may be configured such that a part of a certain component overlaps a part of another component.

  Each component in each embodiment described above and a module that realizes each component may be realized by hardware as necessary. Moreover, each component and the module which implement | achieves each component may be implement | achieved by a computer and a program. Each component and a module that realizes each component may be realized by mixing hardware modules, computers, and programs.

  As mentioned above, although this invention was demonstrated with reference to each embodiment and an Example, this invention is not limited to the said embodiment and Example. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

  The present invention can be applied to a computer system and a network system in which devices connected by a specific interface are connected by an asynchronous interface.

DESCRIPTION OF SYMBOLS 100 Processor part 210 Memory control apparatus 220 Memory control apparatus 300 Interface control part 303 Interface control part 310 Access request transmission part 311 Memory busy control circuit 312 Request issue control circuit 313 Packet generation circuit 314 Skip code insertion circuit 330 Reply reception part 333 Delimiter removal Circuit 334 Skip code processing circuit 350 Memory control unit 360 Asynchronous interface control unit 400 Asynchronous interface unit 500 Interface control unit 503 Interface control unit 520 Access request reception unit 523 Delimiter removal circuit 524 Skip code processing circuit 540 Reply transmission unit 543 Packet generation circuit 544 Skip code insertion circuit 550 Memory control unit 560 Asynchronous interface control unit 700 Memory Unit 801 Issuance Permission 802 Skip Insertion Permission 803 Request Issuance Inhibition Instruction 804 Skip Insertion Instruction 810 First Access Request 811 Write Request 812 Read Request 813 Read Request 814 Read Request 815 Read Request 816 Write Request 820 Second Access Request 821 Write Request 822 Read request 823 Read request 824 Read request 830 Request packet 840 Access request data 841 Skip code 850 Read data 851 Read data 852 Read data 860 Reply packet 870 Reply data 871 Skip code 880 Read data 881 Read data 882 Read data 891 First clock 892 Second clock 3131 Counter 3132 Comparison circuit 3133 Delimiter generation circuit

Claims (5)

An access request transmitting means connected with each other by an asynchronous interface and operating with a first clock; and an access request receiving means operating with a second clock;
The access request transmission unit generates a request packet including a second access request in which the input first access request is formatted according to the specification of the accessed device, and the first clock is generated between the request packets. And the access request data in which the skip code for absorbing the frequency difference between the second clock and the second clock is inserted is output to the asynchronous interface,
The access request receiving means receives the access request data input from the asynchronous interface, absorbs the frequency difference using the skip code included in the access request data, and is included in the access request data Outputting the second access request to the accessed device ,
The access request transmitting means includes an information processing apparatus that includes two or more requests in the request packet and inserts the skip code between the request packets at a maximum interval that can absorb the frequency difference . Reply transmission means for operating on the second clock, generating a reply packet including read data output from the accessed device, and outputting reply data in which the skip code is inserted between the reply packets to the asynchronous interface; ,
It operates with the first clock, receives the reply data input from the asynchronous interface, absorbs the frequency difference based on the skip code included in the reply data, and is included in the reply data. The information processing apparatus according to claim 1, further comprising: a reply receiving unit that outputs read data. The access request transmission means is based on the timing of inserting the skip code,
The information processing apparatus according to claim 1 or 2, characterized in that to prevent the inclusion of a new second access request to the request packet preceding the skip code. In an information processing apparatus including first interface control means connected to each other by an asynchronous interface and operating with a first clock, and second interface control means operating with a second clock,
The first interface control means generates a request packet including a second access request in which the input first access request is formatted in accordance with the specification of the accessed device, and the first interface control means generates the request packet between the request packets. The access request data into which the skip code for absorbing the frequency difference between the clock and the second clock is inserted is output to the asynchronous interface,
The second interface control means receives the access request data input from the asynchronous interface, absorbs the frequency difference using the skip code included in the access request data, and receives the access request data. Output the second access request included in the access target device ,
The first interface control means includes a data transfer method in which two or more requests are included in the request packet, and the skip code is inserted between the request packets at a maximum interval capable of absorbing the frequency difference . The second interface control means further generates a reply packet including read data output from the accessed device, and outputs reply data in which the skip code is inserted between the reply packets to the asynchronous interface.
The first interface control means further receives the reply data input from the asynchronous interface, absorbs the frequency difference based on the skip code included in the reply data, and is included in the reply data. The data transfer method according to claim 4, wherein the read data is output.

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