JP2008186093A - Bus interface circuit and information processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique capable of improving use efficiency of a bus. <P>SOLUTION: An internal processing module 311 detects the head of a first period repeated at a constant frequency. The internal processing module 311 outputs, when the head of the first period visits first after receipt of a bus use permission signal, the address of data that is a reading object to the bus 100 within a second period shorter than the first period. The module 311 inputs, after a lapse of a third period calculated by multiplying the period by a predetermined positive integer, data corresponding to the address which is output by a slave device to the bus 100 within a fourth period after reduction of the second period from the period successively to the third period. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a bus interface circuit and an information processing apparatus.

  In an electronic device in which a plurality of devices are connected to the bus, when a device (master device) reads data from another device (slave device) whose operation speed is slower than the operation speed of the bus, the data from the slave device There may be a delay in preparation. In such a case, a period in which the bus is not used occurs, and the use efficiency of the bus decreases. FIG. 13 is an example of a timing chart of data transmission. An invalid cycle in which a signal is not transmitted occurs after an address of data to be read is transmitted until data corresponding to the address is transmitted. It shows how it is.

As a technique for improving the use efficiency of the bus, for example, in Patent Document 1, a processor bus connected to a processor, a memory bus connected to a memory, and a system bus connected to an input / output device are connected. An information processing apparatus including a connection device is disclosed. According to this technology, when any two of the processor, the memory, and the input / output device are operating in conjunction with each other, the remaining one can operate independently. There is no disclosure of a technique for improving the use efficiency.
Japanese Patent No. 2910303

  An object of the present invention is to provide a technique capable of improving the use efficiency of a bus.

  In order to solve the above-described problem, the invention according to claim 1 is directed to a bus arbiter that allocates the bus usage period to each device so that the bus usage periods of a plurality of devices connected to the bus do not overlap. A request signal transmitting means for transmitting a bus use request signal indicating a request for use of the bus; a permission signal receiving means for receiving a bus use permission signal indicating permission for use of the bus transmitted by the bus arbiter; and a constant cycle When the head is first visited after the permission signal receiving means receives the bus use permission signal, the second period shorter than the first period is detected. Within a period, there is an address output means for outputting an address of data to be read to the bus, and a third period obtained by multiplying the period by a predetermined positive integer following the second period. If there is, the slave device is data corresponding to an address output by the address output means within a fourth period obtained by subtracting the second period from the period following the third period. And a data input means for inputting data output to the bus. A bus interface circuit is provided.

  According to a second aspect of the present invention, in the bus interface circuit according to the first aspect, the data input means sets a period for the slave device to prepare the data following the third period. When it is requested to extend the period of 3, the data is input within the fourth period after waiting for the third period.

  According to a third aspect of the present invention, in the bus interface circuit according to the second aspect, the slave device requests that the period for preparing the data be extended by the third period, and the address And a stop instructing unit for instructing the slave device to stop processing when an elapsed time after the output unit outputs the address reaches a predetermined value.

  According to a fourth aspect of the present invention, in the bus interface circuit according to any one of the first to third aspects, the address output unit is configured such that the address output unit first receives the bus use permission signal after the permission signal reception unit receives the bus use permission signal. When the head arrives, the address of the data write destination is output to the bus within the second period, and the address output means outputs the address of the data write destination following the second period. And a data output means for outputting data corresponding to the address to the bus within the fourth period following the third period when the third period has elapsed. .

  The invention according to claim 5 detects the head of the first period repeated at a constant cycle, and inputs the address output by the master device to the bus within the second period shorter than the first period. And when the third period obtained by multiplying the period by a predetermined positive integer has passed after the second period in which the address is input by the address input means. And a data output means for outputting data corresponding to the address to the bus within a fourth period obtained by subtracting the second period from the period. I will provide a.

  According to a sixth aspect of the present invention, in the bus interface circuit according to the fifth aspect, when the data output means does not complete preparation for outputting data corresponding to the address within the third period. The master device is requested to extend the period for preparing the data by the third period, and the preparation is further executed only for the third period.

  According to a seventh aspect of the present invention, in the bus interface circuit according to the sixth aspect, the data output means stops the processing for the preparation when the master device instructs to stop the processing. Features.

  According to an eighth aspect of the present invention, in the bus interface circuit according to any one of the fifth to seventh aspects, the determination unit determines whether or not the address input by the address input unit is a data write destination address. And a data input means for inputting the data output to the bus by the master device within the fourth period when the address is a data write destination address as a result of the determination by the determination means. Features.

  According to a ninth aspect of the present invention, in the bus interface circuit according to any one of the first to fourth aspects, the address output means outputs an address during a period from the beginning to the middle of the second period. It is characterized by.

  According to a tenth aspect of the present invention, in the bus interface circuit according to any one of the fourth to eighth aspects, the data output means outputs data during a period from the beginning to the middle of the third period. It is characterized by.

  The invention according to claim 11 is a bus for transmitting data, a bus arbiter for allocating the use period of the bus to each device so that the use periods of the bus by a plurality of devices connected to the bus do not overlap. An information processing apparatus comprising the bus interface circuit according to claim 1 and the bus interface circuit according to claim 5 is provided.

  According to the present invention, the bus use efficiency can be improved.

Embodiments of the present invention will be described below with reference to the drawings. The present embodiment is an example in which the present invention is applied to an information processing apparatus.
FIG. 1 is a diagram illustrating the overall configuration of the present embodiment.
The bus 100 is a transmission path for exchanging data between the devices constituting the information processing apparatus 1. The bus 100 includes an address bus for transmitting addresses, a data bus for transmitting data to be read / written, and a control bus for transmitting various control signals (not shown). Each of the address bus, the data bus, and the control bus includes a plurality of signal lines, and can simultaneously transmit data having the number of bits corresponding to the number of signal lines.

The bus 100 includes a central processing unit (CPU) 301, a read only memory (ROM) 302, a random access memory (RAM) 303, a hard disk drive (HDD) 304, an external interface (I / F) 305, an I / O ( Input / Output) device 306, bus arbiter 200, and oscillator 400 are connected.
The HDD 304 stores a program such as an OS (Operating System). The ROM 302 stores an IPL (Initial Program Loader). When the information processing apparatus 1 is powered on, the CPU 301 executes IPL, the OS is read from the HDD 304 onto the RAM 303, and the CPU 301 executes the OS. Thus, each part of the information processing apparatus 1 is controlled. The HDD 304 stores a program describing a data processing procedure, and the CPU 301 executes the program to perform data processing.

  The external I / F 305 is connected to the network NW and mediates exchange of data between the information processing apparatus 1 and the network NW. The I / O device 306 includes a keyboard, a mouse, a display device, and the like, and a user can input an instruction to the information processing device 1 by operating the I / O device 306.

In the following description, a device that requests data reading or writing to another device is called a master device, and a device that reads or writes data in response to a request from the master device is called a slave device. For example, when the CPU 301 requests the HDD 304 to read or write data, the CPU 301 is called a master device and the HDD 304 is called a slave device. Any of the CPU 301, the ROM 302, the RAM 303, the HDD 304, the external I / F 305, and the I / O device 306 can be a master device or a slave device.
In the following description, when it is not necessary to distinguish the CPU 301, ROM 302, RAM 303, HDD 304, external I / F 305, and I / O device 306, these are simply referred to as the device 300.

  The bus arbiter 200 has a function of assigning a usage period of the bus 100 to each master device connected to the bus 100. Specifically, when the master device reads data from the slave device or writes data to the slave device, the master device sends a bus use request signal (BR signal) indicating a request for using the bus 100 via the control bus. To the bus arbiter 200. Then, the bus arbiter 200 performs arbitration by a known method so that the use periods of the bus 100 by a plurality of master devices do not overlap, and assigns the use period of the bus 100 to each master device. Then, the bus arbiter 200 transmits a bus use permission signal (BG signal) indicating permission of use of the bus 100 to the master device to be permitted via the control bus. The master device can output an address and data to the bus 100 when receiving the BG signal. FIG. 6 is a timing chart showing how BR signals and BG signals are transmitted.

The oscillator 400 supplies a bus clock signal BCLK that determines an operating frequency of data transmission on the bus 100 to each device 300 and the bus arbiter 200 via the bus 100.
Note that data transmission in each device 300 is performed according to an internal clock signal CLK having a frequency higher than that of the bus clock signal BCLK.

FIG. 2 is a diagram illustrating the bus interface circuit 310. All devices 300 are provided with a bus interface circuit 310, and each device 300 is connected to the bus 100 via the bus interface circuit 310.
The internal processing module 311 transmits a bus use request signal (BR signal) indicating a request for using the bus 100 to the bus arbiter 200. The internal processing module 311 inputs data transmitted from the slave device from the bus 100 via an input stage FIFO (First-In First-Out) 330, and performs predetermined processing using the input data. The internal processing module 311 outputs data to be transmitted to the slave device to the bus 100 via the output stage FIFO 320. The internal processing module 311 includes a counter that counts the bus clock signal BCLK.
The effective address generator 312 generates an address in the slave device of data to be read or written.

The output stage FIFO 320 stores the address, data, and the like output from the internal processing module 311. When the internal processing module 311 instructs the output, the output stage FIFO 320 stores the address, data, etc. with the oldest storage time to the bus 100 via the buffer 321. Output.
The input stage FIFO 330 takes in data from the bus 100 via the buffer 331 and transfers it to the internal processing module 311 when the internal processing module 311 instructs to input data.
The address decoder 340 inputs an address from the bus 100, determines whether or not the input address corresponds to the address of its own station, and if it corresponds to the address of its own station, notifies the internal processing module 311 to that effect. To do.

  FIG. 3 is a diagram illustrating a relationship between a period for transmitting an address on the bus 100 and a period for transmitting data corresponding thereto. FIG. 4 is a timing chart of data transmission on the bus 100. In the present embodiment, a period of 7 clocks of the bus clock signal BCLK is called a slot (first period), and the head of the slot comes at a cycle of 7 clocks. Also, a period of 2 clocks from the beginning of each slot is called a second period, a period of 2 slots (= 14 clocks) following the second period is called a third period, The subsequent period of 5 clocks is called a fourth period. That is, a period corresponding to three consecutive slots is composed of a second period, a third period, and a fourth period in order.

  In the present embodiment, as shown in FIG. 3, when an address of certain data is transmitted from the master device to the slave device, data corresponding to the address is not transmitted in the slot in which the address is transmitted, but from the slot. This is done in the slot behind by a predetermined offset value. In the present embodiment, the offset value n = 2. That is, in FIG. 3, transmission of data a corresponding to address a is performed in a slot that is two slots behind the slot in which address a was transmitted.

  Furthermore, in this embodiment, a period in which neither an address nor data is transmitted is provided in order to prevent signal collision. Specifically, it is as follows. When one device 300 outputs a signal to the bus 100 immediately after another device 300 outputs a signal to the bus 100, the X mark in FIG. 5 is used unless the drive element that drives the signal line of the bus 100 is a wired OR. As shown in FIG. 2, there are cases where two signals collide on the bus 100 and a failure occurs in transmission. In order to prevent such a situation, a period in which neither an address nor data is transmitted may be provided between an address transmission period and a data transmission period, as indicated by a circle in FIG. In the present embodiment, as shown in FIG. 4, the first one clock period of the second period is an address cycle for transmitting an address, and the subsequent one clock period is a turn-off cycle. The turn-off cycle is a period in which signal transmission is not performed in order to prevent signals from colliding on the bus. Further, the first four clock periods of the fourth period are set as data cycles for transmitting data, and the subsequent one clock period is set as a turn-off cycle.

The number of delay clocks from the end of address transmission to the start of data transmission corresponding to that address is obtained by the following equation.
(Number of delay clocks d from address transmission to data transmission)
= (Slot size m) x (offset value n) + (turn-off cycle) Equation (1)
In this embodiment, since m = 7 and n = 2, d = 15. That is, after 15 clocks have elapsed from the end of address transmission, data transmission corresponding to the address is started.

  FIG. 4 shows a state of data transmission when each of the CPU 301, ROM 302, RAM 303, HDD 304, external I / F 305, and I / O device 306 is a master device. Here, since each device 300 transmits an address according to the arbitration by the bus arbiter 200, the address is not transmitted from two or more devices 300 in the same slot. Since transmission of data corresponding to each address is always started after being delayed by a predetermined number of delay clocks from the corresponding address, data is not transmitted from the two devices 300 in the same slot. Therefore, when 301 to 306 in FIG. 4 are overlapped, as shown by ALL, address transmission and data transmission are repeatedly performed on the bus 100 at a constant cycle. That is, in this embodiment, although a delay of the delay clock number d occurs from the transmission of the address to the transmission of the data corresponding to the address, the throughput of the bus 100, that is, the effective value of the data transmission amount per unit time is Therefore, it is kept high compared to the case without this configuration.

Next, the operation of the bus interface circuit 310 will be described.
Here, the information processing apparatus 1 is powered on, and the CPU 301 is executing a program such as an OS.
FIG. 8 is a diagram illustrating an operation flow of the bus interface circuit 310 in the master device when the device 300 as the master device requests the device 300 as the slave device to read or write data. The master device is, for example, the CPU 301, and the slave device is, for example, the HDD 304.

  First, in step S01, the internal processing module 311 transmits a bus use request signal (BR signal) to the bus arbiter 200 via the bus 100. The effective address generator 312 generates an address in the slave device of data to be read or written, and outputs this address to the output stage FIFO 320. Further, the internal processing module 311 outputs an identification signal indicating the read / write distinction to the output stage FIFO 320.

  The bus arbiter 200 that has received the BR signal performs arbitration so that the use periods of the bus 100 by a plurality of master devices do not overlap, and assigns the use period of the bus 100 to each master device. Then, the bus arbiter 200 transmits a bus use permission signal (BG signal) to the master device to be permitted.

In step S02, the process waits until the internal processing module 311 receives a bus use permission signal (BG signal). When the BG signal is received (step S02: YES), the process proceeds to step S03.
In step S03, the internal processing module 311 resets the counter and starts counting the bus clock signal BCLK.
In step S04, the internal processing module 311 waits until the head of the slot comes. When the head of the slot comes (step S04: YES), the process proceeds to step S05.

In step S05, the internal processing module 311 instructs the output stage FIFO 320 to output an address and an identification signal. Then, the output stage FIFO 320 outputs the address and the identification signal to the bus 100 via the buffer 321.
In step S06, if the request is a data read request, the internal processing module 311 resets the counter and starts counting the bus clock signal BCLK. On the other hand, if the request is a data write request, the internal processing module 311 outputs the data to be written to the output stage FIFO 320, resets the counter, and starts counting the bus clock signal BCLK.
In step S07, the process waits until the predetermined delay clock number is reached. If the predetermined delay clock number is reached (step S07: YES), the process proceeds to step S08.

In step S08, the internal processing module 311 determines whether the request to the slave device is read / write. If it is a read request (step S08: YES), the process proceeds to step S10, and if it is a write request (step S08: NO), the process proceeds to step S09.
In step S09, the internal processing module 311 instructs the output stage FIFO 320 to output data to be written. Then, the output stage FIFO 320 outputs the write target data to the bus 100 via the buffer 321.
On the other hand, in step S <b> 10, the internal processing module 311 takes in data to be read from the bus 100 to the input stage FIFO 330 via the buffer 331. In step S10, data to be read may not be captured. Since this is related to processing in the slave device, it will be described later.

Here, processing performed by the slave device will be described. FIG. 9 is a diagram illustrating an operation flow of the bus interface circuit 310 in the slave device.
In step B01, the address decoder 340 fetches an address and an identification signal from the bus 100 every time the head of the slot shown in FIG.
In step B02, the address decoder 340 determines whether or not the fetched address is an address corresponding to the own station. If it is an address corresponding to the own station (step B02: YES), the internal processing module 311 is notified to that effect, and the process proceeds to step S03. If the address does not correspond to the own station (step B02: NO), the process is also taken to step B01.
In step B03, the internal processing module 311 determines whether the request from the master device is read / write based on the identification signal. In the case of a write request (step B03: YES), the process proceeds to step B04. In the case of a read request (step B03: NO), the process proceeds to step B05.

In step B04, a process for writing data is performed. FIG. 10 is a diagram showing the flow of processing in step B04 in FIG.
In step C01, the internal processing module 311 resets the counter and starts counting the bus clock signal BCLK.
In step C02, the internal processing module 311 waits until a predetermined number of delay clocks is reached. This delay clock number is the same as the delay clock number in the description of the master device. If the predetermined number of delay clocks has been reached (step C02: YES), the process proceeds to step C03.

In step C03, the internal processing module 311 fetches data to be written from the bus 100 to the input stage FIFO 330 via the buffer 331 at a speed according to the bus clock signal BCLK. Then, the input stage FIFO 330 transfers the fetched data to the internal processing module 311 at a speed according to the internal clock signal CLK.
In step C04, the internal processing module 311 determines whether the fetched data is valid data. Here, “valid data” is data to be processed by the slave device. If the fetched data is valid data (step C04: YES), the process ends. On the other hand, if the data is not valid (step C04: NO), the processing after step C01 is repeated.

Returning to the description of FIG. 9, the processing after step B05 will be described.
In step B05, the internal processing module 311 determines whether a master cancel signal has been received. The master cancel signal is a signal transmitted from the master device to the slave device when data reading in the slave device is not performed within a predetermined period. Details will be described later. Here, first, the case where the master cancel signal is not received (step B05: NO), that is, the process of step B07 will be described.

In step B07, the internal processing module 311 performs processing for reading data. FIG. 11 is a diagram showing the flow of processing in step B07 in FIG.
In step D01, the internal processing module 311 starts preparation for output of data requested to be read. For example, when the slave device is the HDD 304, processing for reading data corresponding to the address fetched in step B01 in FIG. 9 from the recording surface of the magnetic disk is performed.
In step D02, the internal processing module 311 resets the counter and starts counting the bus clock signal BCLK.

In step D03, the internal processing module 311 waits until a predetermined number of delay clocks is reached. This delay clock number is the same as the delay clock number in the description of the master device. If the predetermined number of delay clocks has been reached (step D03: YES), the process proceeds to step D04.
In step D04, it is determined whether or not the requested data has been prepared. If the data preparation is complete (step D04: YES), the process proceeds to step D05. If the data preparation is not complete (step D04: NO), the process proceeds to step D06.
In step D05, the internal processing module 311 outputs the prepared data to the output stage FIFO 320 and outputs it to the bus 100 via the buffer 321 at a speed according to the bus clock signal BCLK.

  On the other hand, in step D06, the internal processing module 311 transmits a Retry response to the master device. Here, the Retry response is to request the master device to extend the period for reading data. Specifically, a valid signal of a normal L (Low) level is supplied to the control bus of the bus 100. In the case of the Retry (1) response, as shown in the timing chart of FIG. 7, the Valid signal is set to the H (High) level only for the period corresponding to the first clock of the data cycle. The data cycle is an invalid data cycle in which valid data is not transmitted. Thereafter, the internal processing module 311 repeats the processing after step D02.

Next, returning to FIG. 8, the processing after step S11 will be described.
In step S <b> 11, the internal processing module 311 determines whether valid data has been fetched from the bus 100. As described above, when data preparation is not completed before the predetermined number of delay clocks is reached, the slave device sets the Valid signal to the H level at the beginning of the data cycle. The internal processing module 311 determines that valid data has not been captured when the Valid signal is at the H level at the beginning of the data cycle. If valid data has been taken in (step S11: YES), the process ends. On the other hand, when valid data is not captured (step S11: NO), the process proceeds to step S12.

In step S12, the internal processing module 311 determines whether or not the elapsed time after transmitting the address to the slave device has reached a predetermined value. As shown in FIG. 11, when the preparation of the data requested from the master device is not completed before the predetermined delay clock number is reached, the slave device issues a Retry response, and the process for preparing the data is infinite. To continue to. In this embodiment, the following processing is performed in order to avoid infinite processing. In other words, when the elapsed time has not reached the predetermined value (step S12: NO), the processing after step S06 is repeated, and when the elapsed time has reached the predetermined value (step S12: YES, the process goes to step S13). move on.
In step S <b> 13, the internal processing module 311 transmits the BR signal to the bus arbiter 200 again.

In step S14, the internal processing module 311 waits until it receives a BG signal. If the BG signal is received (step S14: YES), the process proceeds to step S15.
In step S15, the internal processing module 311 resets the counter and starts counting the bus clock signal BCLK.
In step S16, the internal processing module 311 waits until the beginning of the slot arrives. If the beginning of the slot has arrived (step S16: YES), the process proceeds to step S17.
In step S17, the internal processing module 311 transmits a master cancel signal to the slave device, and ends the process. As shown in the timing chart of FIG. 7, the master cancel signal is transmitted by setting the Valid signal to the H level in the address cycle.

  Next, a case where the slave device receives a master cancel signal transmitted by the master device will be described. In the bus interface circuit 310 of the slave device, the internal processing module 311 determines that the master cancel signal has been received when the Valid signal is at the H level in the address cycle (FIG. 9, step B05: YES), and proceeds to step B06. move on. In step B06, the internal processing module 311 stops the process for reading data.

  FIG. 14 is a simulation result of bus utilization efficiency (%) when the slot offset value n is changed in a burst size of 4/8/16 cycles in the configuration of the present embodiment. According to this result, it can be seen that the delay time is minimum and the throughput is maximum when the offset value is 2 in the burst size 4/8 cycle and the offset value is 1 in the burst size 16 cycles.

<Modification>
The present invention is not limited to the form described above, and can be implemented in various forms. For example, the embodiment described above can be modified as follows.
<Modification 1>
In the above embodiment, the Retry response is expressed by setting the Valid signal to the H level at the beginning of the data cycle. However, a period of one clock is provided immediately before the data cycle, and valid data in the subsequent data cycle The slave device may transmit a signal indicating whether or not is transmitted during this period. In the example shown in FIG. 12, a period of 8 clocks is set as one slot, and a header cycle for transmitting a header is provided following the address cycle and the turn-off cycle. For example, the header value is “0” when valid data is transmitted, and the header value is “1” when valid data is not transmitted. When the header is “1”, the master device determines that the Retry response has been transmitted.
According to this configuration, there is no need to provide a signal line dedicated to the Valid signal, and the configuration of the information processing apparatus 1 can be simplified.

<Modification 2>
Further, when the number of address bits transmitted in the address cycle is smaller than the number of signal lines of the bus 100 (for example, when there are 32 signal lines for 30 bits of address), an extra signal line is used. A Valid signal may be transmitted.
For example, the value “0” is transmitted when the process is not stopped, and the value “1” is transmitted when the process is stopped. If the valid information is “1”, the slave device determines that the master cancel signal has been transmitted.
In this way, it is not necessary to provide a signal line dedicated to the Valid signal, so that the configuration of the information processing apparatus 1 can be simplified.

<Modification 3>
The length of the slot, address cycle, data cycle, and turn-off cycle may be changed as appropriate according to various conditions such as the type of data to be handled and the configuration of the apparatus.
Further, the number of devices connected to the bus 100 is not limited as long as it is two or more.

<Modification 4>
In the above embodiment, an example in which a turn-off cycle is provided has been described, but a configuration in which a turn-off cycle is not provided may be employed. Alternatively, a turn-off cycle may be provided either after the address cycle or after the data cycle.

<Modification 5>
In the above embodiment, each device 300 connected to the bus 100 has the function of both the master device and the slave device. However, all the devices 300 have the functions of both the master device and the slave device. It is not necessary that a certain device 300 has only a function as a master device, and another device 300 has only a function as a slave device. That is, one or more master devices and slave devices may be connected to the bus 100.
Alternatively, the master device may only make a write request to the slave device, and the slave device may only make a write in response to a request from the master device. In this case, the output of the identification signal by the master device and the processing for the slave device to determine read / write based on the identification signal may not be performed.

<Modification 6>
In the above embodiment, an example in which the master device transmits the identification signal indicating the read / write distinction to the slave device via the control bus has been described. For example, a period of one clock is provided before or after the address cycle, and this period The data indicating the read / write distinction may be transmitted to.

<Modification 7>
In the above-described embodiment, an example in which the present invention is applied to an information processing apparatus has been described. The present invention may be applied to any electronic device as long as it is a device that exchanges information.

It is a figure showing the whole structure of embodiment. 3 is a diagram illustrating a bus interface circuit 310. FIG. It is a figure showing the mode of data transmission in case offset value n is 2. FIG. 3 is a timing chart of data transmission on the bus 100. It is a figure showing a turn-off cycle. It is a figure showing BR signal and BG signal. It is a figure showing a Valid signal. It is a figure showing the flow of operation | movement of the bus interface circuit 310 in a master apparatus. It is a figure showing the flow of operation | movement of the bus interface circuit 310 in a slave apparatus. It is a figure showing the flow of a process in step B04 of FIG. It is a figure showing the flow of a process in step B07 of FIG. It is a figure showing a header cycle. It is a timing chart of conventional data transmission. It is a simulation result of bus use efficiency.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Information processing apparatus, 100 ... Bus, 200 ... Bus arbiter, 300 ... Device, 301 ... CPU, 302 ... ROM, 303 ... RAM, 304 ... HDD, 305 ... External I / F, 306 ... I / O device, 400 ... Oscillator 310 ... Bus interface circuit, 311 ... Internal processing module, 312 ... Effective address generator, 320 ... Output stage FIFO, 321 ... Buffer, 330 ... Input stage FIFO, 331 ... Buffer, 340 ... Address decoder.

Claims (11)

Request signal transmission for transmitting a bus use request signal representing a request for use of the bus to a bus arbiter that allocates the use period of the bus to each device so that the use periods of the bus by a plurality of devices connected to the bus do not overlap. Means,
Permission signal receiving means for receiving a bus use permission signal indicating permission of use of the bus transmitted by the bus arbiter;
When the head of the first period repeated at a constant period is detected and the head first arrives after the permission signal receiving means receives the bus use permission signal, it is shorter than the first period. Address output means for outputting an address of data to be read to the bus within a second period;
Subsequent to the second period, when the third period obtained by multiplying the period by a predetermined positive integer has elapsed, the second period from the period is changed from the period to the third period. Data input means for inputting data corresponding to the address output by the address output means within the fourth period subtracted and which is output by the slave device to the bus. circuit.   When the data input means requests the slave device to extend the period for preparing the data by the third period following the third period, the data input unit further includes the third period. The bus interface circuit according to claim 1, wherein the data is input within the fourth period after waiting.   When the slave device requests to extend the period for preparing the data by the third period, and when the elapsed time since the address output means outputs the address reaches a predetermined value 3. The bus interface circuit according to claim 2, further comprising stop instruction means for instructing the slave device to stop processing. The address output means, when the head first visits after the permission signal receiving means receives the bus use permission signal, sets an address to which data is written to the bus within the second period. Output,
When the third period has elapsed following the second period in which the address output means has output the address to which data is written, within the fourth period following the third period, The bus interface circuit according to any one of claims 1 to 3, further comprising data output means for outputting data corresponding to the address to the bus. An address input means for detecting a head of a first period repeated at a constant period and inputting an address output by the master device to the bus within a second period shorter than the first period;
Following the second period when the address input means inputs the address, when a third period obtained by multiplying the period by a predetermined positive integer has elapsed, following the third period, A bus interface circuit comprising: data output means for outputting data corresponding to the address to the bus within a fourth period obtained by subtracting the second period from the cycle.   The data output means extends a period for preparing the data by the third period when preparation for outputting the data corresponding to the address is not completed within the third period. The bus interface circuit according to claim 5, wherein the bus interface circuit requests the master device and executes the preparation only for the third period.   7. The bus interface circuit according to claim 6, wherein the data output means stops the preparation process when the master device instructs to stop the process. Determining means for determining whether or not the address input by the address input means is an address to which data is written;
When the address is a data write destination address as a result of determination by the determination means, the master device has data input means for inputting the data output to the bus within the fourth period. The bus interface circuit according to claim 5.   5. The bus interface circuit according to claim 1, wherein the address output means outputs an address during a period from the beginning to the middle of the second period.   9. The bus interface circuit according to claim 4, wherein the data output means outputs data during a period from the beginning to the middle of the third period. A bus for transmitting data;
A bus arbiter that allocates the use period of the bus to each device so that the use periods of the bus by a plurality of devices connected to the bus do not overlap;
A bus interface circuit according to claim 1;
An information processing apparatus comprising: the bus interface circuit according to claim 5.

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