JP4840963B2 - Bus system and control method thereof - Google Patents

Description

  The present invention relates to a bus system in which at least one master device and at least one slave device are interconnected.

  In recent years, IP (Intellectual Property) cores that require high throughput, such as from USB 1.1 to USB 2.0 or from PCI to PCI-Express, have been rapidly increasing. Along with this, the demand for an on-chip bus that enables high-speed throughput transfer is rapidly increasing (see, for example, Patent Document 1).

  In June 2003, ARM announced the AMBA 3.0 AXI (Advanced eXtensible Interface) protocol as a next-generation on-chip bus standard, and has attracted attention. AMBA is an abbreviation for “Advanced Microcontroller Bus Architecture”. In this AXI, the concept of a channel that was not found in the conventional AHB (Advanced High-Performance Bus) is introduced, and consideration is given to improving the data transfer throughput by performing transfer through this channel. Specifically, it supports an independent transfer method for the address phase and the data phase, and an out-of-order transfer method in which the result of the cycle entered later may be returned to the front.

  Here, as shown in FIG. 1, the channel is defined as a series of transfer paths in which the master 101 and the slave 102 transfer the data 105 by the 2-wire handshake using the signals of valid 103 and ready 104, respectively. The transfer source of data 105 outputs valid 103 and the transfer destination outputs ready 104.

  In this AXI, as shown in FIG. 2, data transfer is performed between the master 201 and the slave 202 using four channels of address 203, write data 205, read data 204, and write response 206. Therefore, since the address channel and the data channel can be transferred independently, address processing can be issued one after another, and the bus can be used effectively.

  Furthermore, by supporting out-of-order, it is possible to return data from a slave having a low latency first. For this reason, AXI can be expected to improve bus utilization efficiency.

  On the other hand, a system having a plurality of CPUs, memories, and I / Os inside a system LSI has become common, and these devices need to be connected to each other. However, a plurality of bus masters and bus slaves are not necessarily arranged and wired equally in the system LSI. For this reason, it is considered that it becomes clear at the stage of the layout process that some connection networks, particularly high-load buses such as addresses and data, cannot be operated at the expected operating frequency.

  In such a case, time and labor have been spent re-laying the path that does not satisfy the timing many times and guaranteeing the timing at the expected operating frequency. As a worst result, the operation frequency may be lowered or the chip size may be increased.

  Therefore, in order to solve such problems, a method is adopted in which a register is inserted into a signal group between a master and a slave, which is a critical path, and the path is divided to reduce the delay amount between the register and the register. Has been. In the case of the point-to-point connection such as AXI described above, the protocol is defined by the two-wire handshake, and the flow of information passed by the handshake is unidirectional. Easy. In AXI, this method is called “register slice”.

FIG. 3 is a diagram illustrating a connection example in which a register slice is inserted into the point-to-point connection illustrated in FIG. In the example shown in FIG. 3, the register slices 301 and 302 are inserted in one stage into the address channel and the read data channel to separate the paths. As a result, the latency from the address issuance of the master 201 to the reading of the read data is increased by two cycles, but it is possible to operate at twice the maximum operating frequency.
Special table 2004-513430 gazette

  As described above, a high operating frequency can be guaranteed by inserting a register for a point-to-point connection and dividing the path. However, even if the operating frequency is increased, the performance is not improved uniformly, and depending on the relationship between the throughput and the increased latency, the performance may be decreased.

  The average transfer rate with respect to the operating frequency when burst transfer is performed using a point-to-point connected 32-bit data bus as shown in FIG. 2 will be described with reference to FIGS.

  FIG. 4 is a diagram showing the relationship between the operating frequency and the transfer rate when 16 burst transfer is performed. FIG. 5 is a diagram showing the relationship between the operating frequency and the transfer rate when 4-burst transfer is performed.

  As shown in FIGS. 4 and 5, a difference in latency appears as a difference in average transfer rate between when the register slice is inserted and when no register slice is inserted. For example, when 16 burst transfer shown in FIG. 4 is performed, a transfer rate of 480 MByte / s is obtained at 120 MHz operation without register slice. On the other hand, if a register slice is inserted, the performance of 120 MHz operation without a register slice cannot be exceeded unless it is operated at an operating frequency of at least about 135 MHz.

  Here, the number of cycles required for 16 burst transfers without register slices is 16 cycles, and when register slices are inserted, 18 cycles due to an increase in latency of “+2 cycles”.

  Further, when the 4-burst transfer shown in FIG. 5 is performed, a transfer speed of 480 MByte / s is obtained at 120 MHz operation without register slice. On the other hand, when a register slice is inserted, the performance of 120 MHz operation without a register slice cannot be exceeded unless it is operated at an operating frequency of at least about 195 MHz.

  In other words, the smaller the burst length that is supported, the greater the demand for operating frequency when register slices are inserted.

  From the above results, when it is found that timing convergence at the target frequency is difficult at the layout stage, there are the following problems even if the target frequency can be satisfied by inserting a register slice. . That is, the target frequency is for the performance before the register slice is inserted, and after the register slice is inserted, the performance may not be satisfied as the latency increases. In this case, it is necessary to select a higher frequency from selectable frequency candidates to satisfy the performance.

  When deploying a developed system LSI platform from low-end models to high-end models according to product specifications, operating at a low operating frequency rather than operating at a high operating frequency for products with low required performance reduces power consumption. There are benefits. However, simply reducing the operating frequency for a system LSI with a register slice inserted may lead to increased performance and insufficient performance.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to switch the operating frequency regardless of the state of the master and the slave, and to arbitrarily perform it while maintaining the maximum transfer performance.

The present invention includes a path through inserted storage means between the master and slave devices, and any can be selected path selection means of the path not passing through the storage means, the operating frequency to the bus system In response to a switching request, an inactivation request is output to the master device, and when an inactivation notification is input from the master device, the operating frequency is switched and a path corresponding to the operating frequency is selected. And a control means for outputting a selection signal to the path selection means .

Further, the present invention is control of the bus system comprising a route via inserted storage means between the master and slave devices, the path selection unit can select one of the paths not passing through the storage means The method outputs an inactivation request to the master device in response to a request for switching the operating frequency to the bus system, and switches the operating frequency when an inactivation notification is input from the master device. In addition, a selection signal for selecting a route according to the operating frequency is output to the route selection means .

  According to the present invention, the operating frequency can be switched regardless of the state of the master and the slave, and can be arbitrarily performed while maintaining the maximum transfer performance.

  The best mode for carrying out the invention will be described below in detail with reference to the drawings.

  FIG. 6 is a diagram illustrating a configuration example inside the system LSI in the present embodiment. In this example, three master devices 601 to 603 and three slave devices 604 to 606 exist in the system LSI and are interconnected. The protocol connecting the master devices 601 to 603 and the slave devices 604 to 606 is a simple common protocol (FIG. 1) of valid, data, and ready. Then, four types of information (FIG. 2) of address, write data, read data, and write response are communicated.

  Here, the master-slave data transfer supports burst transfer, and a maximum of 16 burst transfers are possible. The burst transfer length is communicated as part of data in the address information phase. When operating in the fastest condition, it is assumed that it takes 16 cycles for the master to issue an address and take in 16 bursts of read data.

  It is assumed that the following products having different required performance are covered by one system LSI of this embodiment.

Product A: Request transfer rate 525MByte / s
Product B: Required transfer rate 475 MByte / s, low power specification From the relationship shown in FIG. 4, it can be seen that the operating frequency that satisfies the required transfer rate 525 MByte / s when there is no register slice is 130 MHz or higher. Therefore, in this system, the design, simulation, and logic synthesis are performed using the hardware description language in the system LSI design process, and the master and slave are operated at 160 MHz.

[Layout result]
How each device is arranged in the system LSI depends on various factors such as the relationship with other functional modules and external pins, and is rarely arranged evenly.

  Here, as a result of the layout, it is assumed that the path delay between the address of the master A 601 to the slave C 606 and the read data is 7.8 ns. Therefore, this path can operate at 120 MHz, but cannot operate at 160 MHz or higher (critical path). As can be seen from FIG. 4, the product A does not reach the target performance at 120 MHz. For all other paths, it is assumed that timing is guaranteed at 160 MHz.

  FIG. 7 is a diagram showing a configuration focusing on the master A 601 -slave C 606. In FIG. 7, the master device 601 and the slave device 606 are connected on a one-to-one basis (point-to-point). Here, only the address and read data channels whose timing could not be satisfied are shown. The clock 702 input to the master A 601 and the slave C 606 is generated by the clock generator 701 and can be selected from a plurality of frequency candidates (120, 140, 160, 180, 200 MHz) by the frequency selection signal 712 of the setting register 711.

[Insert register slice / bypass circuit from layout result]
In view of such layout results and target performance, as shown in FIG. 8, the circuit is changed so that timing can be guaranteed.

  FIG. 8 is a diagram illustrating operating conditions after the re-layout. In FIG. 8, “◯” indicates that operation is possible, and “x” indicates that operation is not possible.

  FIG. 9 is a diagram showing a configuration in which a register slice & bypass circuit is inserted in the layout process. As shown in FIG. 9, a register slice circuit 901 is inserted in the layout process for the address and read data signals. The configuration of the register slice circuit 901 differs depending on the number of stages in which the register slice is inserted, the location where the register slice is inserted, and the like. For example, two stages of register slices are inserted at locations where the path delay is large, or the ready path satisfies the request timing, so one stage is inserted only in the valid (data) path, and the configuration differs depending on the request level.

  A clock 913 input to the register slice circuit 901 is output from a clock control circuit 910 described later, and is also input to the master device 601 and the slave device 606. The clock control circuit 910 will be further described in detail with reference to FIG.

  FIG. 10 is a diagram illustrating an example in which a one-stage register slice is inserted only in valid (data). In general, the register slice circuit 901 is not simply composed of a sequential circuit, and a combinational circuit is mixed for handling a ready signal. Similarly, in the example shown in FIG. 10, when one register slice is inserted into valid (data), not only the registers 1001 and 1002 but also a combinational circuit (for example, an AND gate 1003) is included. Further, an inverted signal obtained by inverting the valid signal after insertion of the register slice by the inverter 1004 is output as the register slice inactivation signal 1005.

  Returning to FIG. 9, selector 902, 903, 904, and 905 are inserted in the subsequent stage of the register slice circuit 901 along with the register slice circuit 901, and a path that passes through the register slice circuit 901 and a path that does not pass through the register slice circuit 901 are selected. It can be so.

  The bypass selection signal 915 is a signal 1103 output from the output port of the selector circuit 1102 in the clock control circuit 910 shown in FIG. The input candidate group of the selector circuit 1102 corresponds to the bypass selection signal polarity for each frequency candidate, and a value is given according to the system operable at the frequency. If the timing shown in FIG. 8 is satisfied, “1” is output so as to bypass the register slice at 120 MHz, and “0” is passed through the register slice system at other frequencies. Confirm the value to output.

  Thereby, according to a frequency selection signal 1101 output from a CPU (not shown), an appropriate bypass selection signal 1103 corresponding to the change in frequency can be generated simultaneously. Therefore, it is not necessary for the user to bother to consider the relationship between the operating frequency and the bypass selection / non-selection, and erroneous setting that the operation cannot be performed can be prevented.

  With such a circuit configuration, it is possible to use a register slice system for 160 MHz operation and a system for bypassing the register slice for 120 MHz operation. As a result, the product A is operated at 160 MHz, and in the case of the product B whose required performance is lower than that of the product A, a register bypass system is used at a transfer of 120 MHz.

  For product B, the performance can be satisfied by operating at 140 MHz or 160 MHz using a register slice. However, the product B can be operated at 120 MHz without inserting a register slice, which has the advantage of reducing power consumption.

  In addition, regarding the generation of the bypass selection signal, by configuring the circuit so as to uniquely determine the register slice system or the bypass system depending on the operating frequency, the user only needs to focus on the frequency, which is convenient for the user. Can be improved.

  As described above, the clock frequency is switched and used for each product as an example. However, the clock frequency may be switched depending on the operation mode of the product. When switching according to the operation mode or the like, the timing at which switching of the operating frequency with bypass selection is requested is not necessarily in a state where point-to-point (one-to-one) communication is not performed. Of course, the register slice bypass system and the register slice system cannot be switched during communication. On the other hand, it is troublesome to perform switching control of the operating frequency while paying attention to whether or not one-to-one communication is being performed as viewed from the user.

  Therefore, the clock control circuit 910 performs handshaking with the master device 601 or the register slice circuit 901 so that it is not necessary to check whether or not the user is currently performing one-to-one communication and the operation frequency can be switched safely. It is carried out.

  As minimum signals necessary for this handshake, FIG. 9 shows a bus inactivation request 911, a master inactivation notification 912, and a register slice inactivation notification 914. This bus inactivation request 911 is a signal output from the clock control circuit 910 to the master device 601. The master deactivation notification 912 is a signal output from the master device 601 to the clock control circuit 910. The register slice inactivation notification 914 is a signal output from the register slice circuit 901 to the clock control circuit 910.

  Here, an operation in which the clock control circuit 910 performs handshaking with the above-described signal with the master device 601 or the register slice circuit 901 and performs bypass switching with the bypass selection signal 915 will be described with reference to FIGS. 12 and 13. .

  FIG. 12 is a flowchart showing the frequency switching operation in the clock control circuit 910. First, in step S1201, when the clock control circuit 910 receives a clock switching request 916 for switching the operating frequency from the user, the process proceeds to step S1202. In step S1202, it is determined whether the switching of the operating frequency is accompanied by bypass switching of the register slice circuit 901. This determination processing is processing for determining that it is not necessary to perform bypass switching, for example, when the operating frequency is switched from 140 MHz to 200 MHz, or from 180 MHz to 160 MHz. If it is determined that no bypass switching is involved, the process advances to step S1203 to immediately switch the operating frequency.

  On the other hand, when the switching of the operating frequency involves bypass switching, for example, when switching from 120 MHz to 160 MHz, or from 200 MHz to 120 MHz, the process proceeds to step S1204 and the above-described handshake is performed. First, in step S1204, the clock control circuit 910 outputs a bus inactivation request 911 to the master device 601, and in step S1205, a master inactivation completion notification 912 sent from the master device 601 is detected as a result. In step S1206, the register slice inactivation completion notification 914 sent from the register slice circuit 901 is detected.

  When these notifications 912 and 914 are detected, the process proceeds to step S1207, where the clock frequency and the bypass selection signal 1103 are switched by the frequency selection signal 1101. In step S1208, the bus inactivation request 911 output to the master device 601 is negated, and the process is completed.

  FIG. 13 is a flowchart showing the frequency switching operation in the master device 601. First, in step S1301, when the master device 601 detects the bus inactivation request 911 output from the clock control circuit 910, the process proceeds to step S1302, and issuance of a new address is interrupted. In step S1303, the process waits for completion of all data phases with respect to already issued addresses.

  Thereafter, when all the data phases are completed, the process advances to step S1304 to output a master inactivation notification 912 indicating that the bus inactivation has been completed to the clock control circuit 910. As a result, it waits for the bus inactivation request 911 from the clock control circuit 910 to be negated, and if it is detected in step S1305 that the bus inactivation request 911 has been negated, the state transits to the normal state and a new address is obtained. It is ready to issue.

  Note that the register slice inactivation notification 914 output from the register slice circuit 901 can be generated based on whether the valid signal of the register slice is inactive at the subsequent stage of the register slice. If multiple stages of register slices are inserted for valid, the valid signal at each stage may be NORed.

  In the present embodiment, the number of register slices is one. However, depending on the result of placement and routing, it is naturally possible to insert two or more registers. In this case, the present invention can be similarly applied. In addition, although only one master-slave connection to which the present invention is applied is handled, naturally a plurality of connections can also be applied.

  According to the present embodiment, by providing a register slice system and a bypass system thereof, it is possible to prevent degradation in performance due to an increase in latency due to the addition of a register slice, and to obtain an optimum operating frequency that does not become overspec with respect to required performance. You can choose. In addition, it is not necessary for the user to bother to consider the relationship between the operating frequency and bypass selection / non-selection, and erroneous setting of operation inability can be prevented. Furthermore, it is possible to respond to an operating frequency change request at an arbitrary timing from the CPU, and it is possible to perform safe switching to a system that is optimal in terms of performance.

  Even if the present invention is applied to a system composed of a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), it is applied to an apparatus (for example, a copier, a facsimile machine, etc.) composed of a single device. It may be applied.

  In addition, a recording medium in which a program code of software for realizing the functions of the above-described embodiments is recorded is supplied to the system or apparatus, and the computer (CPU or MPU) of the system or apparatus stores the program code stored in the recording medium. Read and execute. It goes without saying that the object of the present invention can also be achieved by this.

  In this case, the program code itself read from the recording medium realizes the functions of the above-described embodiment, and the recording medium storing the program code constitutes the present invention.

  As a recording medium for supplying the program code, for example, a floppy (registered trademark) disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a CD-R, a magnetic tape, a nonvolatile memory card, a ROM, or the like is used. be able to.

  In addition, by executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also the following cases are included. That is, when the OS (operating system) running on the computer performs part or all of the actual processing based on the instruction of the program code, and the functions of the above-described embodiments are realized by the processing.

  Further, the program code read from the recording medium is written in a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer. After that, based on the instruction of the program code, the CPU of the function expansion board or function expansion unit performs part or all of the actual processing, and the function of the above-described embodiment is realized by the processing. Needless to say.

It is a figure which shows the concept of the channel in an AXI (Advanced eXtensible Interface) protocol. It is a figure which shows four channels used for data transmission between a master and a slave. It is a figure which shows the example of a connection which inserted the register slice with respect to the point-to-point connection shown in FIG. It is a figure which shows the relationship between the operating frequency at the time of performing 16 burst transfer, and a transfer rate. It is a figure which shows the relationship between the operating frequency at the time of performing 4 burst transfer, and a transfer rate. It is a figure which shows the example of a structure inside the system LSI in this embodiment. It is a figure which shows the structure which paid its attention to master A601-slave C606. It is a figure which shows the operating condition after a re-layout. It is a figure which shows the structure which inserted the register slice & bypass circuit in the layout process. It is a figure which shows the example at the time of inserting the one-stage register slice only in valid (data). It is a figure which shows the allocation of the frequency after register slice of the clock control circuit 910, and bypass circuit insertion. 10 is a flowchart showing a frequency switching operation in the clock control circuit 910. 5 is a flowchart showing a frequency switching operation in the master device 601.

Claims (5)

A route selection unit capable of selecting one of a route passing through the storage unit inserted between the master device and the slave device, and a route not passing through the storage unit;
In response to a request for switching the operating frequency to the bus system, when an inactivation request is output to the master device and an inactivation notification is input from the master device, the operating frequency is switched and the operating frequency And a control unit that outputs a selection signal for selecting a route according to the route selection unit.   The control means performs only switching of the operating frequency when switching to an operating frequency that does not require path selection control by the path selecting means is requested as the operating frequency switching request. The bus system according to claim 1.   The control means outputs a selection signal for enabling a route passing through the storage means to the route selection means when the switching to the high frequency is requested as the operation frequency switching request, 2. The bus system according to claim 1, wherein when switching to a low frequency is requested, a selection signal for enabling a route that does not pass through the storage means is output to the route selection means.   The master device interrupts issuance of a new address to the bus in response to the deactivation request, and outputs a deactivation notification when a data phase for the issued address is completed. The bus system according to 1. A bus system control method comprising: a path that passes through a storage means inserted between a master device and a slave device; and a path selection means that can select either a path that does not pass through the storage means,
In response to a request for switching the operating frequency to the bus system, when an inactivation request is output to the master device and an inactivation notification is input from the master device, the operating frequency is switched and the operating frequency A bus system control method, comprising: outputting a selection signal for selecting a route according to the route selection means to the route selection means.

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