JP3300016B2 - Communication interface, recording device, and communication control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data communication interface and a recording device. More specifically, the present invention relates to a data communication interface for performing data communication with a connected external device, and a recording apparatus including the data communication interface.

[0002]

2. Description of the Related Art There is a recording apparatus that receives recording data from a connected external electronic device, forms an image based on the received recording data, and records this image on a recording medium. In a conventional recording apparatus of this type, the timing of a handshake in data communication between an external electronic device and the recording apparatus is fixed to a standard specific timing. Then, a method is adopted in which data communication with all general host computers is enabled by this standard timing.

[0003]

However, in the above conventional example, since the timing of the handshake signal is fixed, there are the following disadvantages. That is, 1. 1. In communication with various new and old host computers, communication can be executed only at the same data communication speed. 2. If the data communication speed is matched with the interface with the high communication speed, the data communication cannot be performed correctly with the interface having the low communication speed. If the data communication speed is matched to the low communication speed interface, the interface becomes a bottleneck even if the recording system including the host computer and the recording device has the ability to execute processing at the high communication speed. It has the disadvantage that communication processing cannot be performed.

[0004] Further, even if the timing of the handshake signal is changed, a great deal of time and expense is required because the hardware is changed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and has an advantage that the timing of a handshake control signal can be appropriately set according to the data communication speed of a connected external device. Communication interface and recording device for performing data communication at an appropriate communication speed with
An object of the present invention is to provide a communication control method .

[0006]

According to the present invention, there is provided a communication interface having the following configuration. That is, the communication interface receives communication data from the external device based on reception of an instruction signal from the external device, and receives communication data from the external device by repeating a procedure of returning a response signal to the external device. Outputting means for outputting the response signal to the external device after the response time interval including the time for receiving the communication data after receiving the instruction signal, and a time interval for receiving the instruction signal. And changing means for changing the response time interval, so that
The response time interval is changed as the time interval for receiving the instruction signal is shortened by changing the response time interval.

A recording apparatus according to the present invention for achieving the above object has the following arrangement. In other words, the recording device receives communication data from the external device based on the reception of the instruction signal from the external device, and receives communication data from the external device by repeating a procedure of returning a response signal to the external device. Output means for outputting the response signal to the external device after a response time interval including a time for receiving communication data after receiving the instruction signal, and a time interval for receiving the instruction signal. Changing means for changing the response time interval so as to shorten the response time interval, wherein the changing means changes the response time interval so as to shorten the time interval for receiving the instruction signal by changing the response time interval. Is changed. Further, a communication control method according to the present invention for achieving the above object includes a procedure for receiving communication data from an external device based on reception of an instruction signal from the external device, and returning a response signal to the external device. A communication control method for a device that receives communication data from the external device by repetition, wherein after the response time interval including the time for receiving the instruction data and after receiving the communication data, the response signal Outputting to the external device, and the step of changing the response time interval so that the time interval for receiving the instruction signal is shortened, and the changing step is performed by changing the response time interval. The response time interval is changed as the time interval for receiving the instruction signal becomes shorter.

[0008]

According to the above arrangement, an instruction signal from an external device is provided.
Captures communication data from the external device based on the
The procedure of returning a response signal to the external device.
The communication data is received from the external device by the return.
You. Here, the response signal is after receiving the instruction signal.
Response time interval, including the time to receive communication data.
Output to an external device after an error. In this communication,
Communication interface (or recording device, communication control method)
Method), the time interval for receiving the instruction signal from the external device is
Change the response time interval so that it is shorter
The time interval for receiving the indication signal is shortened by changing the interval.
Change the response time interval accordingly.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

[First Embodiment] A recording apparatus according to a first embodiment is connected to a host computer via a communication cable, receives recording data from the host computer, and performs recording on a recording medium. In the first embodiment, a description will be given using a Centronics interface as an example of the communication interface.

FIG. 1 is a configuration diagram of a communication interface unit with a host computer in the recording apparatus according to the first embodiment. In FIG. 1, each signal line 101 to 104 is
It is included in a communication cable and is for data communication with a host computer. The signal line 101 is a signal line for transferring print data, and the signal line 102 is a signal line for a data strobe signal (DTSTB signal) for notifying the data reception timing. Signal line 10
Reference numerals 3 and 104 denote signal lines for a BUSY signal and an ACK signal, respectively.

Reference numeral 105 denotes a flip-flop, which holds recording data transferred from the host computer via the signal line 101. 106 is a timer, DTSTB
Measure the period of the signal. A BUSY signal generation circuit 107 generates a BUSY signal which is one of the handshake signals. An ACK signal generation circuit 108 generates an ACK signal which is one of handshake signals. Reference numeral 109 denotes a FIFO memory, which temporarily stores the recording data held in the flip-flop 105. 1
Reference numeral 10 denotes a timing control unit which generates a write pulse to the FIFO and controls the write timing of the FIFO. A data bus 111 is connected to a data bus of a CPU described later. Reference numeral 112 denotes a signal line for a FIFO write pulse signal. Reference numeral 113 denotes a signal line for a read signal for reading from the FIFO, 114 denotes a signal line for a read signal for reading a timer value, 115 denotes a signal line for a BUSY reset signal for resetting a BUSY signal, ACK 116 sets an ACK signal
A signal line 117 for the set signal is a signal line for an ACK reset signal for resetting the ACK signal. Also, 11
Reference numeral 8 denotes a signal line for a clock (CLK) for driving the timer and driving the timing control circuit.

FIG. 2 is a block diagram of the recording apparatus according to the first embodiment. In FIG. 1, reference numeral 201 denotes a CPU, which controls the entire recording apparatus. Reference numeral 202 denotes an I / O control unit which generates various control signals and
Control. Reference numeral 203 denotes an interface unit having the configuration shown in FIG. Reference numeral 204 denotes a RAM, which is used for a work area of the CPU 201, storage of received data, and the like. Reference numeral 205 denotes a ROM, which stores a control program of the CPU 201, font information, and the like. 2
Reference numeral 06 denotes an image generation unit which generates recording image data and outputs it to the recording unit 207. A recording unit 207 performs recording and output on a recording medium. Reference numeral 208 denotes an address bus of the CPU 201, and reference numeral 209 denotes a data bus. Figure 1 above
Is connected to the data bus 209. A clock generator 210 generates a CLK signal for driving the timing control circuit 110 and the timer 106.

The CPU 201 executes various processes according to a control program on the ROM 205. Furthermore, CPU2
01 sets a predetermined data at a predetermined address to perform a read operation or a write operation,
Various control signals are generated on the respective signal lines 113 to 117 via the / O control unit 202, so that the interface unit 203 can be accessed.

The operation of the data interface unit 203 in the recording apparatus having the above configuration will be described.

First, the host computer sets recording data on a data signal line 101 and outputs a DTSTB signal to a data strobe signal line 102 for a certain period. The recording data on the signal line 101 is held in the flip-flop 105 at the leading edge of the DTSTB signal. Further, the timing control unit 110 controls the FiFo 109 at a timing slightly delayed from the leading edge of the DTSTB signal.
, A write pulse is generated. This write pulse is input to the FiFo 109 via the signal line 112,
At this time, the recording data held in the flip-flop 105 is written to the FiFo 109.

At the leading edge of the DTSTB signal, the BUSY signal is output by the BUSY generation circuit 107 to the host computer via the signal line 103. Furthermore, this D
At the leading edge of the TSTB signal, the timer 106 starts, and the current D
The time interval between the TSTB signal and the next DTSTB signal is measured.

The CPU 201 controls the AC at the timing described later.
A K set signal is output on a signal line 116, thereby
CK signal generation circuit 108 outputs an ACK signal. Thereafter, a BUSY reset signal is output on the signal line 115 at a later-described timing, whereby the BUSY signal generation circuit 1
07 resets the BUSY signal. Further, an ACK reset signal is output on the signal line 117 at a timing described later, and the ACK signal is reset by the ACK signal generation circuit 108. Also, the CPU 201 can sequentially read data stored in the FiFo 109 by generating a FiFo read signal. Further, the CPU 201
Generates a timer read signal,
06 can be read.

Next, an operation in which the signal line for handshaking adapts to the data communication speed of the host computer will be described below.

FIG. 3 shows an optimum B based on the cycle of the DTSTB signal.
FIG. 9 is a diagram for explaining how the timings of the USY signal and the ACK signal are set. Timing chart shown in FIG. 3 (1) represents the timing of the data communication in the first round, a diagram representing the timing of the BUSY signal, ACK signal by the initial value B _1. When the transmission of data from the host computer is started first, BUSY signal by the initial value B _1, it controls the ACK signal. Te is at the (1), the pulse width B ₁ of the BUSY signal is set sufficiently long, CPU 201 is a BUSY signal is reset after time B ₁ from coming DTSTB signal, wait for the next DTSTB signal. When the following DTSTB signal is recognized by reading the value of the timer 106 to obtain the period P ₁ of the DTSTB signal.

[0021] Te is at the (2) in FIG. 3, to reset the BUSY signal after Similarly period B ₂ and course (1), DTSTB
Obtaining a period P ₂ of the signal. At this time B ₂ is set shorter by the short time than B _1, Therefore P ₂ is shorter than P ₁ minute time.

As described above, the pulse width of the BUSY signal is gradually reduced. For example, the m-th data strobe period P _m and the (m + 1) -th data strobe period P
When _{m + 1} and is assumed to equal the pulse width B _m of the BUSY signal at this time is the optimal BUSY pulse width. This situation is shown in (m) and (m + 1) of FIG. Therefore m +
First after communicates by setting the pulse width of the BUSY signal to B _m.

The processing procedure for determining the optimum pulse width of the BUSY signal described above will be further described with reference to the flowchart of FIG. Figure 4 shows the optimal BUS
9 is a flowchart illustrating a processing procedure performed by a CPU 201 when determining a pulse width of a Y signal.

In step S1, n is set to 1, and
In step S2, the data strobe period P_n-1 That is
P₀ Is infinite. In step S3, the DTSTB signal is
Loop until it is recognized, and B in step S4_n Time elapsed
Then, the BUSY signal is reset. Next in step S5
Wait for DTSTB signal, and if DTSTB signal is confirmed
In step S6, the value of the timer is read and_n Toss
You. This P_n Is the DTSTB signal of the n-th communication.
It is a cycle. Next, in step S7, the current communication
DTSTB signal interval P_n And the previous DTSTB
Signal interval P_n-1 And P_n <P_n-1 If so
Proceed to step S9, otherwise proceed to step S8
No. In step S9, n = n + 1 is set, and in step S10
Proceed to. Then, in step S10, B_n-1 When it is smaller
A value smaller by T for B_n After setting in step S3
And the above processing is repeated. In step S7
P_n <P _n-1 If not, the process proceeds to step S8 and BUSY
Set the signal pulse width to B_n-1 To decide. And after this
Is the pulse width B_n-1 Of handshake by BUSY signal
Work.

As for the method of recognizing the DTSTB signal in steps S3 and S5, the DTSTB signal may be detected by an interrupt means, or the DTSTB signal may be used as a sense signal.

Although omitted for the sake of simplicity, it is desirable to adopt a method that takes into account some errors in the DTSTB signal period. For example, the same n
For example, a method of performing a test multiple times and taking an average is effective for this.

As described above, the means for detecting the cycle of the DTSTB signal is provided, and by changing the pulse width of the BUSY signal, it is adapted to the data transfer speed of the connected electronic device, and the optimum BUSY signal, The ACK signal cycle can be automatically set.

[Second Embodiment] In the second embodiment, the CPU 201
A communication interface for optimizing the timing of communication control without intervention of (software) will be described.

FIG. 5 shows an interface section of a recording apparatus according to the second embodiment. Reference numeral 501 denotes a BUSY / ACK signal generation circuit which generates a BUSY signal and an ACK signal. Reference numeral 502 denotes a counter, which outputs a BUSY signal and an ACK signal.
Generate signal timing. 503 is a subtractor,
The constant T is subtracted from the output value from the timer 106. Others are the same as the first embodiment, and the description thereof is omitted here.

In the second embodiment, the pulse width control of the BUSY signal is performed only by hardware. Example 1
Period P _n of DTSTB signal is measured by the timer 106 in the same manner as. The value of the period P _n of DTSTB signal outputted from the timer 106, after the predetermined value T is subtracted by the subtracter 503 is input to the counter 502. The counter 502 counts the CLK, and the subtracter 5
The BUSY signal and the ACK signal are controlled by the value output from the control signal 03.

The constant T is the cycle of the n-th DTSTB signal.
P_n , The period P of the (n + 1) -th DTSTB signal_{n + 1} 
Is selected such that is reduced. Therefore, P_n Against
P_{n + 1} Is reduced, thereby the pulse width B of the BUSY signal
_{n + 1} Also decreases. While repeating the above operation, P_n Is strange
No longer. That is, P_n Is B_n Affected by
It means that it is gone, B_n Also stops at this time
You. This situation is shown in the timing chart of FIG. FIG.
(A), the period P of the (n-1) -th DTSTB signal
_n-1 Is obtained. Next, in FIG._n-1 -T
ACK signal and BUSY signal are controlled based on the count value.
You. The cycle of the DTSTB signal at this time is P _n And Next
In FIG. 6 (c), P_n Based on the count value of -T
To control the ACK signal and the BUSY signal. And this
The period P of the DTSTB signal at the time of_{n + 1} Is the above (b)
P_n When it is equal to, the timing chart of FIG.
Communication is performed by the chart.

The numerical value T used in the above-described subtractor 503 needs to be a value larger than the time from the reset of the BUSY signal to the setting of the next DTSTB signal. That is, after the reset of the BUSY signal, the next DTSTB
Assuming that the time until signal setting is t, the subtractor constant T
Becomes T = t + α. And in the next data communication,
The interval between the DTSTB signals becomes narrower by the maximum of α.

As described above, according to each of the above embodiments, the pulse width of the BUSY signal automatically converges to the optimum value, and the highest transfer rate can be obtained.

In the first embodiment, the timing of the BUSY signal and the ACK signal is set by software. However, the processing procedure shown in the first embodiment may be executed by hardware. It is. In the second embodiment, the BUS is used only by hardware.
Although the timings of the Y signal and the ACK signal are set, the processing procedure of the second embodiment may be executed by software.

[Third Embodiment] In the third embodiment, the automatic communication control timing is not set as in the first and second embodiments, but various data communication speeds are set in advance by setting desired timing. A recording device that realizes the above will be described.

The recording apparatus according to the third embodiment connects a host computer via a communication cable, receives recording data from the host computer, and performs recording on a recording medium. In the present embodiment, a description will be given by taking a Centronics interface as an example of the communication interface.

The configuration of the interface unit according to the third embodiment will be described with reference to FIG.

FIG. 7 is a block diagram showing the configuration of the interface unit of the printing apparatus according to the third embodiment. Each of the signal lines 701 to 704 is included in the communication cable, and is a signal line for communication with the host computer. A signal line 701 is a signal line for transmitting recording data. A signal line 702 is a signal line for a data strobe signal (DTSTB signal) for notifying the data reception timing. 703 and 704 are signal lines for a BUSY signal and an ACK signal, respectively, which are signals for handshaking.

Reference numeral 705 denotes a demultiplexer, and DTS
Each flip-flop (706 to 70) receives the TB signal.
9) A latch signal is generated. Also, the signal line 71
3,714 via direct memory access (DM
A) A signal for controlling transfer The input of the DMAACK signal and the output of the DMAREQ signal are controlled, and the DMA transfer control of each of the flip-flops 706 to 709 is executed. 70
Reference numerals 6 to 709 denote first to fourth flip-flops, which hold received data in response to a latch signal from the demultiplexer 705. First to fourth flip-flops 706 to 7
The received data held at 09 is DMA-transferred to a RAM 205 described later via a data bus 712.

Reference numeral 710 denotes a counter starter, which has a DTS
Upon receiving the TB signal, the counter 711 is started. A counter 711 counts a clock (CLK) signal supplied via a signal line 715. 731 is BUSY
A count latch that holds a set value of a BUSY count. 732 is an ACK set count latch,
Holds the set value of ACK set count. 733 is A
A CK reset count latch that holds a set value of an ACK reset count.

Reference numeral 728 denotes a BUSY comparator.
The value held in the USY count latch and the signal line 7
The count value of the counter 711 input through the counter 18 is compared with the count value, and when the respective values match, a match signal is output to the control unit 723 via the signal line 724. 72
Reference numeral 9 denotes an ACK set comparator, which compares the value held in the ACK set count latch with the count value of the counter 711 input via the signal line 718, and when the values match each other, via the signal line 725. A match signal is output to the control unit 723. 730 is A
A CK reset comparator that compares a value held in an ACK reset count latch with a count value of a counter 711 input via a signal line 718;
When the values match, a match signal is output to the control unit 723 via the signal line 726.

Reference numeral 723 denotes a control unit which controls the timing of the BUSY signal and the ACK signal in accordance with a DMA control signal, various coincidence signals on the signal lines 724 to 726, and the like. 737 is a BUSY signal generation circuit, and DTSTB
A BUSY signal reset pulse from the control unit 723 input through the signal and the signal line 720 causes the BU
Set / reset the SY signal. Reference numeral 738 denotes an ACK signal generation circuit which controls the signal line 72 from the control unit 723.
An ACK signal is set / reset by an ACK set pulse signal input via the control unit 1 and an ACK reset pulse signal input via the signal line 722 from the control unit 723.

Further, a signal line 727 for inputting a temporary stop request signal to the control unit 723 and a BUSY
A signal line 717 for inputting a BUSY set signal to the signal generation circuit 737 is provided.

FIG. 8 is a configuration diagram of a recording apparatus according to the third embodiment. In the figure, reference numeral 801 denotes a CPU, which controls the entire recording apparatus. 802, an I / O control unit;
U801 generates various signals used when controlling the interface unit 803. An interface unit 803 has a configuration as shown in FIG.
A DMA control unit 804 controls the DMA transfer of the received data to the RAM. 805 is RAM
It is used as a work area for the CPU 801 and for various purposes such as storing received data. 806
Is a ROM, which stores a control program for the CPU 801, font information, and the like. An image generation unit 807 generates image data from the received recording data under the control of the CPU 801. A recording unit 808 records and outputs an image generated by the image generation unit 807 on a recording medium.

Reference numeral 809 denotes an address bus of the CPU 801. The signal line 810 is a signal line for a HOLD signal. The HOLD signal is output from the DMA control unit 804 to C
This signal is output to the PU 801 and indicates a bus request. The signal line 811 is a signal line for a HACK signal, and the HACK signal is a bus use permission signal output from the CPU 801 to the DMA control unit 804. 812 is a clock generator, and the signal line 71
5, a clock (CLK) signal for the counter is supplied to the interface unit 803.

In this recording apparatus, the recording data received by the interface unit 803 is DMA-transferred to the RAM 805 under the control of the DMA controller 804.
The CPU 801 sends the print data transferred to the RAM 805 to the image generator 807 according to the control program on the ROM 806. The image generated by the image generation unit 807 is sent to the recording unit 808 and recorded.

The I / O control unit 802 is connected to the address bus 809 and the data bus 712 of the CPU 801. CP
The U 801 can access the interface unit 803 by setting specific data at a specific address by a control program stored in the ROM 806.

The operation of the interface unit 803 in the recording apparatus having the above configuration will be described.

First, in order to determine the timing of the BUSY signal and the ACK signal, the BUSY count latch 73
The ACK set count latch 732 and the ACK reset count latch 733 each have a predetermined set value stored in the CPU.
801 is set. The set value is specified by the user using a predetermined operation means and operation procedure.

Next, when data transmission from the external host computer is started, the external host computer sets 8-bit data to the data line 701 and outputs a DSTB signal for a certain period. When the DTSTB signal is output, the demultiplexer 705 switches the first flip-flop 7
06, and the data on the data line 701 becomes the first
The data is held in the flip-flop 706. At this time, since the counter starter 710 activates the counter 711,
The counter 711 starts counting by the CLK signal. The BUSY signal generation circuit 737 generates a BUSY signal to notify the host computer that the recording apparatus is in the BUSY state.

The count value of the CLK signal by the counter 711 is determined by a BUSY comparator 728, an ACK set comparator 729, and an ACK reset comparator 730.
Is output to BUSY comparator 728 is BUSY
The set value set in the count latch 731 is compared with the count value from the counter 711, and when the count value is equal to the set value, a BUSY count match signal is output to the control unit 723. Similarly, the ACK set comparator 729 compares the set value of the ACK set latch 732 with the count value of the counter 711, and outputs an ACK set count match signal to the control unit 723 when they match. Similarly, ACK
The reset comparator 730 is connected to the ACK reset latch 7
The set value of the counter 33 is compared with the count value of the counter 711, and when they match, an ACK reset count match signal is output to the control unit 723.

In the control section 723, when there is no cause for temporarily stopping the reception sequence, the above-mentioned respective coincidence signals are used as a BUSY reset pulse, an ACK set pulse, and an ACK reset pulse, and a BUSY signal generation circuit 737 and an ACK signal generation circuit 738 are provided. Output to BU
In the SY signal generation circuit, the BUSY signal is
Set signal and BUSY reset pulse to BUS
Reset the Y signal. In the ACK signal generation circuit, an ACK signal is set by an ACK set signal.
The ACK signal is reset by the CK reset signal. When the last match signal among the above match signals is generated, the control unit 723 generates a sequence clear pulse, resets the counter starter 710 and the counter 711, and returns to the initial state.

When there is a cause for stopping the reception sequence, the control unit 723 outputs a STOP signal to the counter 711, and the counter 711 stops counting, whereby the reception sequence is temporarily stopped.

The operation of the interface unit 803 and the timing of the handshake signal will be described in more detail with reference to the timing charts of FIGS.

FIG. 9 is a timing chart showing a reception sequence by the interface unit 803 described above.
Reference numeral 901 denotes input reception data, which is held in a flip-flop at the leading edge of the DTSTB signal 902. 903
Represents a state where the counter 711 is counting the CLK signal. Reference numeral 904 denotes a point in time at which an ACK set count match signal is generated. That is, at this time, the set value of the ACK count latch matches the count value of the counter 711. Similarly, reference numeral 905 denotes a BUSY count coincidence signal, and reference numeral 906 denotes an ACK reset count coincidence signal. 907 is a BUSY signal, 908 is A
Represents the CK signal.

Based on the BUSY signal and the ACK signal, the host computer recognizes the reception state of the recording device, and executes the second data transmission when the first data transmission is completed. At this time, the demultiplexer 705 sends a latch signal to the second flip-flop 707, and the flip-flop 707 holds data. Then, the same processing as the above-described first data transmission is performed. Subsequently, the third data transmission is performed. In the third data transmission, the data is held in the third flip-flop 708 by the demultiplexer 705. Similarly, when the fourth data transmission is executed, the demultiplexer 705
As a result, data is held in the fourth flip-flop 709.

At the time of the fourth data reception, DMA transfer from the flip-flop to RAM 806 is executed. Hereinafter, the DMA transfer will be described.

The demultiplexer 705 sends a DMA transfer request to the DMA control unit 804 as DMARE.
This is performed by the Q signal. The DMA control unit 804 outputs a HOLD signal to the CPU 801 to request the release of the bus. The CPU 801 releases the bus and the HAC
When the K signal is input to the DMA control unit 804,
A DMAACK signal is output to the demultiplexer 705. In response to the DMAACK signal, the flip-flop outputs the held data to the data line 712, and the data is written to the RAM 805. The DMA transfer is executed as described above.
The ACK signal is reset. Then, it is recognized from the DMAREQ signal and the DMAACK signal whether or not the DMA transfer is being performed. That is, it can be understood that the DMA transfer is being performed from the time when the DMAREQ signal is set to the time when the DMAACK signal is set and reset.

The above DMAREQ signal and DMAACK
Based on the signal, the control unit 723 determines whether or not the DMA transfer is being performed, and controls the BUSY signal and the ACK signal. When data from the fourth data transmission is received,
The counter 711 is activated in the same manner as the first sequence,
The control of the BUSY signal and the ACK signal proceeds. The match signal generated first among the match signals is sent to the control unit 72.
3, when the DMA transfer is in progress, STO
The P signal is output, and the counter 711 is temporarily stopped. The control unit 723 outputs a BUSY reset pulse, A
The reception sequence is temporarily stopped without outputting the CK set pulse and the ACK reset pulse. And DMAA
When the end of the DMA transfer is recognized by the CK signal, ST
The OP signal is reset, and the counter starts counting again. Further, the control unit 723 outputs a BUSY reset pulse, an ACK set pulse, and an ACK reset pulse in accordance with each coincidence signal, and the reception sequence is restarted. When the above sequence is completed, the demultiplexer 7
05 returns to the initial state, and the next data is handled again as the first transmission data. Communication is executed by repeating the above-described four data receptions as one set.

FIG. 10 is a timing chart showing a sequence when the fourth data is received. The recording data 1001 is held in a flip-flop at the leading edge of the DTSTB signal 1002. Also, this DTSTB signal 1
At the leading edge of 002, the counter 703 starts operating, and the demultiplexer 705 outputs a DMAREQ signal (during DMA transfer). Until the end of the DMA transfer is recognized by the DMAACK signal from the DMA control unit 804, the first match signal (AC in this example)
When the K set count match signal 1004) is generated, the counter is stopped. When the DMA ACK signal is output and the DMA transfer ends, the counter 711 starts counting again and simultaneously outputs the ACK signal. Thereafter, when the BUSY count match signal 1005 and the ACK reset count match signal 1006 are generated,
The USY signal and the ACK signal are reset. Also,
When the ACK reset count coincidence signal 1006 is generated, the counter 711 is cleared, and the reception sequence is initialized.

In FIG. 7, a signal line 727 is a signal line for a sequence stop request signal by software. The data is output to the control unit 723 by the CPU 801 via the I / O control unit 802. As shown in FIG. 11, when this sequence stop request signal 1011 is set, the counter 7 in the fourth data reception described above is set.
As in the case of the temporary stop operation of No. 11, a wait for the input of the first coincidence signal is performed, and a STOP signal is output to the counter 711. Thus, the reception sequence can be temporarily stopped by software. Then, the sequence stop request signal 1
When 011 is reset, the receiving sequence is restarted.

CPU 80 in the above-described reception sequence
The first processing operation will be described in more detail with reference to the flowchart of FIG.

In step S21, the count of BUSY reset is counted by the BUSY reset count latch 731.
Set to. In step S22, the count number of the ACK set is stored in the ACK set count latch 732.
Set to. Further, in step S23, the ACK reset count number is stored in the ACK reset count latch 7.
Set to 33. Subsequently, in step S24, the DMA control unit 804 is initialized, and the reception sequence is started. The receive sequence itself is DM
The process is completed up to the A transfer, and the recording data is transferred to the RAM 805. The CPU 801 determines in step S25 that the DMA
A predetermined process is performed on the recording data on the RAM 805 to which the transfer has been completed.

If there is a factor for stopping the sequence in step S26, a stop request signal is output in step S27, and the BUSY signal is set to stop the reception sequence. If it is not necessary to stop the reception sequence, the process returns to step S25. When the reception sequence is stopped in step S27, the process proceeds to step S28, and if there is a factor for stopping the sequence, the process loops and waits until the factor for stopping the sequence disappears. When the cause of the sequence stop is eliminated, the process proceeds to step S29, where the stop request signal is reset, and the reception sequence is restarted.

In the third embodiment, the signal is generated in the order of ACK set → BUSY reset → ACK reset, but is not limited to this.
Any order may be used as long as the condition that the ACK set is earlier than the ACK reset is satisfied.

As described above, according to the third embodiment, the hardware executes the reception sequence according to the timing set by the software. Therefore, the timing of the reception sequence can be appropriately adjusted according to the data communication speed of the external host computer. Can be set.

[Fourth Embodiment] FIG. 13 is a block diagram of an interface section of a recording apparatus according to a fourth embodiment.
13, the control unit 723 in FIG. 7 is omitted. Reference numeral 1301 denotes a sequence clear pulse generation circuit, and reference numerals 1302 to 1304 denote flip-flops holding respective coincidence pulses. 1305 is STO
The P signal generation circuit includes a DMAREQ signal and a DMAAC signal.
It is determined whether or not DMA transfer is being executed based on the K signal.
If the MA transfer is in progress, the STOP signal is output to the counter 71.
Output to 1. Other configurations are the same as those in FIG. 7 of the third embodiment, and the description thereof is omitted here.

As for the reception sequence, the timing setting of the reception sequence and the first to third reception operations are the same as those in the third embodiment, so that the description thereof is omitted here, and the fourth reception is performed. The operation will be described below with reference to FIG.

In the fourth reception sequence, the DM
The A transfer processing is the same as that of the third embodiment, but the method of stopping the reception sequence during the DMA transfer is different. FIG. 14 is a timing chart of the reception sequence of the fourth data reception according to the fourth embodiment. In the interface unit according to the fourth embodiment, the STO for stopping the counter of the counter 711 is used.
The P signal 1401 is generated by the STOP signal generation circuit 1305 at the timing when the DMAREQ signal 1010 is set. Then, DACK is given by DMAACK signal 1011.
The end of the MA transfer is detected, and the STOP signal generation circuit 130
5 restarts the operation of the counter 711 by resetting the STOP signal 1401, and restarts the reception sequence operation.

When the clear pulse generation circuit 1301 detects that all the count match signals (BUSY reset count match, ACK set count match, ACK reset count match signal) are held in each of the flip-flops 1302 to 1304, it is cleared. A clear pulse signal is generated from the pulse generation circuit 1301. With this clear pulse signal, the reset of the counter 711 and the reset of the flip-flops 1302 to 1304 are executed, and the reception sequence for one cycle ends.

According to the fourth embodiment, compared to the third embodiment,
This is the same as the third embodiment except that the counter stop period is lengthened by the amount by which the count is immediately stopped by the DMAREQ signal without waiting for the input of the first count match signal at the time of the DMA transfer in the second reception sequence. Since the control unit 723 is omitted, the configuration is simplified.

In the third and fourth embodiments, B
A plurality of combinations of the set values of each timing of the USY signal and the ACK signal may be registered, and the registered combination may be selected according to the data communication speed of the host computer.

In each of the above embodiments, the Centronics system is used as the data communication interface, but the present invention is not limited to this.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of one device. Needless to say, the present invention can be applied to a case where the present invention is achieved by supplying a program to a system or an apparatus.

[0075]

As described above, according to the present invention, it is possible to appropriately set the timing of a control signal for handshaking in accordance with the data communication speed of a connected external device, and And data communication at an appropriate communication speed. In particular, instructed by an external device
From receiving the signal to issuing the response signal
Since the response time interval including the reception time is properly controlled,
The communication interface according to the communication speed of the external device
It can be established dynamically and is convenient.

[0076]

[Brief description of the drawings]

FIG. 1 is a block diagram of a communication interface unit with a host computer in a recording apparatus according to a first embodiment.

FIG. 2 is a block diagram of a recording apparatus according to a first embodiment.

FIG. 3 is a timing chart from the cycle of a DTSTB signal to the setting of optimal timing of a BUSY signal and an ACK signal.

FIG. 4 is a flowchart illustrating a processing procedure for determining an optimum pulse width of a BUSY signal.

FIG. 5 is a block diagram of an interface unit of a printing apparatus according to a second embodiment.

FIG. 6 is a timing chart of communication by an interface unit according to the second embodiment.

FIG. 7 is a block diagram of a communication interface unit with a host computer in a printing apparatus according to a third embodiment.

FIG. 8 is a block diagram of a recording apparatus according to a third embodiment.

FIG. 9 is a timing chart of data communication in the interface unit according to the third embodiment.

FIG. 10 is a timing chart of data communication in the interface unit according to the third embodiment.

FIG. 11 is a timing chart of data communication in the interface unit according to the third embodiment.

FIG. 12 is a flowchart illustrating a processing operation in a reception sequence according to the third embodiment.

FIG. 13 is a block diagram of an interface unit according to a fourth embodiment.

FIG. 14 is a timing chart of a fourth communication operation according to the fourth embodiment.

[Explanation of symbols]

 105 flip-flop 106 timer 107 BUSY generation circuit 108 ACK generation circuit 201 CPU 202 IO control unit 203 interface unit 204 RAM 205 ROM 206 image generation unit 207 recording unit

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 13/38-13/42 G06F 3/12 G06K 15/00

Claims (11)

(57) [Claims] 1. A communication for receiving communication data from an external device by repeating a procedure of fetching communication data from the external device based on reception of an instruction signal from the external device and returning a response signal to the external device. An interface, comprising: an output unit that outputs the response signal to the external device after a response time interval including a time for receiving communication data after receiving the instruction signal; and receiving the instruction signal. Changing means for changing the response time interval, so that the time interval for receiving the instruction signal is shortened by changing the response time interval, A communication interface, wherein the response time interval is changed. 2. The communication interface according to claim 1, wherein the response signal is a signal received by the external device before the external device transmits a next instruction signal. 3. A measuring device for measuring a time interval for receiving the instruction signal, wherein the changing device shortens the response time interval as the time interval measured by the measuring device becomes shorter. The communication interface according to claim 1 or 2, wherein: 4. The apparatus according to claim 3, further comprising detecting means for detecting that the time intervals measured by said measuring means become equal before and after said response time interval is changed by said changing means. Communication interface as described in. 5. The apparatus according to claim 4, wherein the change unit does not change the response time interval after the detection unit detects that the measured time intervals have become equal. Communication interface. 6. A record for receiving communication data from an external device by repeating a procedure of fetching communication data from the external device based on reception of an instruction signal from the external device and returning a response signal to the external device. An output unit configured to output the response signal to the external device after a response time interval including a time for receiving communication data after receiving the instruction signal; and receiving the instruction signal. Changing means for changing the response time interval so as to shorten the time interval, wherein the changing means changes the response time interval so that the time interval for receiving the instruction signal is shortened, A recording apparatus characterized by changing a response time interval. 7. The recording apparatus according to claim 6, wherein the response signal is a signal received by the external device before the external device transmits a next instruction signal. 8. The apparatus according to claim 1, further comprising a measuring unit that measures a time interval for receiving the instruction signal, wherein the changing unit shortens the response time interval as the time interval measured by the measuring unit decreases. 8. The recording apparatus according to claim 6, wherein 9. The apparatus according to claim 8, further comprising detecting means for detecting that the time intervals measured by said measuring means become equal before and after said response time interval is changed by said changing means. The recording device according to claim 1. 10. The recording apparatus according to claim 9, wherein the change unit does not change the response time interval after the detection unit detects that the time intervals have become equal. 11. An apparatus for receiving communication data from an external device by repeating a procedure of fetching communication data from the external device based on reception of an instruction signal from the external device and returning a response signal to the external device. Outputting the response signal to the external device after receiving the instruction signal and after a response time interval including a time for receiving communication data has elapsed, and the instruction signal Changing the response time interval so that the time interval for receiving the command signal is shortened, and the changing step is performed in response to the time interval for receiving the instruction signal being shortened by changing the response time interval. And changing the response time interval.