JP3395762B2 - Data processing system and data transmission method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing system and a data transmission method for transmitting data to and from an external storage device using a serial interface.

[0002]

2. Description of the Related Art Conventionally, there has been known a data processing device to which a memory card containing a storage medium such as a flash memory is connected. A data processor of this type and a memory card connected to the data processor will be described with reference to the drawings.

As shown in FIG. 11, the data processing apparatus 100 comprises a data processing unit 101, a register 102, a host side serial interface circuit 103, and a host side controller 104. Further, the memory card 110 includes a memory 111, a register 112, a card side serial interface circuit 113, and a card side controller 114.

The data processing unit 10 of the data processing device 100
1 reads the data stored in the memory card 110, performs various data processing, and performs various data processing to generate data to be written in the memory card 110. That is,
The data processing unit 101 is a data processing circuit of various devices using the memory card 110.

The register 102 is a buffer between the data processing unit 101 and the host side serial interface 103. That is, when the data processing device 100 supplies data from the data processing unit 101 to the host side serial interface circuit 103, this register 102 is used.
The temporary data is stored in and is supplied to the host-side serial interface circuit 103. Similarly, the data processing device 100 includes the host-side serial interface circuit 1
When data is supplied from 03 to the data processing unit 101, temporary data is stored in the register 102 and then supplied to the data processing unit 101.

Host-side serial interface circuit 1
03 converts the data supplied from the data processing unit 101 via the register 102 and the command supplied from the card-side controller 114 into a serial signal and supplies the serial signal to the memory card 110. Further, the host-side serial interface circuit 103 converts the data and command of the serial signal supplied from the memory card 110 into a parallel signal and supplies the parallel signal to the data processing unit 101 and the card-side controller 114.

Further, the host-side serial interface circuit 103 has a data and command synchronization signal (CL).
K) and chip select signal (CS) to memory card 1
Supply to 10. Further, the host-side serial interface circuit 103 receives the busy signal (BUSY) and the interrupt signal (IN) supplied from the memory card 110.
TERRUPT) is acquired.

The host side controller 104 controls the data processing operation of the data processing section 101 and the data transmission operation of the host side serial interface circuit 103. The host-side controller 104 also sends a command, which is a control instruction to the memory card 110, to the register 112.
To the memory card 110 via.

On the other hand, the memory 111 of the memory card 110
Stores, for example, data supplied from the data processing unit 101 such as a flash memory.

The register 112 is a buffer between the memory 111 and the card side serial interface circuit 113. That is, the memory card 110 has the memory 111
When writing data from the data processor 100, the temporary data is stored in the register 102 and then the data to be written is supplied to the memory 111. Similarly, in the memory card 110, the data processing device 100 stores the memory 11
When reading the data from 1, the data to be read after the temporary data is stored in the register 102 is supplied to the card side serial interface circuit 113. The register 112 is a circuit that functions as a page buffer of the flash memory.

Card-side serial interface circuit 1
13 is based on the control of the card side controller 114,
The data of the parallel signal supplied from the memory 111 and the command supplied from the card-side controller 114 are converted into a serial signal and supplied to the data processing device 100. In addition, the card side serial interface circuit 11
3 converts the data and command of the serial signal supplied from the data processing device 100 into a parallel signal, and supplies the parallel signal to the memory 111 and the card-side controller 114.

Further, the card side serial interface circuit 113 is provided with a synchronizing signal (CL for data and command).
K) and the chip select signal (CS) from the data processing device 100. Furthermore, the card-side serial interface circuit 113 outputs a busy signal (BUSY).
And an interrupt signal (INTERRUPT) to the data processing device 100.

The card-side controller 114 is the memory 1
The data storage operation, the read operation, the erase operation, and the like of 11 are controlled based on the command and the like supplied from the data processing device 100. In addition, the card-side controller 114 is
The transmission operation of each data of the card side serial interface circuit 113 is controlled. The host-side controller 104 also sends a busy signal or an interrupt signal, which is a status signal of the memory card 110, to the memory card 110.
To get from.

Data transmission between the data processing device 100 and the memory card 110 as described above is performed via a transmission line provided between the host side serial interface circuit 103 and the card side serial interface circuit 113. .

Between the card side serial interface circuit 113 of the data processing device 100 and the card side serial interface circuit 113 of the memory card 110, there are a CLK line, a CS line, a DT line and a BUSY.
Five signal lines, a line and an INT line, are provided.

Data to be processed by the data processing unit 101, which is main data, and data to be written to the memory 111 and data to be read from the memory 111 to the data processing unit 101 are transmitted to the DT line. Also, on the DT line,
A command that is a control command supplied from the data processing device 100 to the memory card 110 and a command supplied from the memory card 110 to the data processing device 100 are transmitted. That is, main data and commands are bidirectionally transmitted as serial signals to the DT line.

On the CLK line, the synchronization signal of the main data and the command transmitted to the above-mentioned DT line is supplied from the data processing device 100 to the memory card 110.

A so-called chip select signal is supplied from the data processing device 100 to the memory card 110 on the CS line. This chip select signal indicates that the above-mentioned main data, command, and sync signal are valid during, for example, a high period.

In the BUSY line, the memory card 110
A busy signal is transmitted indicating that is processing. For example, when the memory card 110 is performing a writing process and the access from the data processing device 100 is prohibited, the busy signal is supplied from the memory card 110 to the data processing device 100.

On the INT line, an interrupt signal indicating an interrupt from the memory card 110 to the data processing device 100 is supplied from the memory card 110 to the data processing device 100.

A time chart of various signals transmitted through such a transmission line is as shown in FIG. Using the time chart shown in FIG. 12, the memory card 1
The case of reading the data stored in 10 will be described.

First, at time t ₁₁ , the data processing device 100 supplies a chip select signal to the memory card 110 via the CS line. Data processing device 100
Synchronizes the chip select signal with the sync signal
Supply through the line. The memory card 110 prepares to acquire the command supplied from the data processing device 100 by acquiring this chip select signal. Then, when the data processing device 100 supplies this chip select signal, the data processing device 100 sends a command indicating a read command and its address via the DT line to the memory card 110.
Supply to.

The data processing device 100 uses this read code.
After the supply of mand, etc. is completed, time t ₁₂In this
Supply of command and sync signal is stopped. Memory card 11
0 receives this command when it finishes acquiring the command.
The busy signal is processed by the data in order to perform command-based control.
It is supplied to the processing device 100. That is, the memory card 11
0 indicates whether the main data at the specified address is stored in the memory 111.
Control to read from the register 112. In addition, with this
Then, the data processing device 100 supplies the chip select signal.
Salary does not stop.

When the memory card 110 reads out the main data from the register 112, the supply of the busy signal is stopped at time t ₁₃ . That is, the data processing apparatus 100 is notified of the ready state indicating that the main data is ready to be transmitted.

When the data processing device 100 learns that the supply of the busy signal has stopped, it determines that the control based on the command supplied by the memory card 110 has ended, and at time t ₁₄ , the synchronization signal is sent to the memory card 110. Supply. Then, the memory card 110 transmits the main data to the data processing device 100 via the DT line.

Then, when the memory card 110 finishes the transmission of the main data, the data processing device 100 causes the time t ₁₅
At, the supply of the synchronization signal and the chip select signal is stopped.

[0027] Incidentally, the memory card 110, the result or the like of the read processing, if the change in the internal state of the memory card 110 has occurred, as shown at time t _16, IN
An interrupt signal indicating an interrupt is supplied to the data processing device 100 via the T line. Data processing device 100
When this interrupt signal is supplied, the memory card 1 acquires a predetermined command together with the chip select signal in order to acquire the interrupt factor from the memory card 110.
Supply to 10.

As described above, the data processing device 100 is
DT line for transmitting main data and commands, CLK line for supplying synchronization signal, CS line for supplying chip select signal, BUS for acquiring busy signal
A Y line and an INT line for acquiring an interrupt signal are provided to realize data transmission with the memory card 110.

[0029]

In consideration of downsizing of the memory card 110 which is the external storage device described above, it is necessary to reduce the number of signal lines between the data processing device 100 and the memory card 110. .

The present invention has been made in view of such circumstances, and is a case where data is transmitted by a serial signal, and the number of signal lines used for transmitting this serial data is reduced. It is an object of the present invention to provide an external storage device used in a data processing device that enables the above.

[0031]

A data processing system according to the present invention is a data processing system for processing data between a data processing device and an external storage device.

In this data processing system, the data processing device transmits / receives data to / from the external storage device by a host-side serial signal input / output unit and a host-side serial signal input / output unit. A control signal output unit for supplying a control signal for controlling the timing of data switching to the external storage device, and a synchronization signal for data transmitted / received by the host side serial signal input / output unit to the external storage device. And a synchronization signal output section. Here, the host-side serial signal input / output unit transmits at least control command data for controlling the operation of the external storage device,
A serial signal is used to receive a status signal indicating the operation state of the external storage device, transmit data to be written to the external storage device, and receive data to be read from the external storage device.

On the other hand, the external storage device transmits / receives data to / from the data processing device by a serial signal input / output unit on the external device side for transmitting / receiving data by a serial signal and a serial signal input / output unit on the external device side. A control signal input unit that receives a control signal for controlling the timing of data switching from the data processing device, and a synchronization signal that receives a synchronization signal of data transmitted and received by the external device side serial signal input / output unit from the data processing device. And a signal input section. Here, the external device side serial signal input / output unit performs at least reception of the control command data, transmission of the status signal, reception of written data, and transmission of read data by serial signals.

In this data processing system, the control signal output section outputs a control signal according to data transmitted and received between the host side serial signal input / output section and the external device side serial signal input / output section. The signal level is set to a predetermined level. Further, when the external device side serial signal input / output unit changes from the state of not accepting signal input from the data processing device to the state of waiting for signal input, a ready signal that repeats the change of the signal level at a predetermined cycle is transmitted. Output as a signal. Further, the external device side serial signal input / output unit outputs a busy signal having a constant signal level when the external storage device performs processing based on the control command data and does not accept a signal input from the data processing device. Either output as a status signal or stop the output of the signal, and stop the output of the signal when an error occurs during the reception of the control command data.

In this data processing system, the signal level of the control signal supplied to the external storage device depends on the data transmitted and received between the serial signal input / output unit on the host side and the serial signal input / output unit on the external device side. It is set to a predetermined level. Further, when the external storage device changes from the state of not accepting a signal input from the data processing device to the signal input waiting state, a ready signal that repeats the change of the signal level at a predetermined cycle is output from the external storage device. Also,
When the external storage device is performing processing based on control command data and is not accepting signal input from the data processing device, the external device side serial signal input / output unit outputs a busy signal with a constant signal level as a status signal. Or the output of the signal from the serial signal input / output unit on the external device side is stopped. Further, when an error occurs when the external storage device receives the control command data, the output of the signal from the external device side serial signal input / output unit is stopped.

A data transmission method according to the present invention is a data transmission method for transmitting data between a data processing device and an external storage device.

The data processing device used in this data transmission method includes a host-side serial signal input / output unit for transmitting / receiving data to / from the external storage device by a serial signal, and the host-side serial signal input / output unit. A control signal output section for supplying a control signal for controlling the timing of switching of data transmitted and received by the external storage device, and a synchronization signal for data transmitted and received by the host side serial signal input / output section to the external storage device. And a synchronization signal output unit for supplying the same. Here, the host-side serial signal input / output unit transmits at least control command data for controlling the operation of the external storage device, receives a status signal indicating the operating state of the external storage device, and writes the status signal in the external storage device. Transmission of data and reception of data read from the external storage device are performed by serial signals.

On the other hand, the external storage device transmits / receives data to / from the data processing device by a serial signal input / output unit on the external device side for transmitting / receiving data by a serial signal, and a serial signal input / output unit on the external device side. A control signal input unit that receives a control signal for controlling the timing of data switching from the data processing device, and a synchronization signal that receives a synchronization signal of data transmitted and received by the external device side serial signal input / output unit from the data processing device. And a signal input section. Here, the external device side serial signal input / output unit performs at least reception of the control command data, transmission of the status signal, reception of written data, and transmission of read data by serial signals.

Further, in this data transmission method, the control output from the control signal output unit according to the data transmitted and received between the host side serial signal input / output unit and the external device side serial signal input / output unit. The signal level of the signal is set to a predetermined level. Further, when the state of the external storage device changes from the state of not accepting a signal input from the data processing device to the signal input waiting state, the signal level changes from the external device side serial signal input / output unit at a predetermined cycle. The ready signal that repeats is output as a status signal. Further, when the state of the external storage device is in the state of performing the processing based on the control command data and not accepting the signal input from the data processing device, the signal level from the external device side serial signal input / output unit is constant. The busy signal is output as a status signal, or the output of a signal from the external device side serial signal input / output unit is stopped. Further, when an error occurs when the control command data is received by the external device side serial signal input / output unit, the output of the signal from the external device side serial signal input / output unit is stopped.

In this data transmission method, the signal level of the control signal supplied to the external storage device is predetermined according to the data transmitted and received between the host side serial signal input / output unit and the external device side serial signal input / output unit. Level. Further, when the external storage device changes from the state of not accepting a signal input from the data processing device to the signal input waiting state, a ready signal that repeats the change of the signal level at a predetermined cycle is output from the external storage device. Also, when the external storage device is performing processing based on the control command data and the signal input from the data processing device is not accepted, a busy signal with a constant signal level is output from the external device side serial signal input / output unit. It is output as a status signal or the output of a signal from the external device side serial signal input / output unit is stopped. When an error occurs when the control signal data is received by the external device side serial signal input / output unit, the output of the signal from the external device side serial signal input / output unit is stopped.

[0041]

BEST MODE FOR CARRYING OUT THE INVENTION A data processing device used in a data processing device and a data transmission method according to the present invention and a memory card which is an external storage device used in the data processing device will be described below with reference to the drawings. .

First, a data processing device constituting a data processing system according to the present invention will be described. The data processing device 10 includes a data processing unit 11, a register 12, and a host side serial interface circuit as shown in FIG. 1
3 and a host-side controller 14. The memory card 20 is a storage medium having a card-like appearance, and is connected to the data processing device 10 and used as an external storage device. The memory card 20 includes a memory 21, a register 22, and a card-side serial interface circuit 2
3 and a card-side controller 24.

The data processing section 11 of the data processing device 10
Reads the data stored in the memory card 20, performs various data processing, and performs various data processing to generate data to be written in the memory card 20. The data processing unit 11 serves as a data processing circuit of an audiovisual device such as a computer device that uses the memory card 20, a recording / reproducing device of a digital audio signal, and a camera device.

The register 12 is a buffer between the data processing unit 11 and the host side serial interface 13. That is, the data processing device 10 includes the data processing unit 1
When data is supplied from 1 to the host-side serial interface circuit 13, the data is temporarily stored in the register 12 and then supplied to the host-side serial interface circuit 13. Similarly, when supplying data from the host-side serial interface circuit 13 to the data processing unit 11, the data processing device 10 temporarily stores the data in the register 12 and then supplies the data to the data processing unit 11.

Host-side serial interface circuit 1
The memory card 2 3 converts the data supplied from the data processing unit 11 via the register 12 and the command supplied from the card-side controller 24 into a serial signal.
Supply to 0. Further, the host-side serial interface circuit 13 converts the data and command of the serial signal supplied from the memory card 20 into a parallel signal and supplies the parallel signal to the data processing unit 11 and the card-side controller 24.

Further, the host-side serial interface circuit 13 uses the synchronizing signals (CL
K) etc. are supplied to the memory card 20. Further, the host-side serial interface circuit 13 acquires a status (STATUS) signal supplied from the memory card 20 and indicating the operating state of the memory card 20.

The host controller 14 controls the data processing operation of the data processing unit 11 and the data transmission operation of the host serial interface circuit 13. The host-side controller 14 also supplies a command, which is a control command for the memory card 20, to the memory card 20 via the register 22.

On the other hand, the memory 21 of the memory card 20 is
For example, the data processing unit 1 includes a flash memory or the like.
The data supplied from 1 is stored.

The register 22 is a buffer between the memory 21 and the card side serial interface circuit 23.
When the memory 21 writes the data from the data processing device 10, the temporary data is stored in the register 12 and then the data to be written is supplied to the memory 21. Similarly, when the data processing device 10 reads data from the memory 21, the temporary data is stored in the register 12 and then the read data is supplied to the card side serial interface circuit 23. That is, the register 22 is a circuit that functions as a so-called page buffer of the flash memory.

Card side serial interface circuit 2
Under the control of the card-side controller 24, 3 converts the parallel signal data supplied from the memory 21 and the command supplied from the card-side controller 24 into a serial signal, and supplies the serial signal to the data processing device 10. Further, the card side serial interface circuit 23 converts the data and command of the serial signal supplied from the data processing device 10 into a parallel signal and supplies the parallel signal to the memory 21 and the card side controller 24.

The card-side serial interface circuit 23 also uses various data and command synchronization signals (CL
K) and the like are acquired from the data processing device 10. Further, the card-side serial interface circuit 23 supplies a status signal to the data processing device 10.

The card-side controller 24 has a memory 21.
The data storage operation, the data read operation, the data erase operation, and the like are controlled based on commands and the like supplied from the data processing device 10. The card-side controller 24 also controls the transmission operation of each data of the card-side serial interface circuit 23. Furthermore, the host controller 14
Controls to supply a status signal to the memory card 20 to the memory card 20.

Data transmission between the data processing device 10 and the memory card 20 as described above is performed via a transmission line provided between the host side serial interface circuit 13 and the card side serial interface circuit 23. .

Between the card side serial interface circuit 23 of the data processing device 10 and the card side serial interface circuit 23 of the memory card 20, CLK is provided.
Line 31, control line 32, and DT line 33
And three signal lines are provided.

To the DT line 33, main data, that is, data processed by the data processing unit 11 and written in the memory 21, and data read from the memory 21 to the data processing unit 11 are transmitted. A command which is a control command supplied from the data processing device 10 to the memory card 20 and a command supplied from the memory card 20 to the data processing device 10 are transmitted to the DT line 33. That is, main data and commands are bidirectionally transmitted to the DT line 33 as serial signals.

Further, the DT line 33 is provided with a resistor 33a whose one end is grounded. This resistor 33
Reference numeral a is a so-called pull-down resistor, and when a signal is not transmitted / received by the DT line 33 between the host side serial interface circuit 13 and the card side serial interface circuit 23, the signal level of the DT line 33 is low level. Become. In other words, when the signal is not transmitted / received by the DT line 33, the signal level of the DT line 33 becomes a constant level determined by the resistance value of the resistor 33a and the like.

Here, a so-called pull-down resistor is adopted as the resistor 33a so that the signal level of the DT line 33 becomes low level when a signal is not transmitted and received by the DT line 33. A so-called pull-up resistor is adopted, and when the signal is not transmitted / received by the DT line 33, the DT line 3
The signal level of 3 may be set to a high level.

On the CLK line 31, the synchronization signal of the main data and the command transmitted to the DT line 33 described above is transmitted from the data processing device 10 to the memory card 20.

A control signal is transmitted from the data processing device 10 to the memory card 20 on the control line 32. The main data and commands described above are transmitted during the period when the control signal is supplied, for example, during the high period.

Here, in addition to the main data and the command, a status (STATUS) signal indicating the operation state of the memory card 20 is supplied from the memory card 20 to the data processing device 10 on the DT line 33 described above. The status signal from the memory card 20 is the DT line 3
3 is supplied in a period in which main data and commands are not transmitted, that is, a period in which a control signal is not supplied, for example, a low period. The status signal includes a busy signal indicating that the memory card 20 is performing processing. For example, memory card 2
When 0 is performing the writing process and the access from the data processing device 10 is prohibited, a busy signal is supplied from the memory card 20 to the data processing device 10.

Further, the status signal includes an interrupt signal indicating an interrupt from the memory card 20 to the data processing device 10. For example, when the memory card 20 requests an interrupt command from the data processing device 10, this interrupt signal is supplied. The busy signal and the interrupt signal are examples, and any signal may be used as long as it is a signal indicating the operating state of the memory card 20 as the status signal.

As described above, in order to supply the status signal while the control signal is not supplied, the output circuit as shown in FIG. 2 may be provided in the memory card 20.

The output circuit 25 of the memory card 20 includes the card side serial interface circuit 23 and the DT line 3.
It is provided between the input / output terminal 3 and the input / output terminal 3, and includes an input buffer 26, an output buffer 27, a changeover switch 28, and an OR circuit 29.

The input buffer 26 is connected to the DT line 33, receives the serial signal supplied from the data processing device 10, and supplies the serial signal to the card side serial interface circuit 23.

The output buffer 27 outputs the serial signal, the busy signal and the interrupt signal supplied via the changeover switch 28 to the DT line 33.

The busy signal and interrupt signal supplied from the card-side controller 24 are supplied to the OR circuit 2.
3 is ORed and the terminal 28 of the changeover switch 28 is
b. The serial signal supplied from the card side serial interface circuit 23 is supplied to the terminal 28 a of the changeover switch 28.

The changeover switch 28 is changed over to the terminal 28a side when the control signal is high. When the changeover switch 28 is switched to the terminal 28 a side, the serial signal from the card side serial interface circuit 23 is supplied to the output buffer 27. When the control signal is low, the changeover switch 28 has the terminal 2
It is switched to the 8b side. The changeover switch 28 is the terminal 28
When switched to the b side, status signals such as a busy signal and an interrupt signal from the card side controller 24 are supplied to the output buffer 27.

A time chart of various signals transmitted on such a transmission line is shown in FIG. A case where the main data stored in the memory card 20 is read will be described with reference to the time chart shown in FIG.

First, at time t ₂₁ , the data processing device 10 supplies a control signal to the memory card 20 via the control line 32. Memory card 20
Prepares to acquire the command supplied from the data processing device 10 by acquiring this control signal. The data processing device 10 supplies this control signal, and also supplies a command or the like indicating a read command to the memory card 20 via the DT line 33. In addition, the data processing device 10, along with this command, etc.
A synchronization signal is supplied to the memory card 20 via the LK line 31.

When the data processing apparatus 10 finishes supplying the read command and the like, it stops supplying the command, the control signal and the synchronizing signal at time t ₂₂ .
Note that the synchronization signal does not have to stop the supply at time t _22.

When the memory card 20 finishes acquiring the command, it supplies a busy signal to the data processing device 10 through the DT line 33 to perform control based on the supplied command. Since the data processing device 10 does not supply the control signal at this time, the data processing device 10 can determine that the signal supplied from the memory card 20 is a busy signal. When the memory card 20 supplies the busy signal, the memory card 20 reads the main data of the specified address from the memory 21 to the register 22.

When the memory card 20 reads out the main data from the register 22, the supply of the busy signal via the DT line 33 is stopped at the time t ₂₃ . That is, the data processing device 10 is notified of the ready state indicating that the main data is ready to be supplied.

When the data processing device 10 finds that the supply of the busy signal is stopped at time t ₂₄ , it determines that the control based on the command supplied by the memory card 20 is completed, and supplies the control signal and the synchronization signal. do.
Based on the supply of the control signal, the memory card 20 synchronizes the main data with the supplied synchronization signal via the DT line 33 and transmits the main data to the data processing device 10.

When the memory card 20 finishes transmitting the main data, the data processing device 10 stops the supply of the synchronizing signal and the control signal at time t ₂₅ .

When a change occurs in the internal state of the memory card 20 as a result of the reading process or the like, the memory card 20 transmits the data via the DT line 33 at time t ₂₆ as necessary. An interrupt signal indicating an interrupt is supplied to the data processing device 10. Since the data processing device 10 does not supply the control signal, the data processing device 10 can determine that the signal supplied from the memory card 20 is an interrupt signal. When the interrupt signal is supplied, for example, this interrupt factor is detected by the memory card 20. The control signal is supplied to obtain from the command and the corresponding command is supplied.

As described above, the data processing device 10 and the memory card 20 can reduce the number of signal lines by transmitting the status signal from the memory card 20 using the DT line 33. Therefore, it is not necessary to specially provide a signal line for a busy signal or an interrupt signal, and reliable data transmission can be performed with a simple configuration. Further, when data is transmitted between the data processing device and the memory card without providing an interrupt signal, polling must be performed at regular intervals, but this data processing device 10 requires polling. There is no.

By the way, the data processing apparatus 1 as described above
In the case of data transmission between the memory card 20 and the memory card 20, the content of the command supplied from the data processing device 10 to the memory card 20 or the data processing device 1 from the memory card 20.
The contents of the command supplied to 0 are previously determined by the host-side controller 14 and the card-side controller 24. For example, a write command, a read command, an erase command, etc. are predetermined. When these commands are transmitted via the DT line 33, the order of data and commands or status signals to be subsequently transmitted to the DT line 33 is always determined.

Specifically, when a write command is transmitted from the data processing device 10 to the memory card 20, the memory card 20 is sent after this write command.
Main data to be written into the memory card 20 is transmitted from the data processing device 10 to the memory card 20. The memory card 20 to which the write command and the main data are transmitted outputs a busy signal to the data processing device 10 while performing the write processing of the main data, and outputs a ready signal when the write processing of the main data is completed. Output to the processing device 10. Further, when the read command is transmitted from the data processing device 10 to the memory card 20, the memory card 20 performs the read process of the main data according to the read command. The memory card 20 outputs a busy signal to the data processing device 10 during the reading process, and outputs a ready signal to the data processing device 10 when the reading process is completed. After the data processing device 10 receives the ready signal, the memory card 2
Main data is transmitted from 0 to the data processing device 10, and thereby main data is read.

Therefore, as a second data transmission method, a case where the contents of the data transmitted by the DT line 33, the order thereof, and the like are predetermined by a command will be described below.

In this second data transmission method, the state of data transmitted on the DT line 33 is set by switching the control signal. That is, by switching the control signal, the state of the data to be transmitted is determined and the data is transmitted.

The state of the data transmitted by the DT line 33 is set as follows. First, the state in which no control command, that is, a command is not supplied from the data processing device 10 to the memory card 20 and the memory card 20 is not performing any process is the "state 0".
And Subsequently, a state in which a command is supplied from the data processing device 10 to the memory card 20, for example, a state in which a write command, a read command, an erase command, or the like is supplied via the DT line 33 is “state 1”. And After that, the state transits to "state 2" and "state 3" in which the processing according to the command supplied in "state 1" is performed, and returns to "state 0" after "state 3".

Then, the control signal switches such states from "state 0" to "state 3". That is, in "state 0", the control signal is low, and when the control signal goes high from the state of "state 0", the control signal is switched to "state 1". Then, when the control signal goes low from the "state 1", the state is switched to the "state 2". Then, when the control signal goes high from the "state 2", the state is switched to the "state 3". Finally, when the control signal goes low from the "state 3", the state switches to "state 0".

In this way, by switching the control signal, the content of the data transmitted by the DT line 33 is switched. Then, the data processing device 10 and the memory card 20 determine the contents of the data to be transmitted to the next “state 2” and “state 3” according to the contents of the command transmitted in the “state 1” and determine the respective states. Perform processing according to.

Specifically, for example, when the main data is read from the memory card 20, first, the "state 1" is set, and the data processing device 10 causes the memory card 20 to read.
The read command is transmitted to. Next, the state becomes "state 2", and the main data is read by the memory card 20 in response to the read command. While performing this process, the data processing device 10
When the busy signal is transmitted to the data processing device 10 and the processing is completed, a ready signal is transmitted from the memory card 20 to the data processing device 10. When the ready signal is detected by the data processing device 10, the state becomes “state 3”, and the memory card 2
The main data read from 0 is transmitted from the memory card 20 to the data processing device 10 via the DT line 33. When the main data transmission is completed, the state returns to "state 0".

Alternatively, for example, when writing main data to the memory card 20, first, "state 1" is set.
Then, the write command is transmitted from the data processing device 10 to the memory card 20. Next, the state becomes “state 2”, and the main data to be written in the memory card 20 is transferred from the data processing device 10 to the memory card 20 via the DT line 33.
Be transmitted to. Next, the state becomes “state 3”, and the main data write processing is performed by the memory card 20 in response to the write command. During this process, a busy signal is transmitted from the memory card 20 to the data processing device 10, and when the process is completed, a ready signal is transmitted from the memory card 20 to the data processing device 10. And
When the data processing device 10 detects the ready signal, the state returns to "state 0".

Alternatively, for example, when erasing the main data written in the memory card 20, first,
In the “state 1”, the erase command is transmitted from the data processing device 10 to the memory card 20. Next, the state becomes "state 2", and the main data is erased by the memory card 20 in response to the erase command. During this process, the memory card 20 transmits a busy signal to the data processing device 10. When the process is completed, the memory card 20 transmits a ready signal to the data processing device 10. When the data processing device 10 detects the ready signal, the state returns to "state 0".

As described above, regarding the second data transmission method for controlling the state of data transmission by switching the control signal according to the data transmitted to the DT line 33, refer to the time charts of FIGS. 4 and 5. Then, it will be described in more detail. Here, the time chart shown in FIG. 4 is an example of a time chart when the main data written in the memory card 20 is read by the data processing device 10. In addition, the time chart shown in FIG.
3 is an example of a time chart when the main data is written in the memory card 20 by the data processing device 10.

First, the reading of main data will be described with reference to FIG.

In the state where no data is transmitted between the data processing device 10 and the memory card 20, the control signal is low, which is the initial state of "state 0". Then, the process for reading the main data is started from the initial state of "state 0".

At time t _{31 when the} processing for reading the main data is started, the data processing device 10 switches the control signal supplied to the memory card 20 via the control line 32 from low to high. Therefore, the state of the data transmitted on the DT line 33 is switched from "state 0" to "state 1". The memory card 20 obtains this control signal,
It is determined that the state is changed from the “state 0” to the “state 1”, and preparations are made to acquire the command supplied from the data processing device 10. Then, in the “state 1”, the data processing device 10 supplies the read command to the memory card 20 via the DT line 33, and supplies the synchronization signal to the memory card 20 via the CLK line 31. . Here, the memory card 20 determines the content of the data transmitted via the DT line 33 in the subsequent “state 2” and “state 3” by acquiring the read command in this “state 1” state. To do.

The data processing device 10 switches the control signal from high to low at time t ₃₂ when the supply of the read command is completed. That is, the "state 1" is switched to the "state 2".

When the "state 2" is reached, the memory card 20
Performs a process based on the read command supplied in the "state 1", specifically, a process of reading the main data of the address specified by the read command from the memory 21 to the register 22. During this process, the memory card 20 sends the busy signal DT as the status signal.
It is supplied to the data processing device 10 through the line 33. That is, in the "state 2", the memory card 20 first outputs a busy signal as a status signal. At this time, in the data processing device 10, since the command supplied to the memory card 20 is a read command and the current state is “state 2”, the signal output from the memory card 20 is a status signal. To judge.

After that, when the reading of the main data into the register 22 is completed, the memory card 20 is
At time t ₃₃ when the reading of the main data into the
The output of the busy signal as a status signal is stopped through the DT line 33, and the output of the ready signal indicating that the main data is ready to be supplied to the data processing device 10 is started. That is, in the "state 2", the memory card 20 outputs a ready signal as a status signal when the reading of the main data to the register 22 is completed.

In this example, in the "state 2", D
When the signal output from the memory card 20 via the T line 33 is high, the busy signal is used, and when the signal is low, the ready signal is used. In this "state 2", the data processing device 10 reads the command supplied to the memory card 20 and the current state is "state 2".
Therefore, it can be determined that the signal output from the memory card 20 is the status signal.
Therefore, by simply switching the signal output from the memory card 20 through the DT line 33 from high to low, the data processing device 10 can detect that the signal is switched from the busy signal to the ready signal. .

The data processing device 10 includes a memory card 20.
When the ready signal is received from, it is determined that the processing of the memory card 20 based on the read command is completed. Then, switch the control signal from the low at time t ₃₄ the processing of the memory card 20 is determined to be completed based on the read command high. That is, the "state 2" is switched to the "state 3".

When the "state 3" is reached, the memory card 20 transmits the main data read to the register 22 in the "state 2" to the data processing device 10 via the DT line 33. Then, at time t ₃₅ the transmission of main data has been completed from the memory card 20 to the data processing apparatus 10, the data processing apparatus 10 switches to the low control signal from high with stopping the supply of the synchronizing signal. That is, from "state 3" in which main data is transmitted,
The state is returned to the initial state “state 0”.

When the internal state of the memory card 20 changes due to the influence of the read processing as described above and it is necessary to perform some kind of interrupt processing, the memory card 20 displays the time t ₃₆ as shown in FIG. , "State 0", an interrupt signal indicating an interrupt is supplied to the data processing device 10 via the DT line 33. Here, when the data processing device 10 is in the “state 0”, the memory card 20
Is set in advance so that when the signal is supplied via the DT line 33, it is determined that the signal is an interrupt signal. As a result, this signal is judged by the data processing device 10 to be an interrupt signal. The data processing device 10 that has received this interrupt signal performs necessary processing based on the interrupt signal.

Next, writing of main data will be described with reference to FIG.

In the state where no data is transmitted between the data processing device 10 and the memory card 20, the control signal is low, which is the initial state of "state 0". The process for writing the main data is started from the initial state of "state 0".

At time t _{41 when the} processing for writing the main data is started, the data processing device 10 switches the control signal supplied to the memory card 20 via the control line 32 from low to high. Therefore, the state of the data transmitted on the DT line 33 is switched from "state 0" to "state 1". The memory card 20 obtains this control signal,
It is determined that the state is changed from the “state 0” to the “state 1”, and preparations are made to acquire the command supplied from the data processing device 10. Then, in the “state 1”, the data processing device 10 supplies the write command to the memory card 20 via the DT line 33, and supplies the synchronization signal to the memory card 20 via the CLK line 31. . Here, the memory card 20 determines the content of the data transmitted via the DT line 33 in the subsequent “state 2” and “state 3” by acquiring the write command in this “state 1” state. To do.

The data processor 10 switches the control signal from high to low at time t ₄₂ when the supply of the write command is completed. That is, the "state 1" is switched to the "state 2".

In the "state 2", the data processing device 10
Is the main data to be written to the memory card 20
The time t when the main data is transmitted to the memory card 20 via the T line 33 and the main data is completely transmitted to the memory card 20.
_{At 43} , switch control signal from low to high. That is, the "state 2" is switched to the "state 3".

When the "state 3" is reached, the memory card 20
Performs a process based on the write command supplied in the "state 1", specifically, a process of writing the main data transmitted from the data processing device 10 in the memory 21 in the "state 2". During this process, the memory card 20 supplies a busy signal as a status signal to the data processing device 10 via the DT line 33. That is, in the "state 3", the memory card 20 first outputs a busy signal as a status signal. At this time,
Since the command supplied to the memory card 20 is the write command and the current state is “state 3”, the data processing device 10 determines that the signal output from the memory card 20 is a status signal. .

After that, when the writing of the main data to the register 22 is completed, the memory card 20 makes the register 22
At time t ₄₄ when the writing of the main data to the
As a status signal, stop outputting the busy signal,
The output of the ready signal indicating that the writing of the main data is completed is started. That is, in the "state 3", the memory card 20 outputs a ready signal as a status signal when the main data writing to the register 22 is completed.

In this example, in the "state 3", D
When the signal output from the memory card 20 via the T line 33 is high, the busy signal is used, and when the signal is low, the ready signal is used. In this "state 3", the data processing device 10 has the write command as the command supplied to the memory card 20, and the current state is "state 3".
Therefore, it can be determined that the signal output from the memory card 20 is the status signal. Therefore, by simply switching the signal output from the memory card 20 through the DT line 33 from high to low, the data processing device 10 can detect that the signal is switched from the busy signal to the ready signal. .

The data processing device 10 includes a memory card 20.
When the ready signal is received from, it is determined that the processing of the memory card 20 based on the write command is completed. Then, at time t _{45 when} it is determined that the processing of the memory card 20 based on the write command is completed, the data processing device 10 stops the supply of the synchronization signal and switches the control signal from high to low. That is, the state is returned from the "state 3" in which the main data is being written to the initial state "state 0".

Note that the internal state of the memory card 20 changes due to the influence of the above writing process,
If necessary to do some interrupt processing occurs, the memory card 20, as shown at time t _46, the interrupt signal indicating the interruption when the "state 0" DT line 33
And is supplied to the data processing device 10 via. Here, when the data processing device 10 is in the “state 0”, the memory card 2
When a signal is supplied from 0 through the DT line 33, it is preset so as to determine that the signal is an interrupt signal. As a result, this signal is judged by the data processing device 10 to be an interrupt signal. Then, the data processing device 10 that has received this interrupt signal performs necessary processing based on the interrupt signal.

As described above, in the data processing device 10 and the memory card 20 to which the present invention is applied, the control signal is switched to determine the content of the data to be transmitted to the DT line 33. Three
3 enables transmission of not only commands and main data but also status signals and interrupt signals. Therefore, the data processing device 10 and the memory card 20
The number of signal lines between and can be reduced. Therefore, it is not necessary to specially provide a signal line for a busy signal or an interrupt signal, and reliable data transmission can be performed with a simple configuration. Further, the overhead of switching the data to be transmitted on the DT line 33 can be reduced, and the efficiency of data transmission can be improved.

In the above example, the case of the data processing device 10 and the memory card 20 is described, but the present invention can be applied to another data processing device instead of the memory card 20. In this case, it is necessary to set the command to be transmitted and the like in another data processing device in advance, but not only the command for the memory card 20 but also any command can be transmitted.

Further, in the description of the second data transmission method between the data processing device 10 and the memory card 20, the contents of the transmission data of the DT line 33 which is switched by the control signal are set to state 0, state 1 and state 2. Although the four patterns of the state 3 have been described as examples, the patterns are not limited to these four patterns and may be switched to more patterns depending on the content of the command to be transmitted.

Furthermore, in the description of the second data transmission method between the data processing device 10 and the memory card 20, D
Although the case of switching the state of the transmission data of the T line 33 by turning on / off the control signal has been described, it may be switched by a pulse signal as shown in FIGS. 6 and 7. 6 and 7 are time charts when a pulse signal is used as a control signal, and FIG. 6 reads the main data written in the memory card 20 by the data processing device 10 as in FIG. 7 is a time chart when the main data is written in the memory card 20 by the data processing device 10 as in FIG.

Further, in the memory card 20 described above, for example, the CLK line 31, the control line 3
In addition to the 2 and DT lines 33, a small-sized memory card having one power supply line, three ground lines, and three reserve lines and a total of ten signal lines may be used. When three reserve lines are provided, these three reserve lines are used as DT lines to make four DT lines in combination with the DT line 33, and these four DT lines are used in parallel. You may do it. Also, when three reserve lines are provided, these three reserve lines are respectively CL
It is used as the K line, control line and DT line, and the CLK line 31 and the control line 3 are used.
Two sets of a CLK line, a control line and a DT line may be provided together with the 2 and the DT line 33.

By the way, in the second data transmission method described above, for the command and the main data transmitted on the DT line 33, by transmitting the error correction code and the like together, noise from the outside, etc. However, regarding the control signal transmitted on the control line 31, only by switching from high to low or from low to high, "state 0", "state 1", "state 2", "state 0" Since the transition of the state 3 "is shown, there is a risk of being affected by noise or the like from the outside.

For example, in the example shown in FIGS. 4 and 5,
The control signal is low in the "state 0" and "state 2", and the control signal is high in the "state 1" and "state 3". The determination of "state 0" and "state 2" and the determination of "state 1" and "state 3" are made by following the transition of those states. Therefore, if the state transition is not correctly detected, the memory card 20 may mistakenly judge "state 0" and "state 2" or may mistakenly judge "state 1" and "state 3". There is a risk that it will be lost.

For example, when the main data is read as shown in FIG. 4, noise is added to the control signal, and the memory card 20 makes a mistaken determination between "state 1" and "state 3". The command sent from the data processing device 10 to the memory card 20 and the main data read from the memory card 20 may collide on the DT line 33.

Further, as shown in FIG. 4, when the main data is read, if the control signal contains noise and the memory card 20 makes a mistaken decision between "state 0" and "state 2", The busy signal or ready signal that should be output in "state 2" is sent when it is "state 0", or it is sent when the interrupt signal that should be output in "state 0" is "state 2". There is a possibility that it will be.

Further, when the main data is written as shown in FIG. 5, if the control signal is noisy and the memory card 20 makes a mistaken decision between "state 1" and "state 3", The command sent from the data processing device 10 to the memory card 20 and the status signal output from the memory card 20 may collide on the DT line 33. Alternatively, the data processing device 10
There is a possibility that the side of (1) waits for a ready signal from the memory card 20 and the side of the memory card 20 waits for a command from the data processing device 10, and data transmission / reception on the DT line 33 is stopped.

Furthermore, as shown in FIG. 5, when the main data is written, the control signal may be noisy, and the memory card 20 may mistakenly judge "state 0" and "state 2". The main data sent from the data processing device 10 to the memory card 20 and the interrupt signal output from the memory card 20 may collide on the DT line 33.

In order to avoid the above problems, for example, the ready signal is set to a signal in which the change of the signal level is repeated in a predetermined cycle, and the state where no signal is output from the memory card 20 is detected as the busy signal. You can do it like this. Hereinafter, an example in which the ready signal and the busy signal are detected will be specifically described.

In the following description, the memory card 20
An example of reading the main data written in is described with reference to the time chart of FIG. 8 and the flowcharts of FIGS. 9 and 10. Here, FIG. 8 is a time chart at the time of reading the main data written in the memory card 20 similarly to FIG. 4, but in this example, the contents of the busy signal and the ready signal are different from those in the example of FIG. . Also,
FIG. 9 is a flowchart showing the flow of processing on the side of the data processing device 10 when reading out the main data written in the memory card 20, and FIG.
6 is a flowchart showing the flow of processing on the side of the memory card 20 when reading the main data written in 0.

First, the processing on the data processing apparatus 10 side will be described with reference to FIGS. 8 and 9.

When reading main data from the memory card 20, the data processing device 10 first
A read command, which is a command for instructing the reading of the main data from, is written in the register 12. After that, as shown in step S1, the data processing device 10 sets the control signal output from the host-side serial interface circuit 13 to the high level to set it to "state 1" under the control of the host-side controller 14 (time in FIG. 8). t ₅₁ ). Further, in the "state 1", the data processing device 10 reads a read command from the register 12 to the host-side serial interface circuit 13, attaches an error correction code or the like to the read command, and then adds the read command to the DT line. It is sent to the memory card 20 via 33.

When the transmission of the read command is completed, the data processing device 10 sets the control signal output from the host side serial interface circuit 13 to low under the control of the host side controller 14 to "state 2".
(Time t _{52 in} FIG. 8). In this "state 2", the data processing device 10 detects the status signal sent from the memory card 20. And step S2
At, the data processing device 10 determines whether or not a busy signal is detected.

At this time, the host-side serial interface circuit 13 operates when the signal sent through the DT line 33 is a substantially constant signal (hereinafter referred to as a DC signal) with no particular change in signal level. Determines that the DC signal is a busy signal indicating that the memory card 20 is in a state in which the signal input is not accepted. Also,
The signal transmitted via the DT line 33 is a signal (hereinafter, referred to as AC
It is called a signal. In the case of), it is determined that the signal is a ready signal indicating that the memory card 20 is in a signal input waiting state.

At this time, the host side serial interface circuit 13 only determines whether the signal sent through the DT line 33 is a DC signal or an AC signal. Therefore, the host-side serial interface circuit 13 not only detects the signal as a busy signal while the memory card 20 sends a signal of a certain level, but also causes the memory card 20 to stop outputting the signal. Even when the status signal is present, it is determined that the status signal is a busy signal.

If a busy signal is detected in step S2, the process proceeds to step S3. In step S3, the data processing circuit 10 determines whether the busy signal continues for a predetermined time or more. If the busy signal continues for a predetermined time or more, it is considered that a time-out has occurred and the process returns to step S1 and is repeated. That is, when the busy signal continues for a predetermined time or more, the data processing circuit 10 determines that some error has occurred on the memory card 20 side, returns to the "state 1" again, and returns to the read command. Send again.

On the other hand, if the busy signal does not reach the predetermined time, the process returns to step S2 and is repeated. That is, the data processing circuit 10 repeats the processes of steps S2 and S3 until the status signal from the memory card 20 changes from the busy signal to the ready signal.

As will be described later, the memory card 20
Is designed to stop the output of signals when some kind of error occurs. At this time, the signal level of the DT line 33 is maintained low when the immediately previous state is low, because the resistor 33a acting as a so-called pull-down resistor is connected to the DT line 33, and the immediately previous state is high. Sometimes it gradually changes to a low state.
In any case, these states are data processing device 10
Is detected as a DC signal, that is, as a busy signal. That is, when an error occurs on the memory card 20 side, the busy signal is continued. Therefore, when an error occurs on the memory card 20 side, it is possible to detect the occurrence of the error by the determination in steps S2 and S3.

In other words, in the data processing device 10 and the memory card 20, when an error occurs in the memory card 20, the memory card 20 does not send a special signal indicating the occurrence of the error to the data processing device 10. The data processing device 10 is adapted to detect the occurrence of an error.

On the other hand, when the processing of the memory card 20 is completed without any error, and the memory card 20 is ready to receive a signal input from the outside,
The status signal output from the memory card 20 changes from the busy signal to the ready signal (time t _{53 in} FIG. 8).
Here, the ready signal is an AC signal in which the change in signal level is repeated in a predetermined cycle, as described above. The ready signal is preferably a signal whose signal level changes at a frequency equal to or lower than the frequency of the synchronization signal so that the data processing device 10 can detect it promptly and reliably. Specifically, for example, the signal level is such that the signal level is high, low, high, low and inversion at half the frequency of the synchronization signal.

When the busy signal is no longer detected in step S2, that is, when the ready signal is detected, the process proceeds to step S4. In step S4,
The data processing device 10 sets the control signal output from the host-side serial interface circuit 13 to high under the control of the host-side controller 14 to "state 3".
(Time t _{54 in} FIG. 8). In this “state 3”, the data processing device 10 receives the main data read from the memory card 20 by the host side serial interface circuit 13. The main data received by the host-side serial interface circuit 13 is transferred to the data processing unit 11 via the register 12 under the control of the host-side controller 14.

When the reception of the main data read from the memory card 20 is completed, the data processing device 10 sets the control signal output from the host side serial interface circuit 13 to low under the control of the host side controller 14 to the "state". 0 to "(time t ₅₅ in FIG. 8).

Then, in step S5, the data processing device 10 determines whether or not the interrupt signal is detected. Here, the interrupt signal is a signal indicating that the memory card 20 requests some kind of interrupt processing. When the interrupt signal is detected, the process proceeds to step S6 (time t ₅₆ in FIG. 8). In step S6, the data processing device 10 sends the detected interrupt signal to the data processing unit 11, and then in step S1 in order to perform an interrupt process according to the interrupt signal.
Return to and repeat the process.

On the other hand, if no interrupt signal is detected in step S5, the process proceeds to step S7. In step S7, the data processing device 10 determines whether or not there is any processing to be performed on the memory card 20, that is, whether or not there is a command to be sent to the memory card 20. Then, if there is no command to be sent to the memory card 20, the data processing device 10 returns to step S5 and repeats the processing, and if there is a command to be sent to the memory card 20, returns to step S1 and sends the command. Repeat the process. That is, if there is a request for some processing to the memory card 20 before the interrupt signal is generated, for example, a processing request for detecting the internal status of the memory card 20, etc., step S
Returning to 1, the command corresponding to the process is transmitted.

Next, the processing on the side of the memory card 20 will be described with reference to FIGS.

When the data processor 10 reads the main data, the memory card 20 first determines that the control signal output from the host-side serial interface circuit 13 is high in step S11.
In addition, if the current state is “state 1”, the memory card 2
When 0 is recognized, the data transmitted from the host side serial interface circuit 13 via the DT line 33 is received as a command (time t _{51 in} FIG. 8).
When the data transmission from the data processing device 10 is completed, the control signal switches from low to high.

Next, in step S12, it is determined whether or not an error has occurred during the reception of the command in step S11. At this time, the error occurs, for example, when the memory card 20 side recognizes that the state is “state 1”, but the data processing device 10 side recognizes that the state is “state 3”, and the error occurs. This is the case when the received data is not a command.

If an error occurs when the command is received, the process proceeds to step S13, the signal output from the memory card 20 is stopped, and then the process returns to step S11 to wait for the re-input of the command from the data processing device 10. Becomes
That is, the card side serial interface circuit 23
When an error occurs during the reception of a command from the host side serial interface circuit 13, stops the output of the signal and waits for the input of a new command. When the signal output from the memory card 20 is stopped, the data processing device 10 is in the state of detecting the busy signal.

On the other hand, when no error occurs when the command is received, the state is shifted to "state 2" (time t in FIG. 8).
₅₂ ). Then, proceeding to step S14, the memory card 20 performs processing in accordance with the command received at step S11 and determines whether or not preparation for sending the main data to the data processing device 10 is completed. If the preparation is not completed, the process proceeds to step S15, and if the preparation is completed, the process proceeds to step S16.

In step S15, the card side serial interface circuit 23 outputs a busy signal having a constant signal level, and then returns to step S14 to determine whether or not the preparation for sending the main data to the data processing device 10 is completed. Repeat the determination. That is, the card-side serial interface circuit 23 continues to output a busy signal having a constant signal level until the preparation for sending the main data to the data processing device 10 is completed.

When the preparation for sending the main data to the data processing device 10 is completed, the process proceeds to step S16 and step S1.
6, the card side serial interface circuit 2
3 sends a ready signal to the host-side serial interface circuit 13 (time t _{53 in} FIG. 8). Here, the ready signal is, for example, 1/2 of the synchronization signal as described above.
It is a signal of frequency.

When the ready signal is detected by the data processing device 10, the control signal switches from low to high. In other words, it switched to "STATUS 3" to "state 2" (at time t ₅₄ in FIG. 8). When the "state 3" is reached, in step S17, the card-side controller 24 uses the DT line 33 via the card-side serial interface circuit 23 to send the main data instructed to be read by the command received in step S11 to the host side. The signal is sent to the serial interface circuit 13 in synchronization with the synchronizing signal transmitted by the CLK line. When all of this main data is received by the data processing device 10, the control signal switches from high to low.
In other words, it switched to "STATUS 0" to "state 3" (at time t ₅₅ in FIG. 8).

Next, in step S18, the card-side controller 24 determines whether or not there is any interrupt processing request. If there is no request for interrupt processing, the process proceeds to step S19, and if there is a request for interrupt processing, the process proceeds to step S20.

In step S19, the card-side controller 24 determines whether or not the control signal supplied from the host-side serial interface circuit 13 has switched from low to high, that is, from "state 0" to "state 1". Determine whether or not. Then, if the state is switched to "state 1", the process returns to step S11,
The process is repeated from the reception of the command. On the other hand, "state 0"
If so, the process returns to step S18 to repeat the process. In other words, this memory card 20 has steps S18 and S until an interrupt process occurs or the state switches from "state 0" to "state 1".
The process of 19 is repeated.

On the other hand, if it is determined in step S18 that there is a request for interrupt processing, the card side serial interface circuit switches the state from "state 0" to "state 1", as shown in steps S20 and S21. The interrupt signal is output until it is changed. At this time,
When the data processing device 20 detects an interrupt signal, the control signal supplied from the host-side serial interface circuit 13 switches from low to high, and the state switches from "state 0" to "state 1". . When the state is switched from "state 0" to "state 1", the process returns to step S11 and the memory card 2
0 repeats the process from the reception of the command. At this time, a command for performing processing according to the interrupt signal sent in step S20 is received.

As described above, not only the signal output when the memory card 20 is actually performing processing is the busy signal, but also when the signal output from the memory card 20 is not present. By performing the detection, the data transmission process does not proceed while the memory card 20 incorrectly determines the state. Therefore, the data output from the memory card 20 and the data output from the data processing device 10 collide with each other, incorrect data is exchanged between the memory card 20 and the data processing device 10, and the memory card It is possible to prevent the data transmission from being stopped because the data processing device 20 and the data processing device 10 are in a waiting state with each other.

[0147]

According to the data processing system of the present invention, when the external storage device changes from the state of not accepting signal input from the data processing device to the state of waiting for signal input, the signal level is repeatedly changed at a predetermined cycle. When the ready signal is output from the external storage device and the external storage device is performing processing based on the control command data and is not accepting the signal input from the data processing device, the signal level from the external device side serial signal input / output unit is changed. If a constant busy signal is output as the status signal, or if the output of the signal from the external device side serial signal input / output unit is stopped and an error occurs when the external storage device receives the control command data, Since the output of signals from the serial signal input / output unit on the external device side is stopped, when transmitting data to or from an external storage device. , The data output from the external storage device may collide with the data output from the data processing device, incorrect data may be exchanged between the external storage device and the data processing device, It is possible to avoid a situation in which the processing device and the processing device are in a waiting state with each other and data is not transmitted.

Further, in the data transmission method according to the present invention, when the external storage device changes from the state of not accepting a signal input from the data processing device to the state of waiting for signal input, the ready signal is repeatedly changed at a predetermined cycle. When the signal is output from the external storage device and the state of the external storage device is in the state of performing the processing based on the control command data and not accepting the signal input from the data processing device, the external device side serial signal input / output unit When a busy signal with a constant signal level is output as a status signal, or the output of the signal from the serial signal input / output unit on the external device side is stopped and control command data is received by the serial signal input / output unit on the external device side When an error occurs in the external device, the output of the signal from the external device side serial signal input / output unit is stopped. When transmitting data to and from the storage device, the data output from the external storage device may collide with the data output from the data processing device, or an error may occur between the external storage device and the data processing device. It can be avoided that data is exchanged, or that the external storage device and the data processing device are in a waiting state with each other and data is not transmitted.

[Brief description of drawings]

FIG. 1 is a block diagram showing a data processing device according to the present invention and a memory card used in the data processing device.

FIG. 2 is a circuit diagram showing an output circuit of the memory card.

FIG. 3 is a time chart of data transmitted between the data processing device and the memory card.

FIG. 4 is a time chart of data transmitted between the data processing device and the memory card.

FIG. 5 is a time chart of data transmitted between the data processing device and the memory card.

FIG. 6 is a time chart of data transmitted between the data processing device and the memory card.

FIG. 7 is a time chart of data transmitted between the data processing device and the memory card.

FIG. 8 is a time chart of data transmitted between the data processing device and the memory card.

FIG. 9 is a flowchart showing the flow of processing on the data processing device side when reading data from a memory card.

FIG. 10 is a flowchart showing the flow of processing on the memory card side when reading data from the memory card.

FIG. 11 is a block diagram showing a conventional data processing device and a memory card.

FIG. 12 is a time chart of data transmitted between a conventional data processing device and a memory card.

[Explanation of symbols]

10 data processing device, 11 data processing unit, 12
Register, 13 host side serial interface circuit, 14 host side controller, 20 memory card, 21 memory, 22 register, 23 card side serial interface circuit, 24 card side controller, 31 CLK line, 32 control line, 33 DT line

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04L 29/08 H04L 29/10 G06F 3/06 301 G06F 3/08 G06K 17/00

Claims (6)

(57) [Claims] 1. A data processing system for processing data between a data processing device and an external storage device, wherein the data processing device transmits at least control command data for controlling the operation of the external storage device, A host-side serial signal input for receiving a status signal indicating the operation state of the external storage device, transmitting data to be written to the external storage device, and receiving data to be read from the external storage device by serial signals with the external storage device. An output unit, a control signal output unit that supplies a control signal for controlling the timing of switching data transmitted and received by the host-side serial signal input / output unit to the external storage device, and transmission / reception by the host-side serial signal input / output unit Signal output to supply the external data storage device with the data synchronization signal And an external storage device that performs at least the reception of the control command data, the transmission of the status signal, the reception of the data to be written, and the transmission of the data to be read by a serial signal with the data processing device. A serial signal input / output unit on the device side, a control signal input unit for receiving a control signal for controlling the switching timing of data transmitted / received by the serial signal input / output unit on the external device side, and the external device side A synchronization signal input unit for receiving a synchronization signal of data transmitted / received by the serial signal input / output unit from the data processing device, wherein the control signal output unit includes the host side serial signal input / output unit and the external device side serial Control according to the data sent to and received from the signal input / output section The signal level of the signal is set to a predetermined level, and when the external device side serial signal input / output unit changes from the state of not accepting signal input from the data processing device to the signal input waiting state, A ready signal that repeats changes is output as a status signal, and when the external storage device is performing processing based on control command data and is not accepting a signal input from the data processing device, a busy signal with a constant signal level is displayed. A data processing system characterized by outputting as a signal or stopping the output of a signal, and stopping the output of the signal when an error occurs during reception of control command data. 2. The host-side serial signal input / output unit comprises:
When receiving the status signal, when the status signal is a signal in which the signal level changes repeatedly in a predetermined cycle, the status signal indicates that the external storage device is in a signal input waiting state. 2. The data according to claim 1, wherein the status signal is determined to be a busy signal indicating that the external storage device is in a state in which the input of the signal is not accepted, in other cases. Processing system. 3. The serial signal input / output unit on the host side comprises:
2. The data processing system according to claim 1, wherein when the busy signal is continuously received for a predetermined time or longer, it is determined that an error has occurred in the processing in the external storage device. 4. A data transmission method for transmitting data between a data processing device and an external storage device, wherein the data processing device transmits at least control command data for controlling the operation of the external storage device, A host-side serial signal input for receiving a status signal indicating the operation state of the external storage device, transmitting data to be written to the external storage device, and receiving data to be read from the external storage device by serial signals with the external storage device. An output unit, a control signal output unit that supplies a control signal for controlling the timing of switching data transmitted and received by the host-side serial signal input / output unit to the external storage device, and transmission / reception by the host-side serial signal input / output unit And a synchronization signal output section for supplying a synchronization signal of data to the external storage device. The external storage device includes at least an external device side that performs reception of the control command data, transmission of the status signal, reception of data to be written, and transmission of data to be read by a serial signal with the data processing device. A serial signal input / output unit, a control signal input unit that receives a control signal for controlling the timing of switching data transmitted / received by the external device side serial signal input / output unit from the data processing device, and the external device side serial signal A synchronization signal input unit for receiving a synchronization signal of data transmitted / received by the input / output unit from the data processing device, and transmitting / receiving between the host-side serial signal input / output unit and the external device-side serial signal input / output unit The control signal output from the control signal output section according to the data When the signal level of the roll signal is set to a predetermined level and the state of the external storage device is changed from the state of not accepting signal input from the data processing device to the signal input waiting state, the serial signal input / output unit of the external device side is operated. A ready signal that repeats a change in signal level at a predetermined cycle is output as a status signal, and the state of the external storage device is performing processing based on control command data and does not accept signal input from the data processing device. In the case of, the external device side serial signal input / output unit outputs a busy signal with a constant signal level as a status signal, or the output of the external device side serial signal input / output unit is stopped, and the external device When an error occurs when receiving the control command data by the side serial signal input / output unit, Data transmission method, characterized in that stops the output of signals from the Kigaibu device side serial signal input-output unit. 5. The host-side serial signal input / output unit comprises:
When receiving the status signal, when the status signal is a signal in which the signal level changes repeatedly in a predetermined cycle, the status signal indicates that the external storage device is in a signal input waiting state. 5. The data according to claim 4, wherein the status signal is determined to be a busy signal indicating that the external storage device is in a state in which the input of the signal is not accepted, in other cases. Transmission method. 6. When the busy signal is continuously received by the host-side serial signal input / output unit for a predetermined time or more, it is determined that an error has occurred in the processing in the external storage device. The data transmission method according to claim 4.