KR920008604A - Interface circuit between PC and peripheral device - Google Patents

Interface circuit between PC and peripheral device Download PDF

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Publication number
KR920008604A
KR920008604A KR1019900017248A KR900017248A KR920008604A KR 920008604 A KR920008604 A KR 920008604A KR 1019900017248 A KR1019900017248 A KR 1019900017248A KR 900017248 A KR900017248 A KR 900017248A KR 920008604 A KR920008604 A KR 920008604A
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South Korea
Prior art keywords
data
peripheral device
interface
bus
signal
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KR1019900017248A
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Korean (ko)
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KR930001923B1 (en
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김대영
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이헌조
주식회사 금성사
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Priority to KR1019900017248A priority Critical patent/KR930001923B1/en
Publication of KR920008604A publication Critical patent/KR920008604A/en
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

내용 없음No content

Description

피씨와 주변기기간의 인터페이스회로Interface circuit between PC and peripheral device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명 피씨와 주변기기간의 인터페이스회로 적용위치를 보인 블록도.1 is a block diagram showing the application position of the interface circuit between the PC and the peripheral device of the present invention.

제2도는 본 발명 피씨와 주변 기기간의 인터페이스회로.2 is an interface circuit between the present invention PC and the peripheral device.

제3도는 본 발명에서 운용되는 버스 페이즈 신호흐름도.3 is a bus phase signal flow diagram operating in the present invention.

Claims (5)

피씨의 데이타 및 각종 제어신호루프를 제공하는 피씨버스(100)와, 주변기기의 데이타 및 각종제어신호를 받아들이는 주변기기접속기(200)와, 상기 피씨버스(100)및 주변기기 접속기(200)사이에서 버스프리, 선택, 명령, 데이타입력, 상태단계를 통해 그들간의 데이타를 중계하는 인터페이스용 어댑터(300)와, 사용자의 디엠에이채널 세팅을 받아들이는 딥 스위치(120)와, 상기 딥스위치(120)에서 세팅된 값과 입출력 메모리상의 어드레스값을 비교하여 같을 때 상기 인터페이스용 어댑터(300)의 칩 선택신호를 제공하는 비교기(130)와, 상기 주변기기접속기(200)와 인터페이스용 어댑터(300)간의 데이타 흐름을 결정해주는 버퍼(210)와, 데이타 전송의 기준 신호인 요구신호, 인지신호및 핸드쉐이크를 위한 플립플롭(FF1,FF2)으로 구성된 것을 특징으로 하는 피씨와 주변기기간의 인터페이스회로.The bus between the PC bus 100 that provides data and various control signal loops of the PC, the peripheral device connector 200 that receives data and various control signals of the peripheral device, and the bus between the PC bus 100 and the peripheral device connector 200. In the adapter 300 for the interface to relay the data between them through the pre-selection, selection, command, data input, status step, the dip switch 120 to accept the user's DM channel setting, and the dip switch 120 Chip selection signal of the adapter 300 for the interface when the set value and the address value on the input / output memory are the same Comparator 130 for providing a, a buffer 210 for determining the data flow between the peripheral connector 200 and the adapter 300 for the interface, and the request signal which is a reference signal of the data transmission Acknowledgment And a flip-flop (FF1, FF2) for the handshake. 제1항에 있어서, 호스트 피씨의 중앙처리장치는 인터페이스용 어댑터(300)에 식별데이타(ID)를 라이트한 후, 선택 포트를 액티브시켜 그 라이트된 식별데이타(ID)를 주변기기 접속기(200)측으로 송출하고, 주변기기는 현재의 선택 스텝을 감지하고, 상기 인터페이스용 어댑터(300)로 부터 입력된 식별데이타(ID)를 자신의 것과 비교하여 같을 때 비지신호를 송출하며, 상기 호스트 피씨의 중앙처리장치는 그 비지신호를 감지하는 순간 상기 선택포트를 인액티브시키는 과정으로 상기 ‘선택단계’를 수행하는 것을 특징으로 하는 피씨와 주변기기간의 인터페이스회로.According to claim 1, wherein the central processing unit of the host PC writes the identification data (ID) to the adapter 300 for the interface, and then the selection port Activates and transmits the written identification data ID to the peripheral device connector 200, the peripheral device detects the current selection step, and inputs the identification data ID inputted from the interface adapter 300 to its own. Busy signal when compared to The central processing unit of the host PC is busy signal At the moment of detecting the selection port Interface circuit between the PC and the peripheral device, characterized in that for performing the 'selection step' in the process of inactive. 제1항에 있어서, 주변기기는 명령어 단계의 버스제어 신호(M,C/D,I/O)를 출력하고, 호스트 피씨에 대해 명령어 요구신호를 출력하여 호스트 피씨내에 인터럽트가 걸리게하고, 상기 호스트 피씨는 인터럽트가 발생될 때 인터페이스용 어댑터(300)를 통해 버스가 선택단계로 판명되며 그 인터페이스용 어댑터(300)에 소정의 명령어를 라이트하고, 주변기기는 호스트 피씨에게 출력되는 인지신호가 액티브되는 것을 기다 데이타버스상의 명령어를 리드한 후 요구신호를 인액티브시키는 과정으로 상기 ‘명령단계’를 수행하는 것을 특징으로 하는 피씨와 주변기기간의 인터페이스회로.The peripheral device of claim 1, wherein the peripheral device outputs a bus control signal (M, C / D, I / O) of a command step, and requests a command to the host PC. To interrupt the host PC, and when the interrupt is generated, the bus is determined to be selected through the interface adapter 300, and writes a predetermined command to the interface adapter 300, Peripheral device is a recognition signal output to the host PC Request signal after reading the command on the data bus Interface circuit between the PC and the peripheral device, characterized in that to perform the 'command step' in the process of inactive. 제1항에 있어서, 주변기기가 그의 데이타버스상에 소프트웨어 데이타를 싣고, 요구신호를 액티브시킨 후, 호스트 피씨는 인터럽트가 발생될 때 상기 인터페이스용 어댑터(300)에서 데이타를 리드하고 그의 스트로브포트를 인액티브시키며, 상기 주변기기는 인지포트가 액티브될 때 요구신호및 데이타송출을 중단하고, 더 송출할 데이타가 있고 인지포트가인액티브상태이면 요구신호및 데이타를 상기와 같이 송출하는 과정으로 상기 ‘데이타입력 단계’를 수행하는 것을 특징으로 하는 피씨와 주변기기간의 인터페이스회로.2. A peripheral device according to claim 1, wherein the peripheral device carries software data on its data bus and requests signal. After activating, the host PC reads data from the adapter 300 for the interface when an interrupt is generated and its strobe port. Inactive to the peripheral device is a recognition port Signal when is activated And stop sending data, and have more data to send Request signal if inactive state And performing the 'data input step' in the process of transmitting data as described above. 제1항에 있어서, 호스트 피씨는 인터페이스용 어댑터(300)를 디스에이블시키는 동시에 디엠에이 제어기를 인에이블시키고, 주변기기는 데이타요구포트(DRQ)가 액티브되는 시점에서 데이타를 버스상에 싣고 요구포트를 액티브시키며, 상기 디엠에이 제어기는 데이타요구신호(DRQ)가 액티브된 시점에서 데이타인지포트를 액티브시키고, 데이타 버스상의 데이타를 피씨의 메모리에 저장시키며, 디엠에이에 의해 데이타 인지신호가 인액티브되면 주변기기가 데이타의 송출을 중지하는 과정으로 상기 ‘데이타입력단계’를 수행하는 것을 특징으로 하는 피씨와 주변기기간의 인터페이스회로.2. The host PC of claim 1, wherein the host PC disables the adapter 300 for the interface and at the same time enables the DM controller, and the peripheral device loads data on the bus at the time the data request port DRQ is activated. The MD controller activates the data recognition port at the time when the data request signal DRQ is activated. Is activated, the data on the data bus is stored in the PC's memory, and the data acknowledgment signal is When is inactive, the peripheral device performs a 'data input step' in the process of stopping the transmission of data, the interface circuit between the PC and the peripheral device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900017248A 1990-10-26 1990-10-26 Interface circuit between pc and its other device KR930001923B1 (en)

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KR1019900017248A KR930001923B1 (en) 1990-10-26 1990-10-26 Interface circuit between pc and its other device

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Application Number Priority Date Filing Date Title
KR1019900017248A KR930001923B1 (en) 1990-10-26 1990-10-26 Interface circuit between pc and its other device

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KR920008604A true KR920008604A (en) 1992-05-28
KR930001923B1 KR930001923B1 (en) 1993-03-20

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100221080B1 (en) * 1994-12-08 1999-09-15 정몽규 Apparatus and method for transforming communication speed
KR102289170B1 (en) 2021-02-15 2021-08-12 김진일 Sink faucet to drain ice and water

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100221080B1 (en) * 1994-12-08 1999-09-15 정몽규 Apparatus and method for transforming communication speed
KR102289170B1 (en) 2021-02-15 2021-08-12 김진일 Sink faucet to drain ice and water

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Publication number Publication date
KR930001923B1 (en) 1993-03-20

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