JPS5818727A - Method and apparatus for self-control of dispersion type priority competition - Google Patents

Abstract

PURPOSE:To precisely synchronize respective devices with simple configuration without providing a specific priority controlling device. CONSTITUTION:A counter 120 is connected to a busy line 100 at its reset terminal and also connected to a pull-up power source through a resistor R1. An output of the counter 120 is inputted to a comparator 121, which generates an output Tc when the input coincides with a set value Cs. The output of the comparator 121 is inputted to the set terminal of a FF122. A using request Sreg is supplied to the reset terminal of the FF122. The Sreg is also supplied to an AND gate 123. The output terminal of the AND gate 123 is connected to the base of a transistor 124 and a gate of a data buffer 125 and the collector and emitter of the TR124 short-circuits the busy line 100. The output terminal of the comparator 121 is connected to a FF131 and an AND gate 132 and an output of the AND gate 132 controls a TR130, preventing an I/O10, which is a common source, from erroneous measurement when the I/O10 is made unexclusive for a period beyond a prescribed time.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a self-control method and apparatus for distributed two-type priority competition, and more particularly to a distributed priority competition in which a shared device that can be used by a plurality of devices is used as necessary by the plurality of devices. The present invention relates to a self-control method and device.

Generally, a plurality of devices may be connected to a shared path line, and information may be transmitted between the devices via the shared path line. In addition, there are devices that are shared by multiple devices, and each of the multiple devices is connected independently, and the shared devices cannot be used at the same time. Unless some kind of priority control is performed, conflicts may occur. Problems arise and confusion arises. Therefore, a shared device like the one above (
When using these types of resources (hereinafter referred to as shared resources), it is necessary to perform some kind of priority control. Conventionally, the following methods have been used to solve this problem.

The first method is to provide a priority control device that controls usage requests from multiple devices. This device accepts usage requests from multiple devices and grants permission to use shared resources to various devices according to predetermined priorities.

According to this device, a priority control device is required, a redundant signal line is required for accepting requests, returning permission signals, etc., and furthermore, when an abnormality occurs in the priority control device, the multiple devices It had its drawbacks, such as affecting everything in the world.

Another example is disclosed in Japanese Patent Publication No. 55-29459. This conventional example is a system that does not provide a centralized priority control device as described above.

In other words, contention control is distributed and the right to use resources is passed to round tropins, which requires a reset signal line, a mask signal line, etc. for the priority storage element.
This corresponds to the so-called Deci-chain method. However, there is a drawback that if a part of the chain is removed or breaks down, priority control of subsequent devices becomes impossible.

In addition, as this type of technology, Japanese Patent Application Laid-Open No. 54-81734
This was proposed based on the system disclosed in the above publication, and it has a simple configuration without the need for a special priority control device, can flexibly cope with changes in system configuration, and can be used as a shared resource. An object of the present invention is to provide a self-control method and apparatus for distributed priority competition, which enables synchronization even if a non-exclusive state continues for a predetermined period of time.

In the present invention, in each device that shares one resource, it is determined whether the shared resource is currently being used by any device, and the time when the shared resource is no longer used or the predicted time when it will be no longer used is determined. When the elapsed time is equal to each different unique time set for each device, if the device requests the use of the shared resource, the right to use the shared resource is granted. and enable the use of shared resources, as well as ensuring that the shared resources are predetermined.

In order to eliminate the accumulation of errors in the means for measuring the elapsed time, the shared resource is temporarily brought into an exclusive state when the shared resource becomes unexclusive for a period of time exceeding .

Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In this figure, a shared device (hereinafter referred to as 10) 10 as a shared resource is connected to a plurality of devices (in this embodiment, a computer (hereinafter referred to as CPU) via a shared bus 101.
) is connected to 11y13. Further, each of the CPUs 11 to 13 mutually monitors the usage status of the shared bus 101 via the busy line 100. In this embodiment, the G-line 100 is treated as being in a short-circuited state, indicating that the shared bus 101 is in use, and in an open state, indicating that the shared bus 101 is not in use.

Hereinafter, how each CPU II to 13 obtains the right to use the shared bus 101 will be explained based on FIG. 2.

FIG. 2 is a block diagram showing a portion of the shared bus 101 usage right control circuit of each CPUI 1 to 13 according to the present invention.

In this figure, the shared bus right control circuit has the following configuration. That is, the counter 120 has its reset terminal connected to the busy line 100, connected to a pull-up power supply via a resistor R3, and connected to its clock terminal so as to input the clock CLK pulse, and Color/Re120 count output to comparator 1
It is connected to one input end of 21. This comparator 121
A set value Cs is supplied to the other input terminal of the comparator 121, and this comparator 121 has a count output and a set value Cs.
The output signal Ta is output when the values s and s match. The output terminal of this comparator 121 is connected to a set terminal of a flip-flop 122. The reset input terminal of this solve flop 122 has a usage request 8.
rsq is supplied, and this usage request S1. , are supplied to the other input terminal of the AND gate 123. Logical product game) 1. ．． 23
The output terminal of is connected to the gate terminal of the transistor 124 and to the gate terminal of the data buffer 125. Further, the collector and emitter of the transistor 124 are configured to short-circuit the busy line 100.

On the other hand, when the l1010 as a shared resource becomes non-exclusive for more than a predetermined period of time, measurement errors are accumulated in the means for measuring the elapsed time (in particular, the counter 120). The means are constructed as follows. That is, the comparator 121 has its output terminal connected to the trigger input terminal of the flip-flop 131 and also to one input terminal of the AND gate 132. The reset terminal of this flip-flop 131 is connected to the busy line 100, and the reset terminal of this flip-flop 131 is connected to the busy line 100.
The output terminal of is connected to the other input terminal of AND gate 132. The output terminal of the AND gate 132 is connected to the base of the transistor 130, and the collector and emitter of the transistor 130 are connected to the busy line 100.

The operation of the device configured in this way will be explained below.

Clock pulses are input to a counter 120 that cyclically counts pulses of the clock CLK.

This counter 120 is in a reset state when the busy line 100 is in a short state (hereinafter referred to as @L"), and is in a reset state when the busy line 100 is in an open state (hereinafter referred to as at H").
When it reaches (represented by jj J), counting starts. In other words, the busy line 100 is connected from It L 71 to “Hjj
When any CPU 6 finishes using the shared bus 101, the counter 120 in each CPU 11 to 13 changes to
starts counting at the same time.

The output of the counter 120 is input to the comparator 121, and each C
It is compared with a set value Cs that is set to a different value for each PU, and only when they match, an output signal Tc is generated, and the flip-flop 122 is triggered by the output signal Tc.

When flip-flop 122 is triggered, if use request S10. Otherwise, the flip-flop 122 remains reset and has no effect on the shared node 101 or the busy line lOO.On the other hand, when the flip-flop 122 is triggered, if the use request (S
,. , ), flip-flop 122 is set and produces an output signal. Then, under the condition that there is a use request and the flip-flop 122 is on, the AND gate 1
23 is turned on and transmits transmission data via the output gate 125 using the bus 101. It starts occupying the bus 101 and puts the busy line 100 in the "L#" state.

Setting the busy line 100 to the 'L' state in this manner can be achieved by turning on the transistor circuit 124 as shown in FIG.

In this state, the counters 120 of all CPUs (devices) are reset, and the counters 120 of all CPUs (devices) are reset.
(12.13 if the CPU in question is 11) is the bus 101
becomes unusable.

The CPU that has obtained the right to use the shared bus 101 releases its permission to use the shared bus 101 after completing a series of data transmission processes. The output gate 125 for the shared bus 101 is released, and at the same time, the busy line 100 is placed in the ``H'' state.

Thereafter, the counter 120 in each CPU starts counting from the initial state and repeats the above operation.

Next, the operation of the synchronization signal forming means for preventing the measurement errors of the means for measuring the measurement time from being accumulated will be explained.

That is, the purpose of the portion described here is to prevent out-of-synchronization of the counters of each device (CPU).

When a shared resource is frequently used, the counter 120 of each CPU is reset and synchronized each time it is used. However, if the shared resource remains unused for a long time, the clock error of each CPU will increase. Accumulation occurs, causing the counter to become out of synchronization. In FIG. 2, the fact that the set value and the output of the counter 120 match is stored in the flip-flop 131, and the busy line 100 is
If the flip-flop 131 continues to count without being reset with Hν' and the second coincidence output of the comparator 121 is output, the AND of the memory contents of the flip-flop 131 and the coincidence output of the comparator 121 becomes logical. Product gate 13
2 to the transistor 130, momentarily bringing the pidgey line 100 to the at L'''' state.
By setting all the count values of the shared resource using devices connected to the busy line 100 to the initial state, synchronization can be achieved.

FIG. 3 is a time chart showing the operation of the synchronization signal forming means. A more detailed explanation will be given with reference to this figure.

First, the output signal of the comparator 121 is output as shown in FIG. At the trailing edge 140 of this output signal, flip-flop 131 is inverted and rises as shown.

When there is no request to use the shared resource from any CPU, the counter 120 continues counting, so when the output of the counter 120 matches the set value C8 of the comparator 121, the second An output signal 141 will be output. □Then, any device (CPU
), the state signal #142 in which shared resources are not used and the output signal 141 are ANDed at the AND gate 132, and the AND signal 143 is output to the transistor 130.
supplied to the base of Therefore, the transistor 130 is turned on, and the busy line 100 receives the busy signal (
"L") 144 will be output.

Further, although this function is provided in each device, in reality, the device with the highest priority needs to output the busy signal 144. The reason for this is that when one device issues the busy signal 144, the flip-flops 131 of all devices are set on IJ. It should be noted that the flip-flop 131 and the comparator 121 go to the °L" level due to the busy signal 144 (145).

FIG. 4 is a time chart for explaining the operation when the method according to the present invention is not used, and FIG. 5 is a time chart for explaining the operation when the method according to the present invention is used. be.

As shown in FIG. 4, shared bus 101. Alternatively, from the time t□ when a shared resource such as l1010 is no longer used, each color/li 120 provided in each CPU starts counting.
U (Here, the 11th CPU and the 4th CPU
Pay attention to. ) is counting the time that the device is available for use on each unique clock pulse, the errors in the counters 120 of each CPU's shared resource will accumulate and eventually result in the transmission from multiple CPUs. occur simultaneously. This state is shown at t in the figure. On the other hand, according to the embodiment of the present invention as shown in FIG.
When the counter 120 has fully counted (in other words, when no shared resource is used by any CPU)
CPU with the highest priority (here, the first CPU
However, since the signal tIlis tmls 'Ml is output, the errors in the counters of each device are corrected at this point, and synchronization is achieved. As a result, it can be seen that it is possible to avoid the simultaneous use of shared resources by a plurality of devices as in the past, and it is possible to reliably transfer and receive information signals even in a system with a slow usage cycle.

Next, we will explain the operation when using a shared resource using the time chart shown in FIG. . In Figure 6, the setting value Cs assigned to each CPU
, CPU 11 is It 11), and at time 160, CPU II and CPU 13 are requesting use 151 and 15.
He rolled a 4. At this point, the CPU II, whose set value is 1, acquires the right to use the bus, immediately sends a busy signal 150 to the busy line, and uses the bus.

This resets the counter and its state is
This continues until II finishes using the bus.

When the CPU II finishes using the bus (152), the busy line is released and the counter starts counting again.

Here, the use request 154 from the CPU 13 is accepted at the time 161 when the color/value becomes '3'', and the CPU 13 performs the predetermined operation as described above. 157 is accepted at the time 162 when the path usage 155 of the CPUI 3 is completed and the counter value becomes '2'. At 154, the CPU 13 terminates the use of the bus (155) and releases the request, and at the same time releases the busy line (153). Furthermore, the usage request 157 is canceled in the same way, and Busy Lie/ is also canceled (15
6) Do.

Next, when the busy line Φ) is released (156), C
The counters of PU11 to PU13 start counting. Here, since the CPU 11 is assumed to have the highest priority, the counter 120 continues counting. When the count value of the counter 120 reaches "°1", a pulse is output from the comparator 121 as described above, but since no use request is output from any of the CPUs 11 to 13, the counter 120 is not reset and the pulse is output from the comparator 121 as described above. Continue counting as shown in Figure 6. As mentioned above, this counter 120 is cyclic, so if it is set to return to the original state at ``4'', it will return to ``0'' at count value 64'' and start counting again. Then, when the counter 120 outputs the count value °゛1'' again, the comparator 1
A pulse is output from 21, and the busy line 100 becomes 1L" level (200) through the operation shown in FIG. 3. In other words, as shown in FIG.
), the signal 159 is output and the signal 159 is released. Because it operates in this manner, for example, when the long-term shared resource is in a non-exclusive state, a signal is periodically sent to the busy line 100 at predetermined intervals (t1+) as shown in FIG.
By outputting to ``I+ '・3....),
Each CPUI 1 to 13 is temporarily in an exclusive state and synchronization is forcibly established.

In this embodiment, the busy line is released after the use of the shared resource is completed, but this is intended to simplify the hardware. If it is desired to further improve throughput, it is desirable to adopt a method in which the busy line is released within a certain period of time before the end of use of the shared resource. However, in this case, it is necessary to set the above-mentioned certain period of time to ensure that at the time one device starts using the shared resource, other devices have finished using the shared resource.

This is done in order to increase the efficiency of shared resource use by predicting the end time in advance and starting counting on the counter, so that the device that has issued the usage request can use the shared resource as soon as possible following the end. It is. Such an embodiment is shown in FIG.

FIG. 7 is a block diagram showing another embodiment according to the present invention. In FIG. 7, the same components as those in the embodiment shown in FIG. 2 are given the same reference numerals and their explanations will be omitted. The embodiment shown in FIG. 7 differs from the embodiment shown in FIG.
The only difference is that the output signal of 26 and the pulse of the clock CLK are inputted via an OR gate 127, and the other components are unchanged.

The operation of the embodiment configured as described above will be explained with reference to FIG. That is, FIG. 8 is a time chart of the embodiment shown in FIG. Here, a system is assumed in advance in which transmission data lengths 170, 171, 172°, 173, . . . are equal. In this case, in the embodiment shown in FIG.
The counter 120 starts counting at the times 180, 181, when the busy line 100 reaches the "H" level.
182, but since the transmission data length is fixed, the output of the monostable multivibrator 126 in FIG.
The time period during which the data remains at H''' level is made slightly shorter than the transmission data length, and the counter 120 starts counting at 190, 191, 192, . . . to improve transmission efficiency.

FIG. 9 is a block diagram showing still another embodiment of the present invention. The difference from the embodiment shown in FIG. 1 is that the devices 21 to 23 in FIG. 5 are not CPUs but transmission devices, and the transmission line 200 also serves as a busy line. In this embodiment, each of the transmission devices 21 to 23 can perform transmission and reception, and in particular, by adopting the present invention for control of transmission rights, the configuration is simple and only requires a controller.

FIG. 10 shows details of the transmission right control circuit inside the transmission devices 21 to 23 in FIG. 9. In FIG. 6, reference numeral 220 is a counter, 221 is a comparator, and 2
22 is a flip-flop, 223 is an AND gate, 22
4 is a transmitter, 225 is a receiver, 226 is a monostable multivibrator, 230 is an AND circuit, 231 is a flip-flop, and T is a transformer. Further, to explain its configuration in detail, each transmission device includes the following components. That is, the means for determining the signal on the transmission path (transmission line) 200 is a monostable multivibrator into which the received data from the receiving section 225 is input.

226 corresponds to this, and the presence or absence of a pulse on the transmission line 200 is thereby determined.

When it is determined by the means that there is no pulse on the transmission line 200, the counter 220 measures the clock pulse from that point on to measure the elapsed time. That is, this counter 220 functions as a means for measuring elapsed time. Further, when the measured time coincides with the set time set for each device and there is a transmission request for the device, means for putting the device into the transmitting state include a comparator 2211, a flip-flop 222, and an AND gate 223. It consists of Further, the synchronization signal forming means includes an AND gate 230 and a flip-flop 231, and if the measured time by the means for measuring the elapsed time matches the set time and there is no transmission request to the device, The configuration is configured such that the state is stored until a signal on the transmission path is detected, and when the measured time matches the set time and the state is stored, a transmission signal as a synchronization signal is sent out on the transmission path. has been done.

The operation of the device configured in this way will be explained.

Transmission to the transmission line 200 is performed by transmitting units 224 and 230.
The reception is performed via the receiving section 225. If data is currently being sent from any transmission device to the transmission line 200, the monostable multivibrator 2
26 is set and counter 220 is reset.

Here, the purpose of the monostable multivibrator 226 is to determine the presence or absence of a pulse on the transmission line 200, and to
The purpose is to create a direct current signal that indicates whether or not 00 is being used. Therefore, the output of this monostable multivibrator 226 performs the same function as the busy line signal in FIG. That is, when one transmission is completed, the output of the monostable multivibrator 226 disappears, the counter 220 starts counting, and the transmission from the transmitter 224 is controlled in the same manner as described in the previous embodiment.

In this embodiment, the transmission rights of multiple transmission devices can be controlled without special control lines or controllers, which not only reduces costs, but also enables the addition or reduction of transmission devices while online. This can be easily achieved by simply connecting and disconnecting the transmission device.

By the way, in this embodiment, the transmission line 200 is insulated via the transformer T, but this is irrelevant to the present invention, and the presence or absence of insulation of the transmission line 200, and the presence or absence of the transmission line 200 ( It is clear that the present invention can be implemented regardless of whether the device is wired or wireless.

Furthermore, in this embodiment, a monostable multi-byte break is used to determine the presence or absence of a pulse on the transmission line and to detect whether or not the transmission line 200 is being used, but this function uses a counter, shift register, etc. Needless to say, it can be achieved by using Furthermore, it goes without saying that this function is unnecessary if the transmission signal pulse interval is shorter than the clock interval input to the counter 120.

Further, in FIGS. 2 and 10, in order to perform the operation more stably, it is desirable to provide time delay elements 128, 129, 227° 228, as shown in FIG. 11(a), Φ), for example. The operation time chart at that time is the first
Examples of diagram O are shown in FIGS. 12(a) to (h). As is clear from this, the transmitter 224 or the AND gate 2
The transmission signal from 30 will not go around via the receiving section 225 and cause the operation to become unstable.

For example, 1. Assume that a use request 5req is issued. Assuming that the setting of this device is Cs, at t, the value matches the counter value, the comparator 221 is turned on, and the flip-flop 222 is set. Transmission begins when the TD output signal turns on after a certain time delay. The monostable multivibrator 226 remains on from t.

Comparator 221 turns off at t. When the transmission is now completed, 8Hq is released at t, the flip-flop is reset, and the output of TD is also turned off at t6.

Furthermore, according to the present invention, a device with a low priority level may not be given an opportunity to transmit for any length of time. However, if a method is adopted in which the device that has sent the data twice changes its settings and sequentially shifts the priority level, no matter which device is used, the shared resources can be used at least once every predetermined period. will be given the opportunity to This is particularly effective when there is no fixed priority level and resources are to be made available on average.

As described above, according to the present invention, it is possible to perform priority control of the use of shared resources by several distributed devices in a distributed manner, thereby simplifying the system. Furthermore, system changes can be dealt with flexibly, and synchronization between devices can be ensured.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a system configuration of an embodiment in which the present invention is adopted for shared bus right control between multiple CPUs, FIG. 2 is a block diagram showing a control circuit configuration according to the present invention in FIG. 1, and FIG. 3 is a time chart shown to explain the operation of the synchronizing signal forming means in FIG. 2, FIG. 4 is a time chart shown to explain the operation of the counter when the embodiment of the present invention is not adopted, and FIG. The figure is a time chart shown to explain the operation when an embodiment of the present invention is adopted, FIG. 6 is a time chart showing the transition of bus usage rights in FIG. 1, and FIG. 7 is a time chart showing another embodiment of the present invention. A block diagram showing an example, FIG. 8 is a time chart shown to explain the operation of FIG. 7, and FIG. 9 is a block diagram showing a system configuration of an embodiment in which the present invention is adopted for controlling transmission rights of multiple transmission devices. 10 is a block diagram showing the control circuit configuration according to the present invention in FIG. 9, FIG. 11 is a block diagram showing an example of the wraparound prevention circuit, and FIG. 12 is a timing diagram of the operation in FIGS. 10 and 11. It is a chart. 120...Counter, 101...Shared bus, 121
... Comparator, 122 ... Flip-flop, 123
...AND gate, 130...Transistor, 13
1... Flip-flop, 132,230... AND gate, 3I211 /44- Vine 4 figure ``f, ml'' is Saka 2 Figure 5

Claims (1)

[Scope of Claims] 1. In a system in which a plurality of devices each have a shared resource that can be used and the shared resource is used by the plurality of devices as needed, the resource is no longer used by any of the plurality of devices. The elapsed time from the point in time is measured in each of the plurality of devices, and when the measured elapsed time matches a time uniquely set in advance for each of the plurality of devices and the device has a request to use the shared resource, the Self-control of distributed priority contention, characterized in that when a device dedicates the shared resource and the shared resource becomes non-exclusive for a predetermined period of time, the shared resource is temporarily brought into an exclusive state. Method. 2. In claim 1, the method predicts a time when any of the plurality of devices will use the shared resource, and predicts a time when none of the plurality of devices will use the shared resource. A self-control method for distributed priority competition, characterized in that the method starts measuring the elapsed time. 3. In each transmission device connected to the shared transmission path, means for determining the presence or absence of a signal on the transmission path, and measurement means for measuring the elapsed time after the signal on the transmission path disappears;
means for setting the device in a transmitting state when the measured time matches a set time set for each device and there is a transmission request to the device; If there is no transmission request, the state is stored until a signal on the transmission path is detected, and if the measured time matches the set time and the state is stored,
A self-control device for distributed priority competition, which includes synchronization signal forming means for sending a transmission signal as a synchronization signal onto a transmission path.