JPS63310241A - Communication system by common transmission line - Google Patents

Abstract

PURPOSE:To surely give and receive the right of transmission, and to improve an overall communication speed, and also, the reliability as a whole, by providing a self-sequence timer to which each different set time for determining its own transmission right obtaining rank has been set, on each communication equipment. CONSTITUTION:Transmission and reception of a data in control units 11-1n a gateway 7 and an operation indicator 8 connected to transmission lines 31, 32 through them, etc., are executed in accordance with a fact that one of these apparatuses obtains the right of transmission and executes transmission. Also, when they are equal communication equipments (STA), a no-signal time monitoring silent timer (self-sequence timer) provided on each STA1-STAn is started simultaneously in accordance with turn-on of a power source or a no-signal state, etc. In this case, to the timer, a set time being different at every STA is determined separately, therefore, the STA having that which becomes time-up first obtains successively the right of transmission. In such a way, the right of transmission can be given and received surely by a simple constitution, an overall communication speed is improved, and also, the reliability as a whole can be improved.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a communication method applied when a plurality of communication devices connected by a common transmission path transmit and receive data signals via the transmission path. It is related to.

[Conventional technology]

Such a communication method is also called a common bus method, and for example,
There are some methods proposed in Japanese Patent Application Nos. 59-211215 and 211216, etc., and in general, a control is established based on the control established by specifying the control of each communication device connected to a common transmission path. 9 methods in which each communication device transmits alternately, or a signal called a token indicating the grant of the transmission right is sent and received, and only the communication device that has acquired the transmission privilege transmits. has been adopted.

[Problem that the invention seeks to solve]

However, in the system that determines what has four master rights, this is necessary and special equipment must be installed, which is expensive, and if 'RWk occurs in this equipment, the entire communication becomes impossible and reliability is low. In the case of a system in which tokens are exchanged, it takes time, the overall level of trust is low), and the token exchange procedure becomes troublesome.

[Means for solving problems]

In order to solve the above-mentioned problem, the present invention is constructed by the following means.

In other words, a plurality of communication devices are provided that are connected to a common transmission path, each of these communication devices acquires transmission rights alternately, and the communication device that has acquired this transmission right transmits data via the common transmission path. In the communication method used, each communication device is provided with a self-sequence timer with a different set time to determine the order in which it acquires the right to transmit. All of these timers are started at the same time, and the communication device that has the one that times up first among these sequential timers acquires the transmission right.

[Effect]

Therefore, if there is no signal on the transmission path, the self-sequential timers of each communication device will start at the same time.Since these timers each have different set times, the self-sequential timer that was first time-amplified will start at the same time. The communication device that owns the transmission right automatically acquires the transmission right.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to figures showing examples.

FIG. 2 is a block diagram showing the configuration of the control device, which includes a control unit (hereinafter referred to as BCT) 11 which mainly consists of a microcomputer (hereinafter referred to as MCP) and memory, and a plurality of analog inputs AI, analog outputs AO 1, and the like. or
Input/output crab unit (hereinafter referred to as 10U) 21 to 2 having each circuit corresponding to digital input DI and digital output Do
n are connected by bus 111, BCTlt and l0
By exchanging data with U2+~2n, p1 each input AI,
The MCP in t-BcT11 performs control calculations corresponding to DI, and the results thereof are sent out as respective outputs AO and DO through fIO021 to fIO2nt-, thereby performing local control of air conditioning equipment, etc., which are omitted in the figure.

In addition, multiple BCTs 12 to 1m having similar IOUs are connected by a common transmission path 31, and transmit and receive data between each other. unit (hereinafter referred to as RE
p) 4t- connected via BCT11~1m and B
After CT1m, data is transmitted and received between each other. On the other hand, there is a main data transmission path 6 from the main control device (hereinafter referred to as MCT) 5 of a large computer etc. to each part.
A transmission line 31 is connected to the MCT 5 and BCTI 1 to 1n through a gateway (hereinafter referred to as GW) 7t having relay and time schedule control functions.
Even if the data transmission speed is A, the GW7 will relay the data mutually, and the main data transmission line 6 will be connected to the MCT5t.
If commands from MCT5 cannot be received due to a failure, GW7 will take over functions such as time schedule control,
This does not cause any hindrance to the control operations of the BCTs 1s to 1n, etc.

Therefore, BCT11 to In etc. perform local control based on the basic control data given from MCT5 and send this status to MCT5, and MCT5 sets and changes the overall control status. On the other hand, data transmission and reception with MCT5 became impossible (in response to instructions from GW7, BC
Since T11 to 1n etc. perform local control, general loss of control does not occur.

In addition, a hand-held operation display device (hereinafter referred to as HMMI) 8 can be freely connected and attached to BCT11 to 1n, GW7, etc., and if υHMMI8 is connected to the connector, a transmission line of 3 seconds will be connected via the internal circuit. , connected to 3 snow,
By sending and receiving data with any unit via this,
It is possible to set and change commands, data, and monitor the operating status of BCTll to In, etc. and GW7.

Figure 3 is a front view of HMMI8, for example 97x1
Each circuit including the MCP is housed in a hand-held housing 51 of 80-, and on the upper surface there is a liquid crystal display 52 that displays multi-digit characters, symbols, etc., and a light-emitting diode, etc. A display unit 54 is provided with a plurality of indicator lights 53, below which a keyboard 55 including a numeric keypad and various function keys is arranged, and on the lower side of the housing 51, a memory such as an IC card is provided. Insertion of the card 56 [Insertion of the memory card 56 provided with the card 57 and on which programs, data, etc. are written.

It can be removed freely.

A curl cord 58 is led out from the left side of the housing 51, and a connector 59 connected to the tip of the cord connects the B
The connection to the CTl or GW7, etc. can be made detachable, and a hook-shaped metal fitting or the like is provided on the back of the two bodies 51, so that it can be attached to the surface of the case of the BCTl or GW7, etc.

FIG. 4 is a block diagram of the BCTl, which includes an MCP 71 as the center, variable memory (RAM) 72, programmable read-only memory (FROM) 73, and electrical eraser memory (FROM) 73.
A variable write memory (hereinafter referred to as EEPROM) 74 using a programmable read-only memory and an input/output circuit (hereinafter referred to as
l10) T5, indicator light using multiple light emitting diodes, etc.
It is arranged around the interface (hereinafter referred to as PL) 14 and the interface (hereinafter referred to as
)59 is connected to CN78 and I/F77 and MCP
71 is connected to a selection circuit (hereinafter referred to as 5) using various gates.
EL) 79, while I/F'77
is connected to the data transmission path 3 via a terminal or the like.

Here, the processor (hereinafter, cp
ty) executes the instructions in the ROM built in PROM73 and MCP71, and
Control operations are performed while accessing the necessary data to 74, I/F77 and 5EL79.
In response to received data RD via Ilo 35 and input data via Ilo 35, PROM 73. Performs control calculations based on basic control data stored in the EEPROM 74,
Also, it makes control decisions according to the time schedule from GW7, and as a result, '1sEL79 and I/
F77t'' and sent as output data via l1075't-, and these situations
4 is turned on to display them sequentially.

That is, the MCP 71 always keeps the transmission output TDrn at the logical value "1" and repeats "1" and similar 1゛0 according to the transmission of the transmission data, while the reception data RD from the I/F 77 also keeps the logical value "1". 9.
When HMMI8 is not connected to CN78, terminal L/
G is "0", OR gates 79a + 79b are on, AND gate) 79c and 79d are also resistors R
It is turned on by applying the power supply VD through the
Reception data RD from I/F 77 is given to reception power RDm of MCP 71 via OR gate 79a and AND gate 79ct-, and transmission output TD of MCP 71
The level change from m is applied to the I/F 77 as transmission data TD via an AND gate 79d and an OR gate 79b, whereby data transmission/reception via the data transmission path 3 is performed.

Furthermore, when the HMMI 8 is connected to the CN 78, depending on the setting of the general mode "G" which performs data transmission and reception with all devices connected by the data transmission path 3, or the local mode rLJ which performs data transmission and reception only with the MCP 71, C
HMMI8 gives "0" to terminal L/G of N78 in rGJ mode and "1" in "L" mode, so if it is in "G" mode, it is the same as above (OR game) 7
9a, 79b and AND gates 79c, 79
d are in the on state, and the transmitting terminal TDh of CN78 and the receiving power RDm of MCP71 and I/F77 are connected via AND gate 79c, AND gate 79d and OR gate 79ck, and CN7
An AND gate 79e and an OR gate are also connected between the receiving terminal RDh of 8 and the transmitting output TDm of MCP71 and I/F77.
It is connected through gates 79a and 79f, and transmission data from HMMI8 is transmitted to data transmission line 3 via I/F77, and is also given to MCP71 at the same time.
The received data RD via 7t and the transmitted data from the MCP 71 can be simultaneously received at the HMMI 8, and the HMMI 8 can freely transmit and receive data to and from all devices connected to the data transmission path 3 and the MCP 71.

Note that at this time, MCPT1 is also connected to the I/F 77, and data transmission and reception using the data transmission path 3 is performed in the same way as when HMMt& is not connected.

Regarding the above, depending on the "L" mode setting, the terminal r L/
If "1" is given to GJ, OR gate 79a e
Since each output of 79b is fixed to "1" and these are in the off state, CN7B and MCPTl and I/F77
While the data transmission line 3 via the AN
D game) 79c to 79d remain on, and C
Only N78 and McP71 are connected, and the transmission data from the transmission terminal TDh of CN7B is ANDed.
It is applied to the receiving power RDm of MCPTl via the gate 79c, and the transmission data from the transmission output TDm of MCPTl is applied to the receiving terminal RDh of CN7B via the AND gate 79e, so that data is transmitted and received only between HMMI8 and MCPTl. will be carried out.

Note that GW7 has almost the same configuration as in Figure 4, and has the same connector as CN7B and the same circuit as 5EL79, and can perform the same operation by connecting )1MMI8. It has become.

Therefore, if HMMI8 is connected to BCTl or GW7, in "G" mode, data can be sent and received with other devices via the data transmission path 3t according to the operation of HMMI8, while data can be exchanged with BCTl or GW7. Since it is possible to send and receive freely, BC can be sent and received by operating HMMI8.
Setting data for Tl, GW7 and other equipment,
Changes, monitoring of operating conditions, etc. can be made as necessary.

Also, depending on the "L" mode setting, the data transmission line 3
Since data is transmitted and received only with the device connected to the HMMI 8, regardless of the HMMI 8, large-capacity data transfer can be carried out arbitrarily for a long time without affecting other devices.

Figure 5 is a block diagram of HMMI8, and MCP9.
1, and RAM92. PROM 93, card reading/writing circuit (hereinafter referred to as CRW) s 5, keyboard (hereinafter referred to as KB) 55, display section (hereinafter referred to as DP) 54, and
An I/F 96 having a data signal transmission/reception function is arranged around the periphery, and is connected to each other, as well as between the I/F 96 and CN 59, and between MCP 91 and CN 59. , RAM92~EEPR
The OM94 constitutes the data processing section, and the CPU in the MCP91 is connected to the PROM93 and the R built in the MCP91.
It executes OM instructions and performs data processing operations while accessing necessary data from the RAM 92.

Therefore, depending on the operation of the KB55, the memory card 56
The contents of the memory card 56 are stored in the RAM 92, and the contents of the memory card 56 can be freely set or changed by operating the KB 55, and these conditions are displayed on the DP 54.

In addition, by operating the KB55, the contents of the RAM 92 or memory card 56 are transmitted as transmission data, and a response thereto is received and displayed on the DP54, so commands to each unit, data settings or changes, etc. Alternatively, the contents of the memory card 56 can be transferred and confirmed by the DP 54, and all data to be confirmed can be requested to be sent to a specific unit, and the received contents can be transferred to the RAM 92 or the memory card 56. In addition to being stored, it can be displayed sequentially by the DP 54.

In addition, it is possible to freely receive and display data signals.
This makes it possible to monitor the status of data transmission and reception between each unit.

However, the above data transmission/reception is performed by BCT1t to 1n.

GW7, and transmission lines 31 and 32 via these
One of the HMMIs 8, etc. connected to the HMMI 8 acquires the transmission right, and data is sent and received in response to the one that acquired the transmission right transmitting, and these are all equivalent communications. The apparatus (hereinafter referred to as 5TA) acquires the transmission right as shown in the timing chart of FIG. 1 showing the main part.

In other words, turning on the power, setting the initial state, etc.
According to ART, J, the silent timers for monitoring the no-signal time provided in each of 5TA1 to 5TAn start simultaneously, and the set time Te1=Tsn of these is determined individually for each of 5TA1 to 5TAn. Therefore, in this example, the silent timer of 5TAI times up first, and in response to this, the STA acquires the transmission right and performs transmission SDI.

In addition, the other 5TAB to 5TAn are monitoring the transmission SDI, and when this is finished and there is no signal, the transmission SDI is set to each of the 5TAI to 5TAn, and different set times Tt, ~Ttn are set. The daily timer starts at the same time, and at this time 5TAI has transmitted data, the set time Tt! Since the same time is the shortest after Tt, the summit timer of STA is 5TA3~5TA.
STA is the first to time up compared to the same timer of n, and this is the STA that has the money! acquires the transmission right and starts the transmission SD, and from then on, each 5TAI"=STA
5DI-8Dn alternately acquire the transmission right and transmit 5DI-8Dn.

However, each setting time Tts to Ttn is different from each STA, to
It is necessary to reasonably determine the importance of each 5TAn and the frequency of requests to acquire transmission rights.
A physical address is fixedly determined for each of the Ans according to the connection site, etc., and the EEP
In addition to setting it in the ROM 74, etc., the time to be set in the daily timer for determining the order of acquisition of transmission rights is determined by calculation according to the situation at that time. and a sender address SA based on the physical address, the setting time is determined each time, and the status of acquisition of transmission rights is controlled by certain rules.

In addition, in order to control the time point at which all devices acquire the transmission right and to maintain a synchronized relationship with data transmission and reception, each STA, ~5TAn has the transmission right to each time slot for each fixed time width on the time axis. The timing of all acquisitions is made to coincide.

In Fig. 6, when the time slot TS is set to "1" to r126j, the transmission right acquisition indicated by ○ is GW7゜HMM.
Each of I8 and BCTl l to 1n indicates a possible relationship, and in response to the occurrence of a no-signal state due to the end of any transmission, TS r 1 j to r 126 j are repeated, and G
W7. Those requesting acquisition of the transmission right among HMMI8 and BCT1x to In acquire the transmission right in the corresponding time slot TS.

Furthermore, in this example, GW4 is superior in terms of importance and frequency of occurrence of transmission right acquisition requests, and time slot TS is assigned as the one that can acquire the transmission right the most. , this is GW7 and BC
Considering the case where multiple units are connected to each of T11 to T1n at the same time, the transmission right is acquired promptly according to the operation, and the sender address S is set according to the connection part.
A? Each time slot TSt is determined individually, and each individual time slot TSt is allocated accordingly.

On the other hand, the physical addresses of BCT1+ to 1n shall be determined according to the mounting order or hidden parts, etc., and each
The time slot will be allocated once.

In addition, time slot TS "2" to "4", "6" to "
8'' to r122J to r124J, r126j are
It is allocated according to the number of HMMI8 and BCTl l to 1n installed, and these time slots TS are allocated based on the physical address set for each.
One of them is assigned to each.

Furthermore, a plurality of sender addresses SA are set for the HMMI 8 in order to speed up data setting, transfer, etc. by operating the HMMI 8.

Here, the calculation for determining the set time Tt of the daily timer is performed as follows.

Tt=TTXTwXP ”””(1
) However, TT: 1st place for acquiring transmission rights (self'l@)Tw
: Transmission time for one word of data P: Coefficient determined according to the processing time required by the CPU. For example, Tw = 2.3 m5ec, P =
3, and it is set as the TwXPil time slot.

In addition, the TT sends CW7, HMMI8, B based on the sender address SA corresponding to the physical address, the current address CA of the one that has occupied the transmission right until now, etc.
First, each sender address SA is determined by the following formula, although it is determined for each CT1.

(CW) SA=IX4Xmeeee*(2)
However, m=o, 1,2・es・31 CHMM I:] SA=4xMA−1+4XMNXm “””(3
) However, m=o, 1, 2 *ee**3Q/M
NMA: Physical address MN: Number of connected devices (BCT) SA = 2 The free order TT of is determined by the following formula.

(GW) SA) When CA, TT=8A-CA...(5A)S
When A<CA, TT=TSmax-CA+SA ・---(5B
) However, TSmax: Number of time slots (126 in Figure 6) (HMMI) When SA>CA, TT=SA-CA...-@(6A)SA
(When CA, TT=TSmmx-CA+SA @-(6B)(
BCT) When SA>CA, TT=SA-CA...Fist・ (7
A) When SA≦CA, TT=TSmax-CA+SA ・eee・(7B
) Therefore, TT obtained from equations (5A) to (7B)
To perform the calculation of equation (1) using K, each 0
The time Tt to be set in the forward timer is determined.

In contrast to the above, the silent timer setting time T in Figure 1
3 is fixedly determined by the following formula.

Ta=(TSmax+SA)XTwXP ***s
*(3) Figure 7 shows CW7, HMMI 8, B
CT 1 * ~ 1 n0 This is a comprehensive flowchart of the transmission/reception control situation by the CPU, and the rsTAR in Fig. 1
It is executed according to TJ.

That is, after setting Ta'jz in formula (8) to the silent contest timer configured by the CPU, perform "Silent Timer Flow" J101, and then
Timer fist timeout? While J 102 is N (No), "Signal reception? J 111 N" via transmission path 3
Repeat step 102 and subsequent steps through step 102
If is N or step 111 is Y (YES), then "After performing silent timer clear jl12i,
The content received in step 111 is a global Φ message (hereinafter referred to as GL) for the whole, a command message (hereinafter referred to as CD) that gives a command to one of them, or a data transmission t-' to one of them! rGL or
CD or RQ? j 113, and if this is Y, "self-order calculation" calculates TT according to the current address CA added to the received message.
114 according to formulas (11) to (7B), and then select [Self-addressed?] using the destination address code added to the received message. J 121 t-Discriminate and Y of this
"Receiving processing" 122 is performed in accordance with the step 121, whereas "monitoring processing" 123 is performed when step 121 is N.

On the other hand, if step 102 is Y, since the self can acquire the transmission right, "CA4-8A (the highest priority)" 131
Then, set the own sender address SA and 'i current address CA, and perform "eye face calculation" 1 in the same way as in step 114.
Do 32.

However, "SA (first order)" in step 131 is applied when there is a plurality of SAi, and step 132 is performed for use in a standby state, which will be described later.

Then I asked myself “Transmission data aj9? J133k
If the check is N, the "dummy message sending preparation" 141 is performed to maintain synchronization with others, and then the "sending process" 142 is executed. However, if step 133 is Y, the message is sent immediately. The process moves to step 142.

When the execution of any one of the above steps 122, 123, and 142 is completed, the standby state is entered, and step 114
Or set all mountaintop timers configured in the CPU using the set time Tt based on the TT obtained in step 132. , [Automatic timer timeout? Through Yi of J 153, as in step 133, ``Is there any data to send?'' Checks ``J 154-2,'' and if this is N, then ``Silent timer timeout? By counting clock pulses etc., (1
) time slot TS indicated by Tw
[Wait for 3 time slots J 161]
In this way, the process waits for the time required to start transmitting the signal, and in addition, as in step 111, it checks ``signal reception 'i'' J 162, and while this is N, repeats steps 153 and subsequent steps. In response to 162 becoming Y, steps 151 and 152 "clear each timer" 163 are performed, and step 162 determines whether the received destination is "addressed to self?" 122, whereas in step 164 N, the process returns to step 123.

Moreover, if step 155 becomes Y while step 162 is N, r CA←S as in steps 131 to 141.
A (highest rank) J 171 set, "Transmission data 4j
After checking p'i'j172, performing dummy message transmission preparation J173, and r auto-order calculation J174, the process returns to step 142.

However, the setting time T3 of the silent timer and the setting time Tt of the automatic timer have a relationship of Ts>Tt, and step 153 becomes Y earlier than step 155, and the corresponding check in step 154 is performed. If it is Y, set its own sender address SA as the current address CA by "CA + - 8 people" 181, and after careful consideration,
In order to proceed to step 142, the transmission right is acquired according to the timeout of the self-order timer, and step 1
The data to which the current address CAi determined in step 81 is added is transmitted in step 142.

FIG. 8 is a lower-level routine showing details of step 122, in which the contents of the acceptance signal are determined as "Message type?" 301
It is determined whether it is GL, CD, or RQ, and if it is GL, "Receive one word completed? J" While 311 is N, perform "data reception" 312, repeat steps 311 and after, and this rEXITJf according to Y,
Then, the process moves to step 151 in FIG.

In addition, in the case of a CD, as in steps 311 and 312, the [Data Reception J
332 'ii-Repeat, and if step 321 yields Y, send acknowledgment signal r ACK' 323.

On the other hand, in the case of RQ, the requested "designated data transmission" 332 is repeated while 1331 is N, and the transmission is stopped according to Y in step 331.

FIG. 9 shows the lower routine of step 123. For example, the CPU performs a "blank timer start" 201 set to a time of 7 time slots, and then executes a "blank timer timeout? J 20".
[Signal received? Check J 211, and if it is Y, [Blank Timer Clear
212', and then select "Signal end?" for transmission line 3.
Monitor this money until 213 becomes Y, and step 213
As the signal becomes Y and there is no signal, step 2
01 and subsequent steps are repeated, and when step 202 becomes Y while step 211 is N, the "monitoring process" is ended.

Therefore, seven time slots after the no-signal state has been reached, the self-shift timer in step 151 is started, and the transmission right is acquired as described above.

FIG. 10 shows the lower routine of step 142, which determines the "message type? J401" of the transmission data,
If it is GL, [Send completed?] While J 411 is N,
Data transmission j 412'? It repeats and ends the "transmission process" in response to Y in step 411, whereas in the case of a CD, "transmission complete? The configured "supervisory timer star" j 431 k is performed, and while "supervisory timer timeout?" 432 is N, an acknowledgment signal rACK? is received in response to step 323. 433 becomes Y, the "transmission process" via Yi in step 421 ends, but as step 432 becomes Y while step 433 is N, the counter configured by the CPU returns Ml?,,144
1 and repeats ζ step 422 and subsequent steps until it becomes Y, repeating pig transmission a total of M-1 times.

Also, when RQ, "Transmission completed? J 451 N
t- send an rRQ word specifying the requested data J 452 ? After performing steps 431-433
Similar to ゜441, "Monitoring timer start" 461,
[Monitoring timer timeout? 4462, step 3
Execution of “response data received?” 463 corresponding to 32,
and “Resend Ml?” corresponding to Y in step 462.
Repeated transmission according to N of 471 is performed.

Therefore, according to the set time Ttl-Ttn in FIG.
'shi, time slots TS "1" to r1 shown in FIG.
26j is GW7, HMMI 8 and BCTIB
~In, and each p1 acquires the transmission right in the allocated time slot TS according to the possession of transmission data.

In addition, the setting time Tt of the internal timer is determined each time according to the end of either transmission or the elapse of the silent period, and ρ at the end of transmission is (1) to (7B) 2, and after the elapse of the silent period is (8 ), so the sixth
Time slots in the diagram TS r I J ~ r 128 J
Among them, the most advanced side is allocated as much as possible, thereby reducing communication blank time and overall reducing the time from the generation of data to be transmitted to the start of transmission.

Furthermore, GW7. Since HMMlB and BCT1t~In each have equivalent functions, even if one of them fails, the overall function is maintained, reliability is improved, and special signal transmission and reception is not required for giving and receiving transmission rights. This will improve overall communication speed.

However, the configurations in FIGS. 2 to 5 may be determined according to the situation, and the number of time slots and their allocation status in FIG. 6 may also be determined according to the conditions. In the drawings, various modifications can be made, such as replacing each step with an equivalent one, or replacing the order of the steps, or omitting unnecessary parts.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, with a simple configuration, transmission rights can be reliably transmitted and received, the overall communication speed is improved, the reliability as a whole is improved, and a common transmission path is improved. Remarkable effects can be obtained in various data communications using .

[Brief explanation of the drawing]

The figures show an embodiment of the present invention, in which Fig. 1 is a timing chart of the main parts showing the acquisition status of transmission rights, Fig. 2 is a block diagram of the control device, Fig. 3 is a front view of the operation display, and Fig. 5 is a block diagram of the control unit, FIG. 5 is a block diagram of the operation display, FIG. 6 is a diagram showing the time slot allocation situation, and FIGS. 7 to 10 are flowcharts of the control situation. 11~1n・Fist--BCT (control unit), 1at~
1an11@...Bus line, 21~2n...l0U (input/output crab unit), 31,3...Transmission line, 8...Fist/HR (Ml (operation display), 71.91... @M
CP (microcomputer), 72.92-...R
AM (variable memory), 73.93...FROM (write memory), T4...EEPROM (variable write memory), 77.96...@I/F (interface)
, Ta1~Tsn, Ttl~Ttn...Conflict/setting time, TS11+1Φ/time slot.

Claims (1)

[Claims] A plurality of communication devices connected to a common transmission path are provided, each communication device acquires a transmission right alternately, and the communication device that acquires the transmission right transmits data via the common transmission path. In the communication method, each of the communication devices is provided with a self-order timer having a different set time to determine the order in which it acquires the transmission right, and when the common transmission path becomes in a no-signal state, the self-order timer A communication system using a common transmission path, characterized in that timers are started at the same time, and the communication device having the one whose timer expires first among the sequential timers acquires the transmission right.