CN115964233B - Interconnection bare chip self-test system and method based on self-test node - Google Patents
Interconnection bare chip self-test system and method based on self-test node Download PDFInfo
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Abstract
The invention discloses an interconnection bare chip self-test system and method based on self-test nodes, which relate to the field of bare chip level networks and comprise self-test nodes deployed on each interconnection bare chip; each self-test node comprises a self-test packet sender and a self-test responder; each self-test packet generator comprises a configurable register, a data packet transmission controller, a data wrapper and a data packet parser; the configurable register is configured through the MCU; the configurable register is respectively connected with the data packet sending controller, the data wrapper and the data packet parser; the data packet transmission controller is connected with the data packet wrapper. The invention solves the problem that faults are difficult to locate in the multi-die integrated microsystem based on the interconnected die, realizes the detection of the on-chip inter-chip routing forwarding function of the interconnected die and the basic read-write function of the slave device node under the condition of not depending on a host node, and improves the testability of the multi-die integrated microsystem.
Description
Technical Field
The invention relates to the field of a bare chip level network, in particular to an interconnection bare chip self-test system and method based on self-test nodes.
Background
In monolithic application specific integrated circuits, all components are designed and fabricated in the same process on one silicon wafer. As process dimensions shrink, the cost and development cycle time to develop monolithic application specific integrated circuits becomes extremely high. In this case, multi-Die (Die) integration is a necessary choice for developing high-performance chips in the future, i.e., a plurality of Chip assemblies which have different functions and are verified and not packaged are interconnected and assembled and packaged as a whole into a Chip in the same package, so as to form a Multi-Chip Module (MCM), and the Die of these MCMs are called a Die (Chiplet), and each Die in the same package can be manufactured by different processes and from different manufacturers, so that the development period and difficulty are greatly shortened and reduced.
However, with the explosive growth of the number of processors (processors) and other functional units in a chip, in order to fully play the role of each functional unit, it is also important to construct an on-chip and inter-chip integrated high-performance network to realize efficient communication between a plurality of functional units and a plurality of core grains. Over the past 20 years, network-on-Chip (NoC) technology has been fully studied and developed, and particularly, when a large complex system is constructed, the Network-on-Chip replaces the conventional bus type interconnection to form an indispensable system component. And the NoC-like interconnect structure employed on scalable interconnect Die is referred to as a Network-on-Die (NoD). NoD inherits the high bandwidth and high scalability of NoC, can be used as an interconnect structure for multiple die, and can also form a Network-on-Package (NoP) by extension cascading to realize larger scale die interconnection.
NoD/NoP-based multi-die integrated microsystems have certain system complexity, and interconnection structures, protocol conversion interfaces of all nodes, hosts or memories connected with all nodes and the like may be failed in some cases. Because of the heterogeneous and complex nature of the multi-die integrated microsystem, locating faults becomes difficult. Thus, interconnect die are necessary as an important component of integrated multi-die microsystems to support a set of self-test mechanisms to assist in locating faults and to improve system testability.
Disclosure of Invention
Aiming at the defects in the prior art, the self-test system and the self-test method for the interconnected bare chips based on the self-test node realize the on-chip routing forwarding function of the interconnected bare chips and the detection of the basic read-write function of the slave equipment node without depending on a host node, and improve the testability of the multi-bare-chip integrated microsystem.
In order to achieve the aim of the invention, the invention adopts the following technical scheme:
An interconnect die self-test system based on self-test nodes is provided that includes a self-test node disposed on each interconnect die; each self-test node comprises a self-test packet sender and a self-test responder;
Each self-test packet generator comprises a configurable register, a data packet transmission controller, a data wrapper and a data packet parser; the configurable register is configured through the MCU; the configurable register is respectively connected with the data packet sending controller, the data wrapper and the data packet parser; the data packet sending controller is connected with the data packet wrapper;
A packet transmission controller for driving the packet wrapper to encapsulate the request packet according to the configuration contents of the configurable register;
a data wrapper for wrapping the data packet and transmitting a request packet to the slave node;
A data packet parser for receiving the response packet from the slave node and registering necessary information in the response packet in a configurable register;
The self-test responder is used for detecting whether the interconnection bare chips can be routed correctly or not according to the write request packet of the self-test packet sender, namely detecting whether the two nodes are interconnected and communicated or not, and returning a response packet to the node sent by the write request packet.
Further, the request packets of the self-test packet generator include an erase request packet, a write request packet and a read request packet sent to the NAND FLASH node, a write request packet and a read request packet sent to the DDR memory node, and a write request packet sent to the self-test responder.
Further, each self-test responder includes a request packet parser and a response wrapper; wherein:
the request packet analyzer is used for analyzing the received write request packet and extracting effective information;
and the response wrapper is used for wrapping the write response packet according to the valid information and sending the write response packet to the node sending the request packet.
Further, the configurable register includes:
an interconnection bare chip number register, the address offset is 0x00, and the interconnection bare chip number register is used for reading data of a corresponding address for confirmation;
a main address low-order register with an address offset of 0x04 for recording the low 32 bits of the destination address;
the main address high-order register has an address offset of 0x08 and is used for recording the high 32 bits of the destination address;
A control information register with an address offset of 0x0c for recording a transaction ID, an event type, and a data length;
A control information status register, the address offset is 0x10, which is used for recording whether the configuration of the current control information register is legal; when the bit is 0, representing that the current control information configuration is legal; when the bit is 1, representing that the current control information configuration is illegal;
The method comprises the steps of sending a building register, wherein the address offset is 0x24 and is used as an enabling bit of a self-test packet sender, and the self-test packet sender is used for sending a request packet according to current configuration information when bit is 1, the state of a data packet sending controller is idle, and the configuration of a current control information register is legal; after the bit is set to 1, the bit automatically recovers to 0 at the rising edge of the next clock;
A transmit status register having an address offset of 0x28 for use as a self-test wrapper status bit for recording the self-test wrapper status; when the bit is 0, the self-test packet transmitter is in an idle state; when the bit is 1, the self-test packet sender is in a busy state;
a write request word 0 register having an address offset of 0x14 for recording a word 0 payload of a write request data body flit;
A write request word 1 register having an address offset of 0x18 for recording a word 1 payload of a write request data body flit;
a write request word 2 register with an address offset of 0x1c for recording a word 2 payload of a write request data body flit;
A write request word 3 register having an address offset of 0x20 for recording a word 3 payload of a write request data body flit;
The write response information register has an address offset of 0x2c and is used for recording the transaction ID of the write response packet received last time and the count value of the number of times the write response packet has been received;
the read acknowledgement information register has an address offset of 0x30 and is used for recording the transaction ID of the last received read acknowledgement packet and the count value of the number of times the read acknowledgement packet is received;
The read response information register has an address offset of 0x34 and is used for recording the transaction ID of the read response packet which is received last time, the count value of the number of times of the received read response packet and the count value of the number of times of the read response packet which has received data errors;
the read response word 0 register has an address offset of 0x38 and is used for recording the word 0 effective load of the last received read response packet data body flit;
the read response 1 st word register has an address offset of 0x3c and is used for recording the 1 st word effective load of the last received read response packet data volume flit;
the read response 2 nd word register has an address offset of 0x40 and is used for recording the 2 nd word effective load of the last received read response packet data body flit;
a read response 3 rd word register with an address offset of 0x44 for recording the 3 rd word payload of the last received read response packet data body flit;
The data comparison register has an address offset of 0x48 and is used for recording the effective load comparison result of the write request and the read response of the ID of the two adjacent transactions; wherein the comparison result 00 indicates that the write request data and the read response data are consistent; the comparison result 01 indicates that the write request data and the read response data are inconsistent; the comparison result 10 indicates that the two transaction IDs are incorrectly related.
The self-test method of the interconnected bare chips based on the self-test node comprises a self-test system of the interconnected bare chips based on the self-test node, and further comprises the following steps:
S1, a self-test packet sender sends a request packet to a self-test responder, a DDR memory node and a NAND FLASH node in the same interconnection bare chip, and judges whether the on-chip routing forwarding function is normal, whether the DDR memory node function is normal and whether the NAND FLASH node function is normal according to received response information so as to realize on-chip self-test;
S2, sending a write request packet to a self-test responder in the other interconnection bare chip through the self-test packet sender, and judging whether the inter-chip transmission function is normal or not by reading response information from the self-test responder in the other interconnection bare chip so as to realize inter-chip self-test.
Further, in step S1, the specific method for determining whether the on-chip routing forwarding function is normal according to the received response information is as follows:
The self-test packet sender sends a write request packet to a self-test responder in the same interconnection bare chip, judges whether corresponding response information is received within a set time after the write request packet is sent, and if so, judges that the routing forwarding function of the on-chip interconnection structure is normal; otherwise, determining that the routing forwarding function of the intra-chip interconnection structure is abnormal.
Further, in step S1, the specific method for determining whether the DDR memory node functions normally according to the received response information is:
When the on-chip routing forwarding function is normal, if corresponding response information is not received within a set time after a write request packet or an erase request packet is sent to DDR memory nodes in the same interconnection bare chip, and reading confirmation and reading response information are not received within the set time after a read request packet is sent, judging that the DDR memory nodes have faults; the DDR memory node self faults include network interface faults of the DDR memory node, DDR memory controller faults and DDR memory faults;
When the on-chip routing forwarding function is normal, if the on-chip routing forwarding function is normal, a write request packet or an erase request packet of the DDR memory node is responded, and a read confirmation is received after a read request, but no read response or a read response is available but read response data is wrong, the DDR memory controller fault and/or the DDR memory fault are determined.
Further, in step S1, the specific method for determining whether the function of the NAND FLASH node is normal according to the received response information is as follows: when the on-chip routing forwarding function is normal, if corresponding response information is not received within a set time after a write request packet or an erase request packet is sent to NAND FLASH nodes in the same interconnection bare chip, and reading confirmation and reading response information are not received within a set time after a read request packet is sent, judging that the NAND FLASH nodes have faults; the NAND FLASH node itself failures include network interface failures of NAND FLASH node, NAND FLASH controller failures, NAND FLASH memory failures;
When the on-chip routing forwarding function is normal, if the on-chip routing forwarding function is normal, a write request packet or an erase request packet of the NAND FLASH node is responded, and a read acknowledgement is received after a read request, but no read response is provided or a read response is provided but read response data is wrong, then a NAND FLASH controller fault and/or a NAND FLASH memory fault are determined.
Further, the specific method for determining whether the inter-chip transmission function is normal in step S2 is as follows:
When the on-chip routing forwarding function is normal, if the corresponding write response is not received within a set time after a write request packet is sent to a self-test responder in another interconnection bare chip, judging that the inter-chip transmission has faults.
The beneficial effects of the invention are as follows:
1. The invention solves the problem that faults are difficult to locate in the multi-die integrated microsystem based on the interconnected die, realizes the detection of the on-chip inter-chip routing forwarding function of the interconnected die and the basic read-write function of the slave device node under the condition of not depending on a host node, and improves the testability of the multi-die integrated microsystem.
2. The self-test packet generator comprises configurable functional registers, so that the self-test process is more flexible, and the fault occurrence position is better positioned through self-test feedback information registered by the functional registers.
Drawings
FIG. 1 is a block diagram of a self-test packet transmitter;
Fig. 2 is a block diagram of a self-test responder.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and all the inventions which make use of the inventive concept are protected by the spirit and scope of the present invention as defined and defined in the appended claims to those skilled in the art.
As shown in fig. 1 and 2, the self-test node-based interconnect die self-test system includes a self-test node disposed on each interconnect die; each self-test node comprises a self-test packet sender and a self-test responder;
Each self-test packet generator comprises a configurable register, a data packet transmission controller, a data wrapper and a data packet parser; the configurable register is configured through the MCU; the configurable register is respectively connected with the data packet sending controller, the data wrapper and the data packet parser; the data packet sending controller is connected with the data packet wrapper;
A packet transmission controller for driving the packet wrapper to encapsulate the request packet according to the configuration contents of the configurable register;
a data wrapper for wrapping the data packet and transmitting a request packet to the slave node;
A data packet parser for receiving the response packet from the slave node and registering necessary information in the response packet in a configurable register;
The self-test responder is used for detecting whether the interconnection bare chips can be routed correctly or not according to the write request packet of the self-test packet sender, namely detecting whether the two nodes are interconnected and communicated or not, and returning a response packet to the node sent by the write request packet.
The self-test packet transmitter is configured by the MCU through the AMBA bus interface to the configurable registers, the configurable registers automatically drive the data packet transmitting controller to transmit a request packet to the slave device node after the configuration is completed, and receive a response packet from the slave device node, wherein necessary information in the response packet is registered by part of functional registers, and the MCU can read the response information through the AMBA bus interface to confirm, so that the self-test result is judged.
Further, the request packets of the self-test packet generator include an erase request packet, a write request packet and a read request packet sent to the NAND FLASH node, a write request packet and a read request packet sent to the DDR memory node, and a write request packet sent to the self-test responder.
Further, each self-test responder includes a request packet parser and a response wrapper; wherein:
the request packet analyzer is used for analyzing the received write request packet and extracting effective information;
and the response wrapper is used for wrapping the write response packet according to the valid information and sending the write response packet to the node sending the request packet.
The self-test responder has no configuration interface and does not need MCU configuration, and the self-test responder comprises request packet analysis logic and response packet encapsulation logic in its own structure, and can automatically analyze and extract effective information when receiving a write request packet, then encapsulate the write response packet according to the information, and send the write response packet to the node where the corresponding self-test responder is located through an interconnection structure.
Further, the configurable register includes:
An interconnection bare chip number register, the address offset is 0x00, and the interconnection bare chip number register is used for reading data of a corresponding address for confirmation; the specific content is shown in Table 1;
Table 1: interconnect die number register (NoDID register, address offset: 0x 00)
A main address low-order register with an address offset of 0x04 for recording the low 32 bits of the destination address; the specific content is shown in Table 2;
Table 2: main address low order register (Address offset: 0x 04)
The main address high-order register has an address offset of 0x08 and is used for recording the high 32 bits of the destination address; the specific content is shown in Table 3;
Table 3: main address high-order register (Address offset: 0x 08)
A control information register with an address offset of 0x0c for recording a transaction ID, an event type, and a data length; the specific content is shown in Table 4;
Table 4: control information register (Address offset: 0x0 c)
A control information status register, the address offset is 0x10, which is used for recording whether the configuration of the current control information register is legal; when the bit is 0, representing that the current control information configuration is legal; when the bit is 1, representing that the current control information configuration is illegal; the specific content is shown in Table 5;
table 5: control information status register (Address offset: 0x 10)
The method comprises the steps of sending a building register, wherein the address offset is 0x24 and is used as an enabling bit of a self-test packet sender, and the self-test packet sender is used for sending a request packet according to current configuration information when bit is 1, the state of a data packet sending controller is idle, and the configuration of a current control information register is legal; after the bit is set to 1, the bit automatically recovers to 0 at the rising edge of the next clock; the specific content is shown in Table 6;
Table 6: send setup registers (Address offset: 0x 24)
A transmit status register having an address offset of 0x28 for use as a self-test wrapper status bit for recording the self-test wrapper status; when the bit is 0, the self-test packet transmitter is in an idle state; when the bit is 1, the self-test packet sender is in a busy state; the specific content is shown in Table 7;
Table 7: transmit status register (Address offset: 0x 28)
A write request word 0 register having an address offset of 0x14 for recording a word 0 payload of a write request data body flit; the specific content is shown in Table 8;
Table 8: write request word 0 register (Address offset: 0x 14)
A write request word 1 register having an address offset of 0x18 for recording a word 1 payload of a write request data body flit; the specific content is shown in Table 9;
Table 9: write request word 1 register (Address offset: 0x 18)
A write request word 2 register with an address offset of 0x1c for recording a word 2 payload of a write request data body flit; the specific content is shown in Table 10;
table 10: write request word 2 register (Address offset: 0x1 c)
A write request word 3 register having an address offset of 0x20 for recording a word 3 payload of a write request data body flit; the specific content is shown in Table 11;
table 11: write request word 3 register (Address offset: 0x 20)
The write response information register has an address offset of 0x2c and is used for recording the transaction ID of the write response packet received last time and the count value of the number of times the write response packet has been received; the specific content is shown in Table 12;
table 12: write response information register (Address offset: 0x2 c)
The read acknowledgement information register has an address offset of 0x30 and is used for recording the transaction ID of the last received read acknowledgement packet and the count value of the number of times the read acknowledgement packet is received; the specific content is shown in Table 13;
Table 13: read acknowledgement information register (Address offset: 0x 30)
The read response information register has an address offset of 0x34 and is used for recording the transaction ID of the read response packet received last time, the count value of the number of times the read response packet has been received, and the count value of the number of times the read response packet has received data errors (mainly indicating that the payloads of the data volume flits are inconsistent before and after the payloads of the data volume flits); the specific content is shown in Table 14;
Table 14: read response information register (Address offset: 0x 34)
The read response word 0 register has an address offset of 0x38 and is used for recording the word 0 effective load of the last received read response packet data body flit; the specific content is shown in Table 15;
table 15: read response word 0 register (Address offset: 0x 38)
The read response 1 st word register has an address offset of 0x3c and is used for recording the 1 st word effective load of the last received read response packet data volume flit; the details are shown in Table 16;
Table 16: read response word 1 register (Address offset: 0x3 c)
The read response 2 nd word register has an address offset of 0x40 and is used for recording the 2 nd word effective load of the last received read response packet data body flit; the specific content is shown in Table 17;
table 17: read response word 2 register (Address offset: 0x 40)
A read response 3 rd word register with an address offset of 0x44 for recording the 3 rd word payload of the last received read response packet data body flit; the specific content is shown in table 18;
Table 18: read response word 3 register (Address offset: 0x 44)
The data comparison register has an address offset of 0x48 and is used for recording the effective load comparison result of the write request and the read response of the ID of the two adjacent transactions; wherein the comparison result 00 indicates that the write request data and the read response data are consistent; the comparison result 01 indicates that the write request data and the read response data are inconsistent; the comparison result 10 indicates that the two transaction IDs are incorrectly related. The details are shown in Table 19;
table 19: data alignment register (Address offset: 0x 48)
The self-test method of the interconnected bare chips based on the self-test node further comprises the following steps on the basis of a self-test system of the interconnected bare chips based on the self-test node:
S1, a self-test packet sender sends a request packet to a self-test responder, a DDR memory node and a NAND FLASH node in the same interconnection bare chip, and judges whether the on-chip routing forwarding function is normal, whether the DDR memory node function is normal and whether the NAND FLASH node function is normal according to received response information so as to realize on-chip self-test;
S2, sending a write request packet to a self-test responder in the other interconnection bare chip through the self-test packet sender, and judging whether the inter-chip transmission function is normal or not by reading response information from the self-test responder in the other interconnection bare chip so as to realize inter-chip self-test.
In step S1, the specific method for judging whether the on-chip routing forwarding function is normal according to the received response information is as follows: the self-test packet sender sends a write request packet to a self-test responder in the same interconnection bare chip, judges whether corresponding response information is received within a set time after the write request packet is sent, and if so, judges that the routing forwarding function of the on-chip interconnection structure is normal; otherwise, determining that the routing forwarding function of the intra-chip interconnection structure is abnormal.
In step S1, the specific method for judging whether the DDR memory node functions normally according to the received response information is as follows:
When the on-chip routing forwarding function is normal, if corresponding response information (corresponding to a write response information register) is not received within a set time after a write request packet or an erase request packet is sent to DDR memory nodes in the same interconnection bare chip, and if read confirmation (corresponding to a read confirmation information register) and read response information (corresponding to a read response information register) are not received within the set time after a read request packet is sent, judging that the DDR memory nodes have faults; the DDR memory node self faults include network interface faults of the DDR memory node, DDR memory controller faults and DDR memory faults;
When the on-chip routing forwarding function is normal, if a write request packet or an erase request packet of the DDR memory node is responded, a read acknowledgement is received after a read request, but no read response or a read response is available, but read response data (corresponding to a read response x-th word register and a data comparison register) are wrong, the DDR memory controller fault and/or the DDR memory fault are judged.
In step S1, the specific method for judging whether the NAND FLASH node functions normally according to the received response information is as follows:
When the on-chip routing forwarding function is normal, if corresponding response information (corresponding to a write response information register) is not received within a set time after a write request packet or an erase request packet is sent to NAND FLASH nodes in the same interconnection bare chip, and if read acknowledgement (corresponding to a read acknowledgement information register) and read response information (corresponding to a read response information register) are not received within a set time after a read request packet is sent, judging that the NAND FLASH nodes have faults; the NAND FLASH node itself failures include network interface failures of NAND FLASH node, NAND FLASH controller failures, NAND FLASH memory failures;
When the on-chip routing forwarding function is normal, if the on-chip routing forwarding function is normal, a write request packet or an erase request packet of the NAND FLASH node is responded, and a read acknowledgement is received after a read request, but no read response is performed or a read response is performed, but read response data (corresponding to a read response x-th word register and a data comparison register) are wrong, then a NAND FLASH controller fault and/or a NAND FLASH memory fault are determined.
The specific method for judging whether the inter-chip transmission function is normal in the step S2 is as follows: when the on-chip routing forwarding function is normal, if the corresponding write response is not received within a set time after a write request packet is sent to a self-test responder in another interconnection bare chip, judging that the inter-chip transmission has faults.
In one embodiment of the invention, the specific process of initiating the request is:
1) First, according to NoDID (i.e., interconnect die number for distinguishing a plurality of interconnect die of an extended cascade), noDID registers (interconnect die number registers, address offset: 0x 00). After configuration, the data of the address can be read for confirmation.
2) Configuration control information register (address offset: 0x0 c), configuration transaction ID, event type TTP (supporting erase, write and read requests to NAND FLASH nodes, write and read requests to DDR memory nodes, write requests to self-test responders), and data length LEN. After configuration, the data of the address can be read for confirmation.
3) Two main address (destination address) registers (address offset: 0x04, 0x 08), the lower 32 bits and the upper 32 bits of the destination address, respectively.
4) To initiate a write request packet, four write request payload word registers (address offset: 0x14, 0x18, 0x1c, 0x 20), write request data flits (flits, which are the smallest flow control units in the interconnect die, consist of a packet of several flits) for a total of four words (128 bit) of payloads, and then if a write request packet is successfully issued, the payloads of all of the data flits will be consistent with the configuration value. If a read request or an erase request is initiated, this step is ignored.
5) Read control information status register (address offset: 0x 10) determines whether the control information configuration is legal.
6) Reading the transmission status register (address offset: 0x 28) determines if the packet transmitter is in an idle state.
7) After determining that the control information configuration is legal and that the packet transmitter is in an idle state, the transmission setup register (address offset: 0x 24) bit0, i.e., the request packet transmission by the packet transmitter can be triggered.
The specific process of receiving the response is as follows:
1) Acknowledging received write or erase responses
In the invention, the response packet corresponding to the erasing request packet and the response packet corresponding to the writing request packet are both writing response packets, so that only the writing response information register (address offset: 0x2 c) is required to be read to confirm the response information. The number of received response packets and the TID of the last response can be obtained by reading this register. If the count value of the number of times the write response packet has been received is increased by 1 compared with the original value and the TID of the last write response is consistent with the TID of the write request, then the successful receipt of the write response corresponding to the write request is indicated.
2) Acknowledging received read responses
I) Read response information register (address offset: 0x 34). The number of read response packets received, the TID of the last read response, and the number of read response packets for which data errors have been received can be obtained by reading the register. If the count value of the number of times of receiving the read response packet is increased by 1 compared with the original value, the TID of the last read response is consistent with the TID of the read request, and the number of times of receiving the read response packet with data errors is not increased, the correct read response corresponding to the read request is successfully received.
Ii) read four read response word registers (address offset: 0x38, 0x3c, 0x40, 0x 44). The 128bit payload of the first data body flit of the read response packet can be obtained by reading the values of these registers.
Iii) If a write request of the same data length is initiated for the same destination address before a read request is initiated, and TID meets the adjacent rule (i.e., read request tid=write request tid+1), then the data alignment register (address offset: 0x 48) to obtain a comparison of the write request and read response data to determine if the read back data is correct.
In summary, the invention solves the problem that the fault is difficult to locate in the multi-die integrated microsystem based on the interconnected die, realizes the detection of the on-chip inter-chip routing forwarding function of the interconnected die and the basic read-write function of the slave node under the condition of not depending on the host node, and improves the testability of the multi-die integrated microsystem.
Claims (9)
1. An interconnect die self-test system based on self-test nodes, comprising self-test nodes disposed on each interconnect die; each self-test node comprises a self-test packet sender and a self-test responder;
Each self-test packet generator comprises a configurable register, a data packet transmission controller, a data wrapper and a data packet parser; the configurable register is configured through the MCU; the configurable register is respectively connected with the data packet sending controller, the data wrapper and the data packet parser; the data packet sending controller is connected with the data packet wrapper;
A packet transmission controller for driving the packet wrapper to encapsulate the request packet according to the configuration contents of the configurable register;
a data wrapper for wrapping the data packet and transmitting a request packet to the slave node;
A data packet parser for receiving the response packet from the slave node and registering necessary information in the response packet in a configurable register;
The self-test responder is used for detecting whether the interconnection bare chips can be routed correctly or not according to the write request packet of the self-test packet sender, namely detecting whether the two nodes are interconnected and communicated or not, and returning a response packet to the node sent by the write request packet.
2. The interconnect die self-test system based on self-test nodes of claim 1, wherein the request packets of the self-test packet generator include an erase request packet, a write request packet, and a read request packet sent to the NAND FLASH nodes, a write request packet and a read request packet sent to the DDR memory nodes, and a write request packet sent to the self-test responder.
3. The self-test node-based interconnect die self-test system of claim 1, wherein each self-test responder comprises a request packet parser and a response wrapper; wherein:
the request packet analyzer is used for analyzing the received write request packet and extracting effective information;
and the response wrapper is used for wrapping the write response packet according to the valid information and sending the write response packet to the node sending the request packet.
4. The self-test node-based interconnect die self-test system of claim 1, wherein the configurable register comprises:
an interconnection bare chip number register, the address offset is 0x00, and the interconnection bare chip number register is used for reading data of a corresponding address for confirmation;
a main address low-order register with an address offset of 0x04 for recording the low 32 bits of the destination address;
the main address high-order register has an address offset of 0x08 and is used for recording the high 32 bits of the destination address;
A control information register with an address offset of 0x0c for recording a transaction ID, an event type, and a data length;
A control information status register, the address offset is 0x10, which is used for recording whether the configuration of the current control information register is legal; when the bit is 0, representing that the current control information configuration is legal; when the bit is 1, representing that the current control information configuration is illegal;
The method comprises the steps of sending a building register, wherein the address offset is 0x24 and is used as an enabling bit of a self-test packet sender, and the self-test packet sender is used for sending a request packet according to current configuration information when bit is 1, the state of a data packet sending controller is idle, and the configuration of a current control information register is legal; after the bit is set to 1, the bit automatically recovers to 0 at the rising edge of the next clock;
A transmit status register having an address offset of 0x28 for use as a self-test wrapper status bit for recording the self-test wrapper status; when the bit is 0, the self-test packet transmitter is in an idle state; when the bit is 1, the self-test packet sender is in a busy state;
a write request word 0 register having an address offset of 0x14 for recording a word 0 payload of a write request data body flit;
A write request word 1 register having an address offset of 0x18 for recording a word 1 payload of a write request data body flit;
a write request word 2 register with an address offset of 0x1c for recording a word 2 payload of a write request data body flit;
A write request word 3 register having an address offset of 0x20 for recording a word 3 payload of a write request data body flit;
The write response information register has an address offset of 0x2c and is used for recording the transaction ID of the write response packet received last time and the count value of the number of times the write response packet has been received;
the read acknowledgement information register has an address offset of 0x30 and is used for recording the transaction ID of the last received read acknowledgement packet and the count value of the number of times the read acknowledgement packet is received;
The read response information register has an address offset of 0x34 and is used for recording the transaction ID of the read response packet which is received last time, the count value of the number of times of the received read response packet and the count value of the number of times of the read response packet which has received data errors;
the read response word 0 register has an address offset of 0x38 and is used for recording the word 0 effective load of the last received read response packet data body flit;
the read response 1 st word register has an address offset of 0x3c and is used for recording the 1 st word effective load of the last received read response packet data volume flit;
the read response 2 nd word register has an address offset of 0x40 and is used for recording the 2 nd word effective load of the last received read response packet data body flit;
a read response 3 rd word register with an address offset of 0x44 for recording the 3 rd word payload of the last received read response packet data body flit;
The data comparison register has an address offset of 0x48 and is used for recording the effective load comparison result of the write request and the read response of the ID of the two adjacent transactions; wherein the comparison result 00 indicates that the write request data and the read response data are consistent; the comparison result 01 indicates that the write request data and the read response data are inconsistent; the comparison result 10 indicates that the two transaction IDs are incorrectly related.
5. The self-test method of the interconnected bare chips based on the self-test node is characterized by comprising the self-test system of the interconnected bare chips based on the self-test node as claimed in any one of claims 1 to 4, and further comprising the following steps:
S1, a self-test packet sender sends a request packet to a self-test responder, a DDR memory node and a NAND FLASH node in the same interconnection bare chip, and judges whether the on-chip routing forwarding function is normal, whether the DDR memory node function is normal and whether the NAND FLASH node function is normal according to received response information so as to realize on-chip self-test;
S2, sending a write request packet to a self-test responder in the other interconnection bare chip through the self-test packet sender, and judging whether the inter-chip transmission function is normal or not by reading response information from the self-test responder in the other interconnection bare chip so as to realize inter-chip self-test.
6. The self-test method of interconnection die based on self-test node as claimed in claim 5, wherein the specific method for determining whether the on-chip routing forwarding function is normal according to the received response information in step S1 is as follows:
The self-test packet sender sends a write request packet to a self-test responder in the same interconnection bare chip, judges whether corresponding response information is received within a set time after the write request packet is sent, and if so, judges that the routing forwarding function of the on-chip interconnection structure is normal; otherwise, determining that the routing forwarding function of the intra-chip interconnection structure is abnormal.
7. The self-test method of interconnection die based on self-test node as claimed in claim 5, wherein the specific method for determining whether the DDR memory node functions normally according to the received response information in step S1 is as follows:
When the on-chip routing forwarding function is normal, if corresponding response information is not received within a set time after a write request packet or an erase request packet is sent to DDR memory nodes in the same interconnection bare chip, and reading confirmation and reading response information are not received within the set time after a read request packet is sent, judging that the DDR memory nodes have faults; the DDR memory node self faults include network interface faults of the DDR memory node, DDR memory controller faults and DDR memory faults;
When the on-chip routing forwarding function is normal, if the on-chip routing forwarding function is normal, a write request packet or an erase request packet of the DDR memory node is responded, and a read confirmation is received after a read request, but no read response or a read response is available but read response data is wrong, the DDR memory controller fault and/or the DDR memory fault are determined.
8. The self-test method of interconnection die based on self-test node as claimed in claim 5, wherein the specific method for determining whether the NAND FLASH node functions normally according to the received response information in step S1 is as follows: when the on-chip routing forwarding function is normal, if corresponding response information is not received within a set time after a write request packet or an erase request packet is sent to NAND FLASH nodes in the same interconnection bare chip, and reading confirmation and reading response information are not received within a set time after a read request packet is sent, judging that the NAND FLASH nodes have faults; the NAND FLASH node itself failures include network interface failures of NAND FLASH node, NAND FLASH controller failures, NAND FLASH memory failures;
When the on-chip routing forwarding function is normal, if the on-chip routing forwarding function is normal, a write request packet or an erase request packet of the NAND FLASH node is responded, and a read acknowledgement is received after a read request, but no read response is provided or a read response is provided but read response data is wrong, then a NAND FLASH controller fault and/or a NAND FLASH memory fault are determined.
9. The method for self-test of interconnected die based on self-test nodes as claimed in claim 5, wherein the specific method for determining whether the inter-chip transfer function is normal in step S2 is as follows:
When the on-chip routing forwarding function is normal, if the corresponding write response is not received within a set time after a write request packet is sent to a self-test responder in another interconnection bare chip, judging that the inter-chip transmission has faults.
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