CN116594692B - Quick register configuration method based on standard state machine function extension - Google Patents
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Abstract
The invention relates to the field of ultra-large-scale digital integrated circuit testing, in particular to a method for rapidly configuring registers based on standard state machine function expansion. The method comprises the following steps: step 1: default state configuration of the state machine from TDI port input 3' b 000; step 2: the instruction register is configured into a double-core working state, and 8-bit instructions are input, namely 8' b10101000 is input from a TDI port in a Shift-IR state; step 3: performing configuration of a scan chain, wherein the chain length of a configuration register is 4; inputting 4-bit configuration signals, namely, 4' b1001 is input from a TDI port for configuration in four states of Update-IR, run-Test/Idle, select-DR and Capture-DR; step 4: inputting test data, performing assignment displacement update on boundary scanning units corresponding to the core particle pins, and verifying whether the scanned output TDO is consistent with an expected value TDO_EXP; the method has the advantage of short configuration time in most application scenes, and has the advantages of low hardware cost and short configuration time.
Description
Technical Field
The invention relates to the field of ultra-large-scale digital integrated circuit testing, in particular to a method for rapidly configuring registers based on standard state machine function expansion.
Background
The core technology is used as a solution for chip calculation force improvement and an advanced process node encountering bottlenecks, and by stacking modularized and miniaturized cores of different processes into chips, higher performance is obtained with lower cost, and meanwhile, the yield of the chips is improved. The core technology has great prospect, and the application and core oriented research of the core technology are more and more extensive. With the characteristics of low cost, high yield, high performance and the like of the core particles, the core particles also have the problems of complex interconnection condition and huge IO number in the stacked chips, and the core particles bring great challenges to testing.
Aiming at the interconnection test problem after core particle binding, the current mainstream test scheme is designed and improved based on three major standards of IEEE 1149, IEEE 1687 and IEEE 1838, and a design configuration circuit is used for controlling the improved functions. Often, for consistency, control of the configuration circuitry is often by way of a new instruction or state machine, but this greatly increases configuration time. For example, when N cores are connected by using a daisy chain, and k configuration registers are in a single core, the configuration time increased by the new instruction is at least O (4n+6), when the new instruction cannot meet the register configuration requirement, the configuration time increased by the new instruction is at most O (4n+kn+6+5), and the configuration time of the state of the new state machine is O (kn+7).
Disclosure of Invention
The invention aims to provide a method for rapidly configuring registers based on standard state machine function expansion, which can be applied to a wide range of scenes in test problems and is used for rapidly configuring related registers. When the standard test structure lacks test efficiency in a specific scene, a configuration register is often required to be added, and extra time is added for configuring the configuration register. Under the scene of an improved interconnection test structure, the method provided by the invention has the advantages of low hardware cost and short configuration time.
In order to solve the technical problems, the invention provides a method for rapidly configuring registers based on standard state machine function expansion, which comprises the following steps:
step 1: default configuration of the state machine from TDI port input 3' b000 in a defined configuration period;
step 2: the instruction register is configured into a double-core working state, and 8-bit instructions are input, namely 8' b10101000 is input from a TDI port in a Shift-IR state;
step 3: performing configuration of a scan chain, wherein the chain length of a configuration register is 4; inputting 4-bit configuration signals, namely, 4' b1001 is input from a TDI port for configuration in four states of Update-IR, run-Test/Idle, select-DR and Capture-DR;
step 4: inputting test data, and carrying out all-0 signal assignment on a scanning chain of the left core chip Chiplet0 and an interconnection output pin of the right core chip Chiplet 1; wherein 24 signals are active-low enable signals;
step 5: after all 0 signal assignment passes the Capture-Shift-Update, namely CSU period, test data are assigned to an Input pin of core chip 0 or chip 1 from an Output pin of core chip 0 or chip 1 through interconnection lines, and 792-bit all 0 data are stored on a scan chain;
step 6: at this time, the updating of the first shift assignment is finished, and when the configuration state is passed in the two shift assignments, the configuration is continuously carried out by inputting 4' b1001 from the TDI port as in the step 3 for maintaining the interconnection test state of the next shift assignment;
step 7: inputting 792-bit test data from the TDI port, wherein the enable signal bit is set to 0 to shift out 792-bit all 0 data stored in step 5; at this time, whether the value of the test data output TDO is all 0 data after the assignment update in the step 5 is checked;
step 8: after bidirectional Update of data, the interconnection test state for maintaining the next shift assignment is configured from the TDI port input 4' b1001 as in step 3, then 792 bit test vectors are input from the TDI port to shift out 792 bit data stored and updated in step 7, a vector opposite to the parity of assignment in step 7 is input, and the value of the test data output TDO is checked;
step 9: after the bidirectional Update of the data, the configuration is carried out from the TDI port to keep the interconnection Test state, and then 588 bit all 0 Test vector is input from the TDI port to shift out the boundary scan cell storage values of the scan chain of the right core chip 1 and the interconnection input pin of the left core chip 0 in the last four configuration states, namely, update-DR, run-Test/Idle, select-DR and Capture-DR before the next shift assignment state is carried out; and checking the value of the test data output TDO;
step 10, writing comparison logic, wherein expected test data is output as TDO_EXP, and the TDO_EXP is given as 1' bX in a non-observation TCK period; comparing the result compare with 1 when the TDO is not matched with the TDO_EXP in each observation TCK period, otherwise, comparing with 0; the 32-bit signal compare_count records the number of cycles for which compare is 1, i.e., the number of match failures since the start of the test.
Preferably, the standard TAP state machine is divided into a configurable state and an unconfigurable state; wherein five states of Capture-DR, update-IR, run-Test/Idle and Select-DR are divided into configurable states, and the remaining states are non-configurable states.
Preferably, the chip 0 and the chip 1 are two identical 768-pin chips, wherein 384 pins are Input and 384 pins are Output; the two die communicate with each other through 192 Input pins and 192 Output pins.
Preferably, each of the intra-die configuration registers has a chain length of 2, and the configuration registers of its chip have a chain length of 4 by interconnecting the left-hand die Chiplet0 and the right-hand die Chiplet 1.
Preferably, assuming that the configuration register chain length is N, 4 cycles need to pass from Update-IR/Update-DR to Capture-DR during normal two shift assignment operations, and if the test circuit is operated in a certain state controlled by the configuration register at this time, the number of configuration state cycles in the state machine needs to be increased to N cycles;
if the test circuit works in a standard state without configuration register control, the default state corresponds to the all-0 configuration register, and the initial value of the register is 0, when the all-0 configuration is performed for the first time or the all-0 configuration is performed for the previous time, the cycle number of the configuration state of the state machine is not required to be increased, and the cycle number of the configuration state is still 4.
Preferably, when the number of configuration state cycles needs to be increased, if 6 configuration cycles are needed at this time, the configuration should be completed in six cycles of Update-IR/Update-DR- > Run-Test/Idle- > Select-DR- > Capture-DR; wherein "- >" indicates a chronological change of state.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a method for rapidly configuring registers based on standard state machine function expansion. The quick configuration register method is based on IEEE 1149.1, and the key is that the functions of TAP FSM specified by IEEE 1149.1 are expanded; the state in the FSM specified by the standard can be divided into an operation Period (CSU Period) and an idle Period (non-CSU Period) by taking the related registers (data register and instruction register) as objects, and the fast register configuration method is to perform configuration operation on the related control registers in a part of the idle Period. The quick configuration method provided by the invention can quickly configure the related registers between two operation periods, does not influence the original data register assignment and instruction register assignment on the basis of not adding additional ports and adding additional instructions and state machine states, and simultaneously carries out quick assignment on the configuration registers. The method is designed for an improved interconnection test structure, but the configuration method provided by the invention has universality and can be widely applied to test structures designed based on IEEE 1149. In the improved interconnection test structure, the configuration registers of the on-chip scan chains can be configured to shorten the configuration time of the scan chains.
Drawings
Fig. 1 is a block diagram of an IEEE 1149.1 standard TAP state machine in the prior art.
Fig. 2 is a state transition diagram of a test flow commonly found in the prior art.
Fig. 3 is a diagram of a typical boundary scan cell and boundary scan chain in the prior art.
Fig. 4 is a block diagram of a fast configuration method for standard TAP state machine function extension provided by the present invention.
Fig. 5 is a state transition diagram of a standard TAP state machine function extension provided by the present invention.
FIG. 6 is a diagram of an interconnect test architecture for a fast configuration register method provided by the present invention.
Fig. 7 is a schematic diagram of a core particle to be tested in an embodiment provided by the invention.
Fig. 8 is a schematic diagram of assignment of step 7 in an embodiment provided by the present invention.
Fig. 9 is a schematic diagram of updating assignment corresponding to step 7 in the embodiment provided by the present invention.
Fig. 10 is a schematic diagram of assignment of step 8 in an embodiment provided by the present invention.
Fig. 11 is a schematic diagram of updating assignment corresponding to step 8 in the embodiment provided by the present invention.
FIG. 12 is a simulated waveform diagram of an improved dual-core interconnect structure for a fast configuration register method provided by the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and the specific examples. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
The basic principle of the method for rapidly configuring the register based on standard state machine function expansion provided by the embodiment of the invention is as follows: the TAP controller state machine specified in IEEE 1149.1 is shown in fig. 1, from which it can be seen that 16 states can be divided into two branches, a data register branch and an instruction register branch, according to control objects; the state during testing can be generally seen as a combination of these two branches. Meanwhile, the test data input can be observed to enter the test circuit only when the state machine is in the Shift state (Shift-DR, shift-IR) to become an effective and meaningful signal; compared with the standard test circuit independently defined by IEEE 1149.1, the newly introduced configuration register and the related control circuit consider selecting part of states in the existing states, so that test data in the states are input into the configuration circuit as effective signals, the state utilization rate of a state machine can be greatly improved, and the configuration time of the test circuit can be shortened.
In a common test flow, state transition of the state machine is shown as a solid line in fig. 2; the data register branch and the instruction register branch have the same point: the in-loop state can be divided into an operation Period (CSU-Period, capture-Shift-Update Period) and an idle Period (non-CSU Period). The state is reasonably selected, so that the signal entering the test data input port in the state can enter the configuration circuit, and the original value is latched when the signal is in the unselected state.
From the aspect of demand, the purpose of the newly added configuration circuit is to control test data, and the current research is that no control instruction register exists, so the configuration method provided by the invention aims to ensure that the configuration register value is correct before each test data shift operation. The following analysis is performed on the selection of the configuration state:
(1) the structure of a typical boundary scan cell and the boundary scan chain as shown in FIG. 3, the ClockBscan signal starts to generate waveforms at Capture-DR, and returns to normal 0 at the end of Shift-DR; it can be seen that the boundary scan cell starts capturing data (non-test data input) in the Capture-DR state, and the test data input signal starts shifting when Shift is valid; the configuration state selected in the method needs to be before Shift, and the data input from the TDI port does not influence the operation of the scan chain.
(2) Meanwhile, it is observed that while the scan chain is still operated in the Update state, the values stored in the boundary scan cells in the scan chain are output to the functional circuit, but the test data is not operated; therefore, the configuration is carried out through the test data input port in the state, and the normal operation of the boundary scan chain is not affected.
(3) Finally, the state transition condition of the state machine in the test process is divided by the branch circuit, and the state machine can work in the data register branch circuit or the instruction register branch circuit before each data register operation. Therefore, according to analysis (2) above, the configuration in the Update-IR state does not affect the normal operation of the scan chain as well, except for the Update-DR state.
In summary, the state machine is divided into a configurable state and an unconfigurable state, and is configured in five states of Update-DR, update-IR, run-Test/Idle, select-DR, capture-DR, so that the normal operation of the boundary scan chain is not affected, and the configuration circuit can be configured with smaller hardware complexity under the condition that the state of the state machine is not increased without adding instructions.
As shown in fig. 4, in the fast configuration register method, a STATE signal indicating the STATE of the STATE machine at present is led out of the tap_main to control the operation of data in the configuration register chain. Based on the above analysis, the configuration register chain can receive data from the Test data input port while sampling shifts on the falling edge of the Test clock while STATE is in the five STATEs of Capure-DR, update-IR, run-Test/Idle, and Select-DR. Meanwhile, in order to meet the requirement of multi-core testing, the data shifted out of the configuration register chain can be output from the Test data output port in five STATEs of Capture-DR, update-IR, run-Test/Idle and Select-DR, namely, a TDO_SEL signal is generated according to the value of STATE, and the front end source of the TDO port is controlled.
In addition, although the method for rapidly configuring the register provided by the invention modifies the original state machine, when the test circuit works in a state without additional configuration, if the working state is opposite to the state that all the configuration registers are set to 0, and the configuration register chain is configured for the first time or is configured to be all 0 last time, no matter how the configuration register chain is transferred according to the normal state, no configuration state period is required to be increased, and the configuration state is set to a value of 0; assuming that the length of the configuration register chain is N, 4 periods need to pass from Update-IR/Update-DR to Capture-DR between normal shift operations, if the test circuit works in a certain state controlled by the configuration register at this time, the number of configuration state periods in the state machine needs to be increased to N periods; if the test circuit works in a standard state without configuration register control, the default state corresponds to the all-0 configuration register, and the initial value of the register is 0, when the all-0 configuration is performed for the first time or the all-0 configuration is performed for the previous time, the cycle number of the configuration state of the state machine is not required to be increased, and the cycle number of the configuration state is still 4.
It should be noted that, when the number of configuration state cycles needs to be increased, in order to avoid logic confusion in the standard structure specified by IEEE 1149.1 caused by adding part of states, at the same time, run-Test/Idle and Select-DR are the necessary states in the multiple shift process, where the Run-Test/Idle states are self-circulatable states, so in the method, the period of the configuration states is increased only by adding the Run-Test/Idle states; that is, if 6 configuration cycles are required at this time, the configuration should be completed in six cycles of Update-IR/Update-DR- > Run-Test/Idle- > Select-DR- > Capture-DR.
The fast configuration register method proposed by the present invention, shown in fig. 5, is applied to a modified interconnect test structure, as shown in fig. 6. The rapid configuration steps of the configuration registers in the architecture, and the test flow, will be described in detail with respect to the state transition diagram based on standard TAP state machine functional extensions described in fig. 5, and the overall test architecture diagram shown in fig. 6.
In the embodiment of the invention, in the improved interconnection test structure, the chain length of a configuration register in a single chip of a test circuit is 2, and the chain length of the configuration register of a chip is 4 because the actual scene is that 2 chips are interconnected; the default state of the configuration registers, i.e. the configuration registers are all set to 0, the test structure can simultaneously perform bidirectional transmission, i.e. the test of the interconnection condition. As shown in fig. 7, the test object is two identical 768-pin chips, wherein 384 pins are Input and 384 pins are Output; the two die communicate with each other through 192 Input pins and 192 Output pins.
Further, the method for quickly configuring the register based on standard state machine function expansion provided by the embodiment of the invention specifically comprises the following steps:
step 1: the state opportunity goes through a configuration state before configuring the instruction register; since this is the first time configuration is performed and the next operation is to configure the instruction register, it is a standard state that does not need to be controlled by the configuration register, and in the configuration state, only 3' b000 needs to be input from the TDI port;
step 2: the dual-core working state is configured through the instruction register, an 8-bit instruction is input, and the 8' b10101000 is input from TDI in a Shift-IR state according to a specified input instruction in the improved interconnection test structure;
step 3: the configuration of a scanning chain is carried out, and the chain length of a configuration register is 4 under a double-core interconnection scene; inputting a 4-bit configuration signal, wherein the 4-bit configuration signal is 4' b1001 according to the specification of the improved interconnection test structure for performing interconnection test states; according to the analysis, the configuration is carried out in the Capture-DR state and the first three states thereof, namely, the configuration is carried out in four states of Update-IR, run-Test/Idle, select-DR and Capture-DR; as can be seen from fig. 4, in the configuration state, the configuration scan chains of different die are in the connected state, so that the four states are configured from TDI input 4' b1001;
step 4: inputting test data, in step 3, configuring the intra-core scan chain so that only the boundary scan cell where the interconnection port of two cores is located is connected to the scan chain, in the verification scheme of the invention, firstly, all 0 s are assigned to the scan chain of the left core and the interconnection output pin of the right core (wherein 24 low-valid enable signals exist);
step 5: step 4, after the assignment is performed through a CSU period (Capture-Shift-Update), the special design of the improved interconnection test structure is performed, test data is assigned from an Output pin of interconnection to an Input pin of a corresponding core particle through an interconnection line, and at the moment, values stored by 792 BSCs on a scanning chain are all 0;
step 6: at this point, the updating of the first shift assignment is finished, and when the configuration state is passed in the two shifts, step 3 is performed to continue to input 4' b1001 from TDI in order to maintain the interconnection test state of the next assignment shift;
step 7: inputting 792-bit test data, shifting out 792-bit all-0 data stored in the step 5, and inputting 792-bit test vectors (enabling signal bits are endowed with 0) through TDI (time delay integration), wherein the specific assignment situation is shown in FIG. 8; at this time, whether the test data output TDO is all 0 data after assignment updating in the step 5 is checked;
step 8: in the same step 5-7, the theoretical process of the data bidirectional Update is shown in fig. 9; after the Update of the data, to maintain the interconnect test state of the next assignment shift, when the configuration state is passed in two shifts, step 3 is performed, configuration is performed from the TDI input 4' b1001, then the 792-bit data stored and updated in step 7 is shifted out from the 792-bit vector of the TDI input, and a vector opposite to the assignment parity of step 7 is input; the specific assignment is shown in fig. 10; and detecting whether the test data output TDO is the value indicated in fig. 9 according to fig. 9;
step 9: in the same step 5-7, the theoretical process of the data bidirectional Update is shown in FIG. 11; after the data bidirectional Update, before the next entry into the shift state, in the last four configuration states, configuration is performed from TDI input 4' b1001 to maintain the interconnect test state, then from TDI input 588 bit all 0 test vector to shift out the scan chain of the right side core and the boundary scan cell memory value of the interconnect input pin of the left side core; and detecting test data output according to fig. 11;
step 10: sorting the test data input and theoretical output data, and sorting the tables as shown in table 1;
step 11: writing comparison logic, wherein expected test data is output as TDO_EXP, and in a non-observation TCK period, the TDO_EXP is given as 1' bX; comparing the result compare with 1 when the TDO is not matched with the TDO_EXP in each observation TCK period, otherwise, comparing with 0; the 32-bit signal compare_count records the number of cycles with compare being 1, i.e. the number of matching failures from the beginning of the test;
after the tb file is written according to the steps and simulated and verified, the key signal waveforms are shown in fig. 12; wherein the two pairs of scan_out_sel, group1_bscan_in_sel signals are newly added configuration registers in the two die, respectively, and the STATE signal indicates the STATE of the current tap_fsm operation.
From the figure it can be observed that the newly added configuration register of the dual core is successfully assigned 4' b1001, while the test period is not increased with respect to the standard test flow.
The rapid register configuration method of the invention can be compatible with standard test (i.e. default test method, configuration register is all 0) and optimized test (i.e. test controlled by added configuration register); in the default test method with the configuration register of all 0, when the configuration is configured for the first time or the previous time to be all 0, no matter the length of the configuration register chain is the same as that of the standard test, no configuration period is required to be increased, and in most cases, the process period number in the standard test is 4, and 0 is input according to the original state transition process.
In the Test after optimization, when the length of the configuration register chain is greater than 4, namely the default configuration period is insufficient, through the analysis, the invention proposes to increase the Run-Test/Idle state which is necessary and can be circulated by itself, so that the length of the configuration period is enough to configure the configuration register chain.
Taking the chain length of the configuration register as 6 as an example, when actually writing the Test vector, as in step 3, step 6, step 8 and step 9, before the Test shift of each optimization Test, the Run-Test/Idle state is added, so that the configuration period is six periods of Update-IR/Update-DR- > Run-Test/Idle- > Select-DR- > Capture-DR, and the configuration register is configured to complete the optimization Test.
Under the multi-core scene, as the configuration registers have connection conditions and no additional ports are added, the configuration register chains of different cores are still connected through TDO; to meet the need for shift of the connection transmission between the configuration register chains of different core grains, it is proposed to generate the tdo_sel signal by means of the STATE machine STATE signal, which, when active, causes TDO to originate from the configuration register chain output.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (6)
1. A method for quickly configuring registers based on standard state machine function extension, comprising the steps of:
step 1: default configuration of the state machine from TDI port input 3' b000 in a defined configuration period;
step 2: the instruction register is configured into a double-core working state, and 8-bit instructions are input, namely 8' b10101000 is input from a TDI port in a Shift-IR state;
step 3: performing configuration of a scan chain, wherein the chain length of a configuration register is 4; inputting 4-bit configuration signals, namely, inputting 4' b1001 from a TDI port for configuration in four states of Update-DR, run-Test/Idle, select-DR and Capture-DR;
step 4: inputting test data, and carrying out all-0 signal assignment on a scanning chain of the left core chip Chiplet0 and an interconnection output pin of the right core chip Chiplet 1; wherein 24 signals are active-low enable signals;
step 5: after all 0 signal assignment passes the Capture-Shift-Update, namely CSU period, test data are assigned to an Input pin of core chip 0 or chip 1 from an Output pin of core chip 0 or chip 1 through interconnection lines, and 792-bit all 0 data are stored on a scan chain;
step 6: at this time, the updating of the first shift assignment is finished, and when the configuration state is passed in the two shift assignments, the configuration is continuously carried out by inputting 4' b1001 from the TDI port for maintaining the interconnection test state of the next shift assignment;
step 7: inputting 792-bit test data from the TDI port, wherein the enable signal bit is set to 0 to shift out 792-bit all 0 data stored in step 5; at this time, whether the value of the test data output TDO is all 0 data after the assignment update in the step 5 is checked;
step 8: after the data bidirectional Update, to maintain the interconnection test state of the next shift assignment, when the configuration state is carried out in the two shift assignments, 4' b1001 is input from the TDI port for configuration, 792 bit test vectors are input from the TDI port to shift out 792 bit data stored and updated in the step 7, vectors opposite to the assignment parity in the step 7 are input, and the value of the test data output TDO is checked;
step 9: after the bidirectional Update of the data, before the next shift assignment state is entered, the configuration is performed from the TDI port input 4' b1001 to keep the interconnection Test state, and then from the TDI port input 588 bit all 0 Test vector to shift out the boundary scan cell storage values of the scan chain of the right-side core chip 1 and the interconnection input pin of the left-side core chip 0 in the last four configuration states, namely, update-DR, run-Test/Idle, select-DR and Capture-DR; and checking the value of the test data output TDO;
step 10: writing comparison logic, wherein expected test data is output as TDO_EXP, and in a non-observation TCK period, the TDO_EXP is given as 1' bX; comparing the result compare with 1 when the TDO is not matched with the TDO_EXP in each observation TCK period, otherwise, comparing with 0; the 32-bit signal compare_count records the number of cycles for which compare is 1, i.e., the number of match failures since the start of the test.
2. The method for quickly configuring registers based on standard state machine function extension according to claim 1, wherein the standard TAP state machine is divided into a configurable state and an unconfigurable state; wherein five states of Capture-DR, update-IR, run-Test/Idle and Select-DR are divided into configurable states, and the remaining states are non-configurable states.
3. The method for quickly configuring registers based on standard state machine function extension according to claim 1, wherein said chip 0 and chip 1 are two identical 768-pin chips, wherein 384 pins are Input and 384 pins are Output; the two die communicate with each other through 192 Input pins and 192 Output pins.
4. A fast configuration register method based on standard state machine functional extension as claimed in claim 3, wherein each intra-die configuration register chain length is 2, and the configuration register chain length of its chip is 4 by the interconnection of the left-hand die chip 0 and the right-hand die chip 1.
5. A method for fast configuring registers based on standard state machine functionality extension as claimed in any one of claims 1-4, wherein:
assuming that the length of the configuration register chain is N, 4 periods need to pass from Update-IR/Update-DR to Capture-DR during normal two shift assignment operations, if the Test circuit works in a certain state controlled by the configuration register at this time, the number of configuration state periods in the state machine needs to be adjusted to N periods by increasing the number of Run-Test/Idle states;
if the test circuit works in a standard state without configuration register control, the default state corresponds to the all-0 configuration register, and the initial value of the register is 0, when the all-0 configuration is performed for the first time or the all-0 configuration is performed for the previous time, the cycle number of the configuration state of the state machine is not required to be increased, and the cycle number of the configuration state is still 4.
6. The method for quickly configuring registers based on standard state machine function extension according to claim 5, wherein: when the number of configuration state cycles needs to be increased, if 6 configuration cycles are needed at this time, the configuration should be completed in six cycles of Update-IR/Update-DR- > Run-Test/Idle- > Select-DR- > Capture-DR.
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