JPH05181780A - Input/output control device and its method - Google Patents

Abstract

PURPOSE:To improve the through-put of a microprocessor in an I/O control device by informing a status signal and retrial interval data without returning response status to a central processing unit (CPU) when the I/O control device can not temporarily execute an instruction in the bus transfer control system of two cycles in a system. CONSTITUTION:When an instruction applied from the CPU 10 can not be executed at the time of informing the status of the microprocessor 3 from the microprocessor 33 to a common bus control part 31 provided with an I/O instruction receivable/unreceivalbe state answering means by means of a status informing signal 34, the control part 31 informs the status signal and retrial interval data directly to the CPU 10 to allow the CPU 10 to execute a RETRY request.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data input / output control system with an external device by confirming a command reception response between a central processing unit connected to a common bus and an input / output control unit.

[0002]

2. Description of the Related Art FIG. 3 shows a schematic diagram of a conventional input / output control device, and FIG. 4 shows data of a system control signal.

In FIG. 3, an input / output control device 30 is connected to a common bus 20 connected to the central processing unit 10. In the input / output control device 30, the common bus 2
A common bus control unit 31 for interfacing with 0,
There are a microprocessor 33 having an instruction executability response means 36 connected to the common bus control unit 31 via an internal bus 32, and a control circuit 35 for interfacing with an external input / output device 40. This input / output control device 3
0 executes various kinds of processing on the instruction sent from the central processing unit 10 by the built-in microprocessor 33.

Conventionally, the microprocessor 33 in the input / output control unit 30 operates from the central processing unit 10 while performing data processing with the external input / output unit 40 via the control circuit 35. However, the common bus control unit 31 does not know the state of the microprocessor 33 and executes it when an input / output instruction is issued from the central processing unit 10. The availability report (ACK signal shown in FIG. 4) is notified to the central processing unit 10 through the system control signal 21, and the microprocessor 33 is notified of the input / output command.

Therefore, the microprocessor 33 which has received the above-mentioned input / output instruction interrupts the processing with the input / output device 40, and gives a status indicating short busy to the newly received instruction through the common bus 20 to the central processing unit. 1
I was reporting to 0.

[0006]

However, in the short-busy notification method of the conventional input / output control device, although it is known that the microprocessor 33 cannot temporarily execute the input / output instruction, After returning an ACK with the system control signal 21, a bus cycle is generated for the common bus 20 and a response status is transferred using the bus, so that a wasteful bus cycle is used, and the microprocessor 33 responds. It was necessary to interrupt the operation.

Therefore, according to the present invention, in a system for performing a 2-cycle bus transfer control, when the input / output control device is temporarily unable to execute an instruction, a status signal is sent without returning a response status to the central processing unit. The purpose is to improve the throughput of the microprocessor of the I / O controller by reporting the retry interval data.

[0008]

A first solution for solving the above-mentioned problems is to connect to a central processing unit by a common bus including a system control signal, and to further provide data information with an external input / output device. A control circuit for exchanging data, a common bus control unit, and an internal bus connected to the common bus control unit and the control circuit for decoding the input / output command of the central processing unit received via the common bus control unit. In the input / output control device, which comprises a microprocessor having instruction executability response means for reporting the decoding result to the central processing unit, a status notification signal for notifying the self-operation status of the microprocessor is sent to the microprocessor. Is output to the common bus control unit, is provided in the common bus control unit, and waits for re-execution of the data input / output instruction of the central processing unit. The status notification signal is valid when a retry data buffer for storing information set by the microprocessor and a data input / output command to / from the external input / output device is received from the central processing unit. If there is, a notification of refusal of acceptance of the data input / output instruction is given, and if the status notification signal is invalid, an input / output instruction acceptability response means for notifying acceptance of the data input / output instruction is provided to the common bus controller The input / output control device provided, and a retry processing means for reading information from the retry data buffer when receiving the acceptance refusal and performing a retry process of a data input / output command after a predetermined time by this information is the central processing unit. Is prepared for.

A second solution for solving the above problems is to connect a central processing unit with a common bus including a system control signal, and further, to provide a control circuit for exchanging data information with an external input / output device. An input / output of the central processing unit, which is connected to the common bus control unit including an input / output command acceptance / rejection response unit and the internal bus with the common bus control unit and the control circuit, and is received via the common bus control unit. In an input / output control method of an input / output control device comprising a microprocessor equipped with an instruction executability response means for decoding an instruction and reporting the decoding result to the central processing unit, input from the microprocessor to the common bus control unit The status notification signal for notifying the self-operation status of the microprocessor and the data input / output command of the central processing unit. The common bus control unit is provided with a retry data buffer that stores execution wait time information and is set by the microprocessor, and a data input / output command from the central processing unit to the external input / output unit is transmitted. Upon reception, if the status notification signal is valid, the rejection of acceptance of the data input / output instruction is notified, and if the status notification signal is invalid, acceptance of the data input / output instruction is accepted. When the central processing unit receives the refusal of acceptance, the central processing unit reads information from the retry data buffer and performs a retry process of a data input / output command after a predetermined time by this information.

A third means for solving the above-mentioned problems is to connect a central processing unit with a common bus including a system control signal, and a control circuit for exchanging data information with an external input / output device. An instruction executability response step of decoding an input / output instruction of the central processing unit which is connected to the control circuit by an internal bus and received via a common bus control step, and reporting the decoding result to the central processing unit. In an input / output control method of an input / output control device comprising a microprocessor including, a status notification information storage step for holding a self-operation status of the microprocessor, which is given from the microprocessor to the common bus control step, Re-execution waiting time information of the data input / output instruction of the central processing unit, When the retry data storing step of storing information set by the processor and the data input / output command with the external input / output device are received from the central processing unit, the information stored in the state notification information storing step is valid. The data input / output command acceptance refusal, and if the information stored in the status notification information storing step is invalid, the data input / output command acceptability response step When the central processing unit receives the acceptance refusal, it reads the information stored by the retry data storing step, and the information processing unit performs the retry processing of the data input / output command after a predetermined time. It is characterized by being able to go.

[0011]

FIG. 1 shows an embodiment of the present invention.

The central processing unit 10 includes a common bus 2 including a system control signal 21 for controlling the transfer sequence.
0 is connected to the common bus control unit 31 of the input / output control device 30. The common bus control unit 31 includes an input / output command acceptability response unit, and the common bus control unit 31 is connected to the microprocessor 33 and the control circuit 35 by the internal bus 32, and the common bus control unit 31.
Are connected to the microprocessor 33 by the status notification signal 34. The microprocessor 33 is a microprocessor which decodes an input / output instruction from the central processing unit 10 and reports the result to the central processing unit 10. The status notification signal 34 is a status notification signal for notifying the common bus control unit 31 of the status of the microprocessor 33. The control circuit 35 controls the data information transfer operation between the microprocessor 33 and the input / output device 40.

FIG. 2 shows the bit pattern of the system control signal in this embodiment. Bit 0 and bit 1 are shown.
2 bits of A indicating that the input / output instruction from the central processing unit 10 is accepted by the input / output control unit 30.
CK, NACK1 indicating not accepted, short busy indicating that the input / output control device 30 cannot temporarily execute the instruction, and in the case of short busy, retry to the data bus in the common bus 20 Notify the interval.

In the information processing device using the 2-cycle bus transfer control system, when the central processing unit 10 issues an input / output command to the input / output control device 30, the input / output control device 30 receives the input / output command, When it is operable, the common bus control unit 31 notifies the central processing unit 10 of ACK (ACK shown in FIG. 2) by the system control signal 21, and also notifies the microprocessor 33 of the input / output command. Upon receiving the input / output command, the microprocessor 33 reports the response status to this command to the central processing unit 10 via the common bus control unit 31, and executes the command.

When the input / output control unit 30 is in operation, the microprocessor 33 enables the BUSY bit by the status notification signal 34 of the common bus control unit 31 so that the common bus control unit 31 can operate. The command was not accepted by the system control signal 21 in response to the I / O command from the
1) is notified to the central processing unit 10 and the instruction is interrupted.

The microprocessor 33 in the input / output control unit 30 temporarily receives an instruction from the central processing unit 10 while performing data transfer processing with the input / output unit 40 via the control circuit 35. Since the state becomes unacceptable (short busy), the microprocessor 33 enables the short busy bit of the common bus control unit 31 by the status notification signal 34 and sets the retry wait time in the data buffer of the common bus control unit 31. set.

When the short busy bit is valid,
When an input / output command is issued from the central processing unit 10 to the input / output control unit 30, the common bus control unit 31 causes a short busy (short busy shown in FIG. 2) by the system control signal 21, and further the common bus 20. The retry waiting time is notified to the central processing unit 10 by the data signal of.

The central processing unit 10 that has received the short busy notification reissues the instruction after the retry waiting time requested by the input / output control unit 30. Microprocessor 3
When the data transfer process with the input / output device 40 is completed via the control circuit 35, the short busy state is released and the input / output command can be processed. The short busy bit and the data buffer of the control unit 31 are cleared.

When the central processing unit 10 issues an input / output command after the short busy is released, the common bus control unit 31 notifies the central processing unit 10 of an ACK through the system control signal 21 (see FIG. 2). ACK), and notifies the microprocessor 33 of the input / output command sent from the central processing unit 10. When the microprocessor 33 receives the input / output instruction,
The firmware judges whether the data of this command can be executed, reports the response status to the central processing unit 10, and if it can execute this input / output command.

[0020]

As described above, according to the present invention, the microprocessor responds to the common bus control unit of the input / output control device having the input / output command acceptance / rejection response means by the status notification signal to cause its own short busy signal. Along with notifying the status,
The retry time is set in the data buffer of the common bus control unit. Thus, in response to an input / output command from the central processing unit, the common bus control unit can notify the central processing unit of the short busy directly by the system control signal. In addition, the retry waiting time can be designated to the central processing unit, short busy can be reported without wasting bus cycles, and retry of input / output instructions can be quickly re-executed. Therefore, it is possible to efficiently use the common bus and increase the throughput of the entire system without interrupting the operation of the microprocessor of the input / output control device.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing a data state of a system control signal of the present embodiment.

FIG. 3 is an explanatory diagram of a conventional example.

FIG. 4 is a diagram showing a data state of a system control signal in a conventional example.

[Explanation of symbols]

 10 Central Processing Unit 20 Common Bus 30 Input / Output Control Device 21 System Control Signal 31 Common Bus Control Unit 32 Internal Bus 33 Microprocessor 34 Status Notification Signal 35 Control Circuit 36 Command Executability Execution Response Means 40 Input / Output Device

Claims (3)

[Claims] 1. A control circuit, which is connected to a central processing unit by a common bus including a system control signal, and which exchanges data information with an external input / output device, a common bus control unit, and the common bus control unit. And an instruction executability response means for decoding the input / output command of the central processing unit, which is connected to the control circuit by an internal bus and received via the common bus control unit, and reports the decoding result to the central processing unit. In an input / output control device including a microprocessor, the microprocessor outputs a status notification signal for notifying a self-operation status of the microprocessor to the common bus control unit, and the common bus control unit is provided. , The re-execution waiting time information of the data input / output instruction of the central processing unit, which is set by the microprocessor. A retry data buffer for storing information to be stored, and a data input / output command with the external input / output device from the central processing unit, if the status notification signal is valid, the data input / output command is rejected And an input / output command acceptability response means for notifying acceptance of the data input / output instruction when the status notification signal is invalid, the input / output control device having the common bus control unit, and the acceptance refusal. Receiving the information, the information is read from the retry data buffer, and the central processing unit is provided with a retry processing means for performing a retry processing of a data input / output instruction after a predetermined time by this information. apparatus. 2. A common bus, which is connected to a central processing unit by a common bus containing a system control signal, and further comprises a control circuit for exchanging data information with an external input / output device, and an input / output command acceptability response means. A bus control unit is connected to the common bus control unit and the control circuit by an internal bus, and decodes an input / output command of the central processing unit received via the common bus control unit to be decoded by the central processing unit. In an input / output control method of an input / output control device comprising a microprocessor having instruction execution propriety response means for reporting a result, the self-operation state of the microprocessor input from the microprocessor to the common bus control unit is notified. And a status notification signal for performing the re-execution waiting time information of the data input / output instruction of the central processing unit, The common bus control unit is provided with a retry data buffer for storing information set by a clock processor, and when the data input / output command with the external input / output device is received from the central processing unit, the status notification signal is valid. If there is, the notification of refusal of acceptance of the data input / output instruction is notified, and if the status notification signal is invalid, the common bus control unit notifies acceptance of the acceptance of the data input / output instruction, the central processing unit, An input / output control method characterized in that, upon receipt of a refusal of acceptance, information is read from the retry data buffer, and retry processing of a data input / output instruction is performed after a predetermined time by this information. 3. A control circuit connected to a central processing unit by a common bus containing a system control signal, and further connected to a control circuit for exchanging data information with an external input / output device, and connected to this control circuit by an internal bus. An input / output control unit consisting of a microprocessor including an instruction executability response step for decoding the input / output instruction of the central processing unit received through the common bus control step and reporting the decoding result to the central processing unit. In the output control method, a state notification information storing step for holding the self-operating state of the microprocessor, which is given from the microprocessor to the common bus control step, and a re-execution of a data input / output instruction of the central processing unit. Stores latency information that is set by the microprocessor. When a retry data storage step and a data input / output command with the external input / output device are received from the central processing unit, the data input / output command is accepted if the information stored in the status notification information storage step is valid. The common bus control step includes an input / output command acceptance / rejection response step of notifying refusal and of notifying acceptance of the data input / output instruction when the information stored in the status notification information storing step is invalid. When the central processing unit receives the acceptance refusal, the central processing unit reads the information stored in the retry data storage step, and performs a retry process of a data input / output command after a predetermined time by this information. Input / output control method.