JPH03139751A - Dma controller for communication with priority decision function - Google Patents

Abstract

PURPOSE:To improve the communication efficiency by confirming the request of a DMA channel with high priority while performing DMA transfer in predetermined burst size units and performing switching to the DMA request of a channel with higher priority when there is the request. CONSTITUTION:Plural DMA(direct memory access) requests are given priority levels in advance and a transfer means 203 transfers data of burst size which is predetermined by single-time DMA transfer. Every time single DMA burst transfer ends, a priority decision means 201 checks the priority levels of effective DMA requests and the channel is switched to the channel with top priority. Data transfer is carried out over the switched channel and this is repeated. Consequently, the efficiency of the data transfer can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a communication DMA controller having a priority determination function.

(Prior Art) Generally, in data communication, data is transferred at high speed (DMA (direct memory access) transfer is often performed. In conventional DMA transfer, transfer assigned to a certain channel is often performed. data block for
Perform priority transfer on a channel-by-channel basis. Therefore, even if the burst size is set in the DMA to be smaller than the data block for transfer, the channel will not be switched each time even if one burst transfer is completed. When all the transfer data blocks allocated to that channel have been transferred, the channel is switched to the next highest priority channel and DMA transfer is performed.

(Problems to be Solved by the Invention) Since the conventional DMA controller is configured as described above, when it is used for communication data transfer, the following problems occur when transmission and reception overlap.

For example, even if communication data reception begins immediately after transmission DMA starts, the channel cannot be switched to reception DMA mode until all transmission data has been transmitted. Therefore, if the data length of the transmitted data is long, there is a possibility that the received data may be missed. In addition, the conditions for failing to receive received data are as follows:
It varies depending on the size of the reception FIFO (first-in-first-out) buffer and the size of the transmission data that is being transmitted at the same time. If reception fails, the other station retransmits the data from the upper layer.

As a result, data transfer time becomes longer and transfer efficiency deteriorates.

The present invention has been made in view of the above-mentioned drawbacks of the prior art.The purpose of the present invention is to send communication data divided into predetermined burst sizes in DMA transfer, and to transfer all DMA data each time one transfer is completed. The purpose of the present invention is to determine the priority of a transfer request, switch to a channel with a higher priority, perform DMA transfer, and repeat this process to transfer data, thereby improving the efficiency of data transfer.

[Structure of the invention]

(Means for Solving the Problems) In order to achieve the above object, the first advantage of the present invention is to provide a communication DMA controller having a priority determination function. A communication DMA controller that transfers data between memories by DMA transfer, has a plurality of channels, each channel has a FIFO used for the data transfer, and by switching channels, data can be transferred from one memory to another. A communication DMA controller that transfers data to another memory and from another memory to a certain memory, a transfer means that transfers data of a predetermined burst size based on a DMA request with the highest priority;
Each time the transfer by the transfer means is completed, the DM
A device comprising: priority determining means for determining the priority of valid A requests; and channel switching means for switching the channel in accordance with the DMA request determined to have the highest priority by the priority determining means. Constructed as.

Further, in the communication DMA controller having the second priority determination function of the present invention, in the first DMA controller, during the data accumulation time in the FIFO during the data transfer, the communication DMA controller DMA that executes DMA requests for exclusive working memory
It is configured as having execution means.

(Function) Multiple DMA (direct memory access) requests are prioritized in advance. With the transfer means, one D
Data of a predetermined burst size is transferred by MA transfer. Each time one DMA burst transfer is completed, the priority determining means checks the priority of the valid MA request.

The channel is switched to the channel corresponding to the highest priority DMA request. Data transfer takes place on the switched channel. This is repeated.

Furthermore, during data storage in the FIFO during data transfer, a DMA request for the working memory is executed.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, particularly showing the basic blocks of a communication controller. This communication controller is composed of five blocks. The first block (101) is a bus interface block 101 (Bus I/ P). The second block (102) is a DMA control block 102 (DMAC) that operates according to internal DMA firmware and performs intelligent control such as switching the three DMA channels in priority order.
It is. The third block (103) is an FI FO/RAM block 1 that uses a plurality of communication data buffers as automatic buffer locations to improve communication data transfer efficiency.
03 (FIFO/RAM). Fourth block (1
05) is a small CPU block 105 (Small C
PU). The fifth block (104) is a network interface block 104 (Network I/P) that controls communication such as assembling and recognizing communication frames and detecting various communication errors. The bus interface block 101 provides a 24-bit address to a memory circuit (not shown).
The address/data buffer register (Addr) inputs and outputs 16-bit data.
ess /Data Buf'l'er Register
er) and a communication register.The communication register sends a bus request signal BREQ, read signal RD, and write signal WR to the memory circuit, and receives a bus acknowledge signal BACK from the memory circuit. wear. Also, from the host processor, a chip select signal C8 and a read signal RD are sent for I10 access.

The write signal WR is received. DMA control block 102 is a DMA micro control (D
HA Micro Control Logic) and
DMA Firmware ROM
re ROM) and address count/data alignment (Address Count & Data Al
ignment) and DM with 2Port RAM
A control register (DMA Control R
gister). Also, FIFO/RAM
103, a plurality of transmission FIFOs (TX-FIFOs);
a plurality of reception FIFOs (RX-FIFOs);
Working memory with Port RAM (Mark
ing Méraory). The small CPU block 105 also has a communication register interface (ComlIunlcatlonRe).
glsuters Interf'1ce) and internal firmware ROM (Internal F
irmware ROM) and Execution Control
, X register (X-Reg) and Y register (Y-R
eg) and an arithmetic unit (ALU) connected to the internal bus interface (InternalBu
s Interface ) and working register (
Work-8-1ng Registers). On the other hand, network interface (Network l/F
) 104 is a 6-byte transmission FI
O (TX-FIFO), 6-byte receive FIFO (RX-FIFO), and delimiter generator/detector (Delimltor Generator & Delimiter).
tector) and a protocol timer (Protoc
ol Timer) and a parallel/serial converter (P) that sends data to a physical layer data transmitting/receiving circuit (not shown).
The parallel/serial conversion unit (serial to parallel) receives data from the physical layer data transmission/reception circuit. The DMA control register of the DMA control block 102, the transmission/reception FIFO of the FIFO/RAM block and network interface 104, and the internal bus interface of the small CPU block 105 are connected to a 16-bit internal bus (Inte
(nal Bus). Further, the DMA address count/data regulation of the DMA control block 102 and the FIFO/RAM 103 are connected by a dedicated 16-bit data bus. Also DMA
The DMA address count/data tailoring of the control block 102 is performed using the DMA in the FIFO/RAM 103.
Outputs mode signal and strobe signal. Also, DMA
Between the DMA microcontrol of the control block 102 and the execution control of the small CPU block 105, DMA request (DMA Request) and DMA completion (DMA
Complete) is exchanged. Furthermore, 16-bit data is exchanged between the communication register of the bus interface block 101 and the communication register interface of the small CPU block 105.

Figure 2 shows the DMA control block 1 shown in Figure 1.
02 is a basic block diagram. This DMA control block 102 has three basic blocks. The first block (201) receives a DMA request signal, performs DMA
This is a DMA priority determination unit 201 that performs intelligent control such as output of a completion signal and burst steal processing of DMA channels according to priorities. The second block (
202) generates an external memory address (not shown);
Interpretation of communication frame length, burst size, etc., and 2.
A DMA data storage unit 202 receives and transfers DMA data to and from the small CPU block 105 using a port RAM.

The third block (203) is a DMA transfer control unit 203 that requests the host processor for bus ownership through the bus interface block 101, outputs a strobe signal for data input/output to the PIFORAM, and controls the DMA data transfer cycle. It is. The DMA priority determination unit 201 sends signals such as transmission DMA completion, reception DMA completion, and RAM mode DMA completion to the small CPU block 10.
DMA firmware ROM/command instruction deck 7 unit 24 (DMA FI
rmware ROM & In5truction
Deco-der) and small CPU block 10
A DMA request reception register 205 receives and transmits DMA requests from 5 to 1, receive DMA requests, RAM mode DMA requests, and read/write (RD/WR) signals, and a small CP.
Transmission FFO-TH (transmission FI
FO-THRESHOLD), receiving FI FO-T
DM that accepts signals such as H (reception FIFO-THRESHOLD), reception FIFO-empty, and reception completion.
A condition determination circuit 206. The DMA data storage unit 202 includes a communication frame address counter, a RAM data address counter, a transmission frame length down counter, a reception frame length down counter, and a RAM
Counters such as data length down counter, DMA burst size down counter, and DMA data 2
Port RAM (RAM Data 2port-RA
M) and an internal bus interface. Also,
The DMA data storage 202 has a bus interface block 101 and a 24-bit address (Address).
) line and a 16-bit data line. On the other hand, the internal bus 12-interface uses a 5-bit address (Address
ss) line and a 16-bit data line to the internal bus. DMA transfer control unit 203
converts the DMA mode signal and strobe signal to FIFO
/FIFO access signal generation circuit to send to RAM103, bus request signal (BUSRQ), read/write signal (RD/WR), next address (Next A)
ddress) request, next data (NextDat)
a) Transfer signals such as requests to the bus interface block 10
1, transmits and receives a DMA request signal from the DMA firmware ROM/instruction decoder section 204, and DMA
D supplies a DMA completion signal to the condition determination circuit 206
MA cycle control state machine. In addition, D
A data length 0 signal detected by various counters is sent from the MA data storage unit 202, and the DMA cycle control state machine of the DMA transfer control unit 203 and the DMA
The signal is input to the DMA condition determination circuit 206 of the priority determination section 201. Further, from the DMA cycle control state machine of the DMA transfer control unit 203, the DMA data storage unit 2
Count signals for various counters of 02 are sent out.

FIG. 3 is a block diagram showing in detail the configuration of the DMA firmware ROM/instruction decoder section 204 of FIG. 2. As shown in FIG.

In FIG. 3, a multiplexer (MPX) 301 selects either the next address 311 or the jump address 310 and sends out the selected address 313. Selected address 313 from multiplexer 301 is latched into address register 302. Firmware RO
M (PlriWare ROM) 303 outputs data corresponding to address 314 output from address register 302, that is, instruction code 315.

The instruction latch register 304 is a firmware ROM 3
The instruction code 315 output from 03 is latched. Address increment (+1) 306 adds 1 to address 314 output from address register 302 to generate address 311 at the next address. The instruction decoder 305 decodes the instruction code 316 output from the instruction latch register 304 and outputs a control signal 317 for setting/resetting flags, pig transfer between registers, detecting jump conditions, etc. A jump (JLIMP) signal 308 that is input when a jump condition is satisfied based on a jump command from the control signal 317 is an MPX
301 selects the jump address 310, is latched by the register 307 for one clock (CLK), and is given to the instruction decoder 305 for one clock as an instruction decode enable signal 309,
The control signal 317 output by the instruction decoder 305 is invalidated.

Note that a part of the instruction code 316 output from the instruction latch register 304 is given to the multiplexer 301 as a jump address 310. Further, the address register 302 and the instruction latch register 304 are reset by a reset signal (RESET).

FIG. 4 is an operation timing chart of the DMA firmware ROM/instruction decoder section of FIG. 3. FIG. 4 (A) shows the clock, (B) shows the address 314 output from the address register 302, and (C) shows the clock.
is the firmware ROM 303 that received the address 314.
(D) is the instruction code 316 that is the output of the instruction latch register 304 that received the instruction code 315. (E) is the control signal 317 that is output from the instruction decoder 305 that received the instruction code 316. ,(
F) is a jump signal 30 that is input to the register 307 when a jump condition is satisfied in response to a jump instruction output from the instruction decoder 305, similar to the control signal 317.
8, (G) is an instruction decode disable signal 309 given from the register 307 to the instruction decoder 305.

Selected address 31 output from multiplexer 301
3 is the address register 302 at the rising edge of the clock.
The data is latched into the address 314, outputted as an address 314, and given to the firmware ROM 303. Firmware R
The instruction code 315, which is the output of the OM 303, is output at the falling edge 6 of the clock. The instruction code 315 output from the firmware ROM 303 is latched into the instruction latch register 304 at the rising edge of the clock, and is sent to the instruction decoder 30.
5 and the control signal 3 from its instruction decoder 305.
17 and a jump signal 308 are output.

Note that when a jump condition based on a jump command based on a control signal 317 from the command decoder 305 is satisfied, a jump signal 308 is input. This jump signal 30
8 is latched for one clock by register 307,
This becomes an instruction decode enable signal 309. This signal 3
09 is given to the instruction decoder 305 to invalidate the decoding of the instruction code 316 (jump address) given from the firmware ROM 303 through the instruction latch register 304 in the next clock period.

FIG. 5 shows the DMA request reception register 20 shown in FIG.
5 is a block diagram showing details of the DMA condition determination circuit 206. FIG. As shown in FIG. 5, the DMA request reception register 205 includes a transmission DMA request reception register 501, a reception
It has an MA request reception register 502, a RAM mode DMA request reception register 503, and a read/write signal latch register 504. The transmit DMA request 513 is stored in the transmit DMA request reception register 501, the receive DMA request 514 is stored in the receive DMA request reception register 502, and the RA
M mode DMA request 541 is RAM mode DMA
A read/write signal 515 is sent to the request reception register 503.
are respectively input to the read/write signal latch register 504. A clock signal CLK and a reset signal 511 are input to the transmit DMA request reception register 501, the reception DMA request reception register 502, the RAM mode DMA request reception register 503, and the read/write signal latch register 504, and their respective outputs are as follows. AND circuits 524 and 52 to which the detection signal 510 is input
5.526.527.

The DMA condition determination circuit 206 also determines the transmission DMA suspension flag 505, the transmission DMA execution flag 506, the transmission D
It includes an MA execution flag 507 and a burst size DMA completion flag 508. A reset signal 511 and a set signal 512 are input to each flag, respectively. Furthermore, a burst size DMA completion signal 523 is input to the burst size DMA completion flag 508 . Transmission DMA suspension flag 505, transmission DMA execution flag 506, reception D
The outputs of the MA execution flag 507 and the burst size DMA completion flag 508 are input to AND circuits 528, 529, 530, and 538, respectively, to which the detection signal 510 is input.

Further, the detection signal 510 is transmitted to other AND circuits 531 to 53.
8 is input. The AND circuit 531 receives the transmit DMA data length 0 signal 516, and the AND circuit 532 receives the RA
The M mode DMA data length 0 signal 517 is sent to the AND circuit 533, and the burst size 0 signal 518 is sent to the AND circuit 534 via the logic gate 542 to the receive FIFO.
The empty signal 519 and the reception completion signal 520 are sent to the AND circuit 9.
- 535 has a receive FI via logic gates 543, 544;
FO empty signal 519, reception completion signal 520 and reception FIFO
The threshold signal 521 is sent to the AND circuit 536, the set signal 512 is sent to the AND circuit 537, and the transmission FI signal is sent to the AND circuit 537.
FO threshold signals 522 are each input. Each output signal of AND circuits 524 to 538 is input to OR circuit 545. A jump signal 509 is sent from this OR circuit 545.

In FIG. 5, a transmission DMA request reception register 50
1. Reception DMA request reception register 502, RAM mode DMA request reception register 503, and read/write signal latch register 504 receive various DMA request signals, that is, transmission DMA request 513, reception DMA request 5
14, RAM mode DMA request 541, and read/write signal 515, respectively, and D
After the execution of MA is completed, it is reset by a reset signal 511 based on firmware. Further, the transmission DMA interruption flag 505 is set by a firmware-based set signal 512 to interrupt the transmission DMA when executing the reception DMA that shares a channel. This flag 505 is used for the purpose of saving and resetting data, and is reset by a reset signal 511 when transmission DMA is restarted. The transmit DMA execution flag 506 and the receive DMA execution flag 507 are each set by a set signal 512 based on firmware before execution of the transmit/receive DMA. These flags 506 and 507 are used for sending and receiving DM
This is used for the purpose of interrupting A, preferentially executing RAM mode DMA, and then executing transmitting/receiving DMA again from the interrupted point. These flags 506 and 507 are used for sending and receiving DMA
Upon completion of the firmware-based reset signal 51
It is reset at 1. The burst size DMA completion flag 508 is set by the burst size DMA completion signal 523 when the burst size DMA is completed.
After the firmware is detected, it is reset by a reset signal 511. The registers and flags indicated by reference numerals 501 to 508 and the condition signals indicated by reference numerals 516 to 522 are each logically connected to a detection signal 510 based on a firmware microinstruction, and further summed up by an OR circuit 545 to generate a jump signal. 509. DMA execution is controlled based on this jump signal 509.

Figure 6 shows the DMA control block in Figure 1.
FI is used to perform burst processing on the DMA channel when A requests occur repeatedly.
FIG. 2 is an explanatory diagram showing a transmission/reception FIFO threshold signal output from the FO/RAM using a FIFO diagram.

FIG. 6(A) shows the threshold value of the transmitting FIFO, and FIG. 6(B) shows the threshold value of the receiving FIFO.

Each FIFO has an area of 16 bits x 256 words. In this example, the DMA burst size (B
This example shows a case where 32 bytes are set as the urst 5ize. This burst size is
This is an important value that determines the FIFO threshold value, and the host processor writes it to RAM using DMA, and the small CPU block 105 reads it and writes it to RAM using DMA.
This is a value that can be set externally and written to the FIFO.

First, the threshold value of the transmission FIFO will be explained. In the case of transmission, in particular an underrun in the DMA control block 102 causes the F I FO/RAM
The transmit FIFO of 103 must not be empty. Therefore,
The threshold value is 128 Byte (FIFO
Capacity) -32Byte (Burst value) -96Byte
te (threshold value).

Next, the threshold value of the reception FIFO will be explained. For reception, DMA control block 1
FIFO/RAM103 due to underrun of 02
It is necessary to prevent the receive FIFO from becoming full. Therefore, the threshold value is 32 Bytes (burst value) 23--32 Bytes (threshold value).

Incidentally, the DMA control block 102 executes burst size DMA transfer only when the threshold signal is on, in order to prevent transfer of empty data from occurring if communication data is written or erased.

Table 1 is a table showing the priorities of the three channels, reception DMA, and transmission DMA SRAM mode DMA possessed by the DMA control block of FIG. By the way, the priorities shown in the table are fixed.

4- If multiple requests occur simultaneously when DMA is not being executed for any channel, the requests are accepted according to the priority of the channel. On the other hand, if overlapping requests occur during the execution of one of the channels, the other channels are executed according to the condition that the other channels are executed preferentially after the DMA is started. The timing for switching channels is when execution of burst size DMA ends.

FIG. 8 is a DMA execution timing chart when overlapping DMA requests are processed based on the table shown in Table 1.

Time T■ is the time when the transmission DMA request signal is first accepted and the first burst size f) MA is completed. At that time, the transmit FIFO threshold signal (
C) is on (high) and in a state where DMA transfer of transmission data must be performed. However, received DM
Since the A request signal (D) is coming, interrupt the sending DMA channel and accept the receiving DMA request,
Execute burst size receive DMA.

On the other hand, at time T■, RAM mode DM during reception DMA
An A request has come, but since the receive FIFO threshold signal is on (high), the request is not accepted.

Next, at time T■, the second burst size reception DMA
This is the point at which the At that time, the reception FIFO threshold signal is off (low). The receive DMA channel is interrupted and the RAM mode DMA request is received and executed.

Time T■ is the RAM mode DMA that was accepted at time T■.
This is the point at which the Incoming DM that was interrupted here
Running A again.

At time T■, the reception DMA that was accepted at time T■ has been completed, and the suspended transmission DMA is being executed again.

At time T2, all DMA channels have finished executing.

FIG. 9 shows a basic state transition diagram of the DMA control firmware that controls the sequence of the DMA execution timing chart shown in FIG. 6, in comparison with a conventional case.

(A) of the figure shows state transition in the conventional case, and (B) shows state transition in the present embodiment.

First, a conventional state transition will be explained with reference to FIG. 9(A).

It accepts requests for DMA channels in state SOI and continues in this state until a request is received. If there is a DMA request, the process moves to state SO9, and the DMA start condition is detected. For example, the condition is that the reception FIFO threshold signal of the reception DMA request is on. Then, if the reception FIFO threshold signal is off (L) at the end of the parse size DMA, the condition is incorrect while the state SO9 remains. If the DMA start conditions are met in state SO9, the state transitions to state SO3 due to DMA execution permission. In state SO3, data for executing DMA transfer is set. For example, DMA data such as an external memory first address and data length are set. Next, in response to a DMA start request, the state transitions to state SO4 and DM of the burst size is executed.
Execute A. Burst size D in state SO4
When MA is completed, state 4 transitions to state SO6 and D
Perform MA execution completion determination.

If the DMA is not completed here and it is necessary to re-execute the burst size DMA, the DMA that has transitioned to state SO9
re-run. On the other hand, if the DMA is completed, the state S
Transition to O7 and DMA completion processing is performed. When this completion process is completed, the DMA completion process is completed and the state returns to Sol.

As described above, in the conventional case, requests for other channels are not accepted until DMA for one channel is completed.

On the other hand, in this embodiment, one channel's DMA
If there is a request for a high-priority DMA channel during execution, the request will be accepted upon completion of the burst size DMA. That is, the state transition of this embodiment is shown in FIG. 9 (B
) for a detailed explanation. In FIG. 9(B),
The same states as in FIG. 3(A) are given the same reference numerals as in FIG. 4(A).

In the first state S01, DMA channel requests are accepted or accepted based on the DMA channel priority list in Table 1. If there is a request, the process moves to state SO2 and detects the DMA start condition. For example, the condition is that the reception FIFO threshold signal of the reception DMA request is on. Then, at the end of the burst size DMA, if the reception FIFO threshold signal is off (L), the process returns to state S01 and checks for other channels. If the DMA start conditions are met in state SO2, the DMA
Upon execution permission, the state transits to SO3. In state SO3, data for executing DMA transfer is set. For example, DMA data such as an external memory first address and data length received from the small CPU block 105 in FIG. 1 into the 2-point RAM are set in respective dedicated counters. Further, in a case where an address counter or the like is shared between DMA channels, when execution is interrupted, data is saved in a 2-bot RAM until execution is resumed. In the case of a normal DMA execution channel, a DMA start request causes a transition to state SO4, and burst-sized DMA is executed. On the other hand, DM
In the case of the A priority channel, the priority channel DMA start request causes a transition to state SO5, and burst size DMA is executed. When the burst-sized DMA in states SO4 and SO5 is completed, the state transits to state SO6, and it is determined whether the DMA execution is complete. If the DMA is not yet completed and it is necessary to re-execute the burst-size DMA, the state transitions to SOI and the DMA is re-executed.

If DMA is completed, transition to state SO7 and DM
Perform A completion processing. When this completion process is completed, the process returns to state S01 in order to restart the DMA of the interrupted channel.

FIG. 7 is a DMA performance chart when the firmware of this embodiment is used to process overlapping DMA requests. Incidentally, the priority of the DMA channel is based on the priority table of the DMA channel in Table 1.

In FIG. 7(A), the burst size of the transmit FIFO is 64.
This is a performance graph of transmission in the case of bytes. The transmit DMA request is accepted first, and the receive DMA request is accepted at time 0 when the first burst size DMA is completed. Since no transmission is being performed while the reception DMA is being executed, the amount of data in the transmission FIFO does not change.

The third burst size DMA is completed and the transmit FIFO is
At time 0, when the threshold signal turns off, RA
M mode DMA requests are accepted with priority. However, since there is a condition that the maximum data length is 31 to 32 bytes, there will be no inconveniences such as the amount of data in the transmission FIFO becoming empty or communication data being interrupted due to this.

FIG. 4B shows a reception buffer when the burst size of the reception FIFO is 64 bytes.

First, a receive DMA request is accepted, and at time 0, when the first burst size DMA is completed and the receive FIFO threshold signal is turned off, RAM mode DM
Requests A are given priority. However, since the data length is limited to a maximum of 32 bytes, there is no need to worry about inconveniences such as communication data being erased due to the reception FIFO becoming full.

As described above, in a communication DMA controller with a priority determination function, even if the initially accepted DMA request continues, each time a preset burst size of DMA transfer is completed, , check other requests,
D with the highest priority based on pre-assigned priorities
Switch to MA channel and execute DMA. For example, even if there is a receive DMA request immediately after the start of the transmit DMA,
When the priority of the receive DMA is higher than the priority of the receive DMA, the receive DMA is given priority.

Therefore, it is possible to reduce time losses such as when reception fails and the other station is forced to retransmit.

Also, after the DMA of the high priority channel ends,
DMA of the interrupted channel is re-executed from the previous interruption point. Therefore, it is much more efficient than restarting interrupted DMA from the beginning.

Furthermore, since the burst size is a variable value that can be set by the host processor, by adjusting this value as appropriate, the time for acquiring bus rights with the host system can be adjusted to an optimal time.

〔Effect of the invention〕

As described above, according to the present invention, while executing DMA transfer in units of a predetermined burst size, a request for a DMA channel with a high priority is confirmed, and if a DMA request from a channel with a high priority is detected. Since the system is configured to switch to this mode when the communication occurs, it is possible to eliminate loss time such as waiting time and retransmission time, and improve communication efficiency.

[Brief explanation of the drawing]

Fig. 1 is a basic block diagram of an embodiment of the present invention, Fig. 2 is a basic block diagram of the DMA control block in Fig. 1, and Fig. 3 is a basic block diagram of the DMA control block in Fig. 2. /A block diagram showing a detailed example of the instruction decoder section, FIG. 4 is the DMA firmware R in FIG.
Operation timing chart of OM/instruction decoder section, 5th
The figure is a block diagram showing a detailed example of the DMA request reception register and DMA condition determination circuit in Figure 2, and Figure 6 is a block diagram showing a detailed example of the DMA request reception register and DMA condition judgment circuit in Figure 2. About the transmit/receive FIFO threshold signal from FIFO/RAM used when performing burst steal processing
FIG. 7 is an explanatory diagram based on the configuration of O, FIG. 7 is a DMA performance graph when overlapping DMA requests are processed using the firmware of this embodiment, and FIG. 8 is an explanatory diagram showing overlapping DMA requests based on Table 1. DMA execution timing chart when a generated DMA request is processed. FIG. 9 is a basic state transition diagram of the DMA control firmware that controls the sequence of the DMA execution timing chart shown in FIG. 101... bus interface block, 102...
...DMA control block, 103...F I
FO/RAM, 104... Network interface block, lO5... Small CPU block, 201... DMA priority determination unit, 202... DM
A data storage unit, 203...DMA transfer control unit, 20
4... DMA firmware ROM/instruction decoder section, 205... DMA request reception register, 206...
DMA condition determination circuit, 301... multiplexer, 3
02... Address register, 303... Firmware ROM, 304... Instruction latch register, 305
...Instruction decoder, 306...Address increment, 307...Register, 501...Transmission 35
- DMA request reception register, 502... Reception DMA request reception register, 503... RAM mode DMA request reception register, 504... Read/write signal latch register, 505... Transmission DMA suspension flag, 506
...Send DMA execution flag, 507...Receive DM
A execution flag, 508...Burst size DMA completion flag. -36~

Claims (1)

[Claims] 1. Communication DM that is located between memories and performs data transfer between the memories by DMA transfer.
A controller, which has a plurality of channels, and each channel is a FIF used for the data transfer.
In a communication DMA controller, which has a DMA controller that transfers data from one memory to another memory and from another memory to another memory by switching channels, a transfer means for transferring data of a predetermined burst size, and a DM for each transfer by the transfer means;
A priority determining means for determining the priority of valid A requests; and a channel switching means for switching the channel in accordance with the DMA request determined to have the highest priority by the priority determining means. A communication DMA controller having a priority determination function. 2. The communication DMA according to claim 1, further comprising DMA execution means for executing a DMA request for its own exclusive working memory during data accumulation time in the FIFO during the data transfer. controller.