JPS59173829A - Input/output control system - Google Patents

Abstract

PURPOSE:To improve overall processing efficiency by accepting processing at the end of a command having a command chain processing request with a higher priority level to process the processing. CONSTITUTION:The titled I/O control system includes an operation processor 1, a main storage device 2, an I/O processor 3, I/O ports 4-1-4-4, and I/O devices 5-1-5-5. A microprogram in the I/O processor 3 has plural processing levels with different priority to accept and process processing requests. The processing at the end of a command including a command chain processing request is accepted with higher priority level as compared to the processing at the end of a command excluding the command chain processing request.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a human output control method in an information processing system.

In an information processing system, an arithmetic processing unit (hereinafter referred to as EPU)
) outputs data to and from multiple input/output devices (hereinafter referred to as I10 devices, for example, card readers, magnetic tape units, displays, line printers, etc.), the human output of these data is as follows.

Generally, this is done through an input/output control processor (hereinafter referred to as an I10 processor) and a plurality of input/output connection devices (hereinafter referred to as I10 ports) corresponding to each of the I10 devices.

This I10 processor is controlled by a microprogram and controls a plurality of CPU/'0 ports by executing the microprogram.

When the EPU issues a software command, I
The processor 10 executes a channel program whose storage start address is the memory address specified by this input/output command in the main memory. This channel program is
The microprogram of the I10 processor reads this command from main memory, decodes it, and executes a particular routine in the microprogram accordingly.

Starts the base and processes this command.

When the specified work of the I10 device for one command is completed, the I10 device notifies the if/U processor of the work completion via the I10 port.

When the I10 processor receives this notification, it checks whether the next command exists in the channel program, and if it exists, it immediately reads it and processes it in the same manner as described above.

In this way, a channel program consists of a plurality of successive commands, and the process of executing these commands one after another is called command chain processing.

This command chain process when controlling a high-speed I10 device such as a magnetic tape or magnetic disk is such that the read/write head finishes reading a certain block on the storage medium, sends a work completion notification to the I10 processor, and then The next command must be ready for execution while the head is passing through the interblock gap before reaching the next block on the media.

If this time is exceeded, a command overrun occurs and retry processing is required, resulting in an extremely poor performance of the I10 device.

In this way, when performing command chain≧processing for a high-speed I10 device, the I10 processor
It is necessary to receive the above-mentioned notification of the end of work as soon as possible via the 0-boat and process the command chain.

On the other hand, since there is no command to be executed in the 5th order of processing at the end of the last command of a channel program, such time constraints do not apply to high-speed I10 devices.゛.

Generally, if the I10 processor's microprogram handles the channel program.

A plurality of levels with different priorities are provided, and notifications of work completion from each of the 170 devices described above are also made in the form of a processing request for a specific level.

In the conventional example, the priority level when a certain I10 port makes a processing request is fixedly determined according to the type of I10 device connected to that I/() port.

Therefore, for example, the processing request from the I10 port to which the high-speed 1.10 device is connected to the above-mentioned magnetic tape unit is fixedly high in order to avoid the above-mentioned command overrun condition. The priority level is set.

However, as mentioned above, even with high-speed I10 devices, it is necessary to set processing requests to a high priority level only when performing command chain processing; Processing at the end of a command does not need to be set to a high priority level.

Conversely, if you decide to perform processing at a high priority level up to the end of the last command, you will need to edit the status of the processing result and report this status to the software as a channel program end process. Relatively time-consuming processes such as I10 interrupt processing to software will also be performed at this unnecessarily high priority level. This means that the number of high-speed I10 devices that can operate simultaneously under the control of the I10 processor is reduced accordingly.

That is, in the prior art, each I10 boat
The priority level of processing requests made to the 0 processor is fixed according to the type of I10 device connected to that I10 boat, and processing requests from the same I/(J boat when there is command chain processing) and command The above-mentioned inefficiency is caused because processing requests for the end of the last command of a channel program without in-processing are not distinguished from processing requests.

The object of the invention is to obviate the above-mentioned drawbacks of the prior art.

The system of the present invention includes an input/output control processor having multiple processing levels, a plurality of input/output connection devices controlled by the processor, and a plurality of input/output devices connected to each of the input/output connection devices. Processing level register means that can set all specific values corresponding to the processing level, and processing requests from the input/output device connected to this input/output connection device to the specific processing level set in the register means. and request processing level selection means for supplying the request to the processor as a request.

When the input/output device issues a processing request via the connection device, the processing request is made to the processor as a processing request for a specific processing level set in the register means.

Next, the present invention will be described in detail with reference to the 5 drawings.

Referring to FIG. 1 in its entirety, an example of the present invention is shown in FIG.
, human output control processor 3 (hereinafter referred to as I10 processor 3)
), input/output connection device 4-1゜4-2. ...4-4. (
Hereafter I10 baud) 4-1°4-2. ...4-4) and input/output device 5-1. 5-2. ...5-4 (hereinafter referred to as I
10 devices 5-1.5-2°...5-4).

Each I10 port 4-1 to 4-4 has a dedicated I1
For example, I10 port 4-1 is I10 port for card reader (ckL boat), and I10 port 4-2 is I10 port for magnetic tape device (MT boat).
, I10 port 4-3 is an I10 port for a display device (DSP board), and I10 port 4-5 is an I10 port for a line printer (LP port). Each of these I10 ports has a corresponding I/( J device, card reader 5-1, magnetic tape group [5-2.

Display device 5-3. Line printers 5-4 are connected to each.

Now, when the EPUI writes, for example, data in a specific area of the MMU 2 to the magnetic tape device 5-2, the procedure is as follows.

The EPUI issues software input/output commands to the I10 processor v3. When the microprogram of the I10 processor 3 decodes this, it reads the first command of the channel program located at the memory address specified by this input/output command in the MMU 2, decodes it, and reads the command contained in that command. Transfer settings are made to the MT boat 4-2 (I10 port 4-2) for which all parameters have been specified, and data transfer writing is activated.

After this, the actual data transfer writing process will be performed between the MT boat 4-2 and the magnetic tape device 5-2 (I10 device 5-2).
Because the software is doing the same thing.

The microprogram of the I10 processor 3 is released from processing this command and can proceed to other processing.

Now, when the above-mentioned hardware finishes the data transfer write process instructed by the set parameters, the magnetic tape device 5-2 sends a new message to the I10 processor 30 microprogram via the MT port 4-2. This will be reported as a suspicious processing request.

I10 processor 30 microprogram.

A plurality of processing levels with different priorities are used to accept all such processing requests and process them all.

One of them is the normal processing level, in which processing requests to this level are processed until all processing requests at a higher level than the user and all other processing requests at the same level but earlier than the user are completed. Accepted at this time. The processing request for this level will be referred to as LSf (hereinafter).

The other is a processing level that has higher priority than the normal processing level, and processing requests for this level are accepted in the form of program interrupts for the normal processing level. All processing requests for this level will hereinafter be referred to as MSK. The MSK is accepted immediately when the program is operating at its normal processing level, but at other times it is accepted after waiting until the program returns to its normal level.

Now, as mentioned above, in order to prevent a command overrun from occurring, in the conventional example, processing requests from a high-speed I/(J device such as the drowsiness tape device 5-2) are
It is always reported to the I10 processor as MSI (.

This causes the inefficiency mentioned above.

In this embodiment, this problem is solved by using purchasing as described below.

Referring to FIG. 2, the I10 boat 4-2 in one actual case includes driver receivers 101, 109, handshake controllers 102, 110, . I10 control unit 103. Processing request level register 104. ANDGATE IQ5. lQ
Includes all 5.7A/multiplexer 107 and status register 108.

Now, in this embodiment, this I10 boat 4-2 (
The aforementioned work completion report from the I10 device (in the current example, the magnetic disk device 5-2) connected to the MT boat 4-2) is sent to one of the AND gates 105 and 106 via the line 1056e. supplied to human power.

The output of the LSB (least significant bit) of the processing request level register 104 and the output of the bit next to the LSB are connected to the other input terminals of the AND gates 105 and 106, respectively.

Further, the output of the AND gate 105 is supplied as the LSB to the I10 processor 3 via the line 1050, and the output of the AND gate 106 is supplied to the I10 processor 3 via the line 1060.
MSi (is supplied to the I10 processor 3 via ').

If the data stored in the last two digits of the register 104 are "o, l", the completion report from the 2-in 1056 is sent to the I10 processor 3 on the line 105 (l).
It is reported as LSB via.

Furthermore, if the data stored in the last two digits of register 104 is "1.O", the completion report from line 1056 is sent to I10 processor 3 via 1060'.
Si (will be reported.

In this embodiment, this function of the I10 boat 4-2 is used to solve the above-mentioned problem of the conventional example as follows.

Once the I10 processor 30 microprogram decodes the first command of the channel program as described above, it sends a control signal to the handshake controller 102 via the handshake control line 1021 and all parameters contained in this command line 1010. ．． I via driver receiver 101
/(Transfer settings to the necessary registers in the J control unit 103.

At the same time, the microprogram determines the bit value of the command chain flag field included in this command.

If this command has a following command.

If you are making a command chain processing request.

“1” is set in the C field. In this case, the microprogram transfers and stores "1.0" in the processing request level register 104 using the same procedure as described above, and then
I/(J commands the control unit 103 to start data transfer writing.

Also, if there is no command following this command, this command chain flag field will be set to “0”.
It has become. In this case, the microprogram stores "0.1" for all transfers in the processing request level register 104, and then instructs the I10 control unit 103 to start data transfer writing.

When the above steps are completed, the microprogram of 10 processor 3 is released from processing this command.

Proceed to another process.

On the other hand, the I10 control unit 103, which has been instructed to start the data transfer write, executes the data transfer write process instructed to the magnetic chip device 5-2 according to the set parameters. When the instructed processing is completed, a completion report is sent from the magnetic tape device 5-2 via the 2-in 1056t-.

As described above, this completion report can be supplied to the I10 processor 3 as an MS if the currently processed command requests command chain processing, and
If it is the last command not requesting command chain processing, it is supplied to the I10 processor 3 as an LSI.

Conclusion of C 1. If there is a command chain processing request, the I10 processor 30 microprogram accepts it as a processing request by the MS with a high priority, reads the next command from the MMU 2 at the high priority processing level, and processes this new command. Exactly the same processing as described above is performed on the data.

By processing at a high priority level, the processing time of the reception is shortened and the above-mentioned command overrun can be prevented.

Furthermore, if it is a completion report of the last command without a command chain processing request, it is accepted as a processing request by the LSR with low priority, and at the normal level, the status line 108 (
The contents of the status register *108 that stores the processing information supplied via l are transferred and stored in a specific memory address of MMU2, and when this is completed, a notification is sent that the execution of this input/output instruction has been completed. Therefore, an interrupt is issued to the software. These relatively long time consuming processes are processed at one normal level.

Don't waste high-priority program run time on money thieves.

As mentioned above, according to this practical example, even if there is a processing request from the same I10 boat, if there is a command chain processing request, the processing request MSB with a high priority is used to process the processing request within the shortest possible time. By processing the reception, we completely prevent command overruns from occurring, and by using low-priority processing request LSR-i for processing at the end of the last command for which there is no command chain processing request, priority This eliminates the disadvantages of the prior art described above by preventing unnecessary waste of high program run time.

I can do it.

Further, in this embodiment, there are two processing request levels, MSkL and LSR, but this number can be further increased as necessary.

MSkL, LSS by processing request level register 104 and 105 and 106 shown in FIG.
All the circuits that occur are merely shown as one circuit example, and the present invention is not limited thereto.

Further, it is also possible to provide as many I10 boards as necessary having the above-mentioned functions.

As described above, when the present invention is used, when executing an input/output command to a specific input/output device, the processing at the end of a command with a command chain processing request is changed from the processing at the end of a command without a command chain processing request. However, it is possible to accept and process the data at a higher priority level, thereby improving the overall processing efficiency.

[Brief explanation of the drawing]

FIG. 1 is a process diagram showing one embodiment of the present invention. 2 is a block diagram showing details of a specific I/(J boat) used in this embodiment. In the figure, 1... Arithmetic processing unit (EPtJ)
. 2... Main memory unit (MMU), 3...
Input/output control processor Cl10 processor), 4-1
~4-4... Input/output connection device (I/(J port), 5-1 to 5-4... Input/output device (I10 device), 101゜109... ...Driver receiver, 102, 110...Handshake controller'+103...I10 control section, 104...
...Processing request level registration, j05,106...
...AND gate, 107 ...Multiplexer, 108 ...Status register.

Claims (1)

[Claims] A human output control processor having a plurality of processing levels, a plurality of input/output connection devices controlled by the processor, and a plurality of input/output devices connected to each of the input/output connection devices. In the input/output control method, a processing level register means with a setting (a) and a processing request from the input/output device connected to this human output connection device are set to a specific processing level set in the register means. request processing level selection means for supplying a processing request to the processor as a processing request for the level; when the input/output device makes a processing request for the connection device, the selection means selects the register means; A human output control system characterized in that a processing request for a set specific processing level is issued to the processor.