JPH023217B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device, specifically, a data processing device in which a processor with a hold function and a DMA controller are connected via a bus, and which improves the processing efficiency of the processor. Regarding equipment.

In recent years, rapid advances in MOL LSI technology have made it possible to construct a complete and highly capable data processing device with just a few components.

Components of the microprocessor family can also be combined with these types of IC memories or general-purpose peripheral control devices to form data processing devices with a wide range of capabilities. The data processing device consists of the following three parts.

(1) Central processing unit (CPU) (2) Memory (3) Interface unit with peripheral devices (general purpose or dedicated peripheral controller device) The CPU is the heart of the system. Its function is to obtain instructions from memory and perform the desired action. Memory is used to store instructions and often data to be processed. The interface unit with peripherals is used to connect peripherals connected to the data processing device, such as keyboards,
It serves as a data transfer path for CRT displays, printers, magnetic disk devices, floppy disk devices, etc., and also has various control elements. These required components require virtually no external logic and can be connected together in a very simple manner.

Now, let us consider the case where a processor CPU and a DMA controller, which is a general-purpose peripheral device, are combined. In this case, the two are connected via the processor's internal bus (consisting of multiple lines for address and data control),
There are other memory devices on this bus, including the DMA
It is assumed that a peripheral device (for example, a magnetic disk device) is further connected to the controller.

After initial settings are made by a program (processor), the DMA controller has a function of performing block transfer of data between memory and peripheral devices without the intervention of a processor. That is, memory addresses are continuously generated in order to read or write data between the memory and the peripheral device in accordance with a request (DMA request) from the peripheral device. In this case, bus occupancy is the processor's hold function (setting the processor's bus (address/data) to a floating state); for this purpose, the processor is provided with a signal terminal called HOLD.
Therefore, external devices can occupy the bus during this time. ) is used.

As mentioned above, when controlling the processor and DMA controller on the same bus,
When operating the DMA controller, the processor's hold function is used to temporarily put the processor bus in a floating state, and after occupying the bus, a series of processing is performed. By the way, in this case, in order to give priority to the hold function, the processor is designed to perform a fetch every machine cycle. Therefore, even if there is no urgent processing request, the interval between hold requests is short (quick).
Therefore, the processing of the processor itself has to be stopped every machine cycle. This has been one of the causes of a significant decrease in processing efficiency of the processor.

The present invention has been made based on the above circumstances, and an object of the present invention is to provide a data processing device that improves the processing efficiency of a processor by synchronizing the machine cycle of a processor and a DMA request on an instruction-by-instruction basis. .

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 1 is a DMA controller, and 2 is a processor, whose functions are as described above. The hold request terminal HRQ of the DMA controller 1 is the hold terminal of the processor 2.
Both modules 1 and 2 are connected to the HLD, and both modules 1 and 2 are connected to the system bus (6; address/
data and control lines).

In the embodiment of the present invention, the DMA controller is 8257, which is sold by INTEL in the United States;
A programmable DMA controller is also sold by INTEL as a processor.
8085A: Uses a one-chip 8-bit N-channel microprocessor. For details on the specifications of these LSIs, please refer to the Microcomputer User's Manual MCS-85 published by the company on April 15, 1978.

3 is for the DMA controller 1.
A flip-flop 4 is provided to issue a DMA request; 4 is a flip-flop that generates a clock for issuing the DMA request; 5 is an AND gate that detects a machine cycle for an OP code fetch (first machine cycle) in the processor 2; . The AND gate 5 is supplied with three status signals IMO, S ₀₁ and S ₁₁ . This is a status signal issued by the processor 2 at the beginning of every machine cycle, and clearly indicates what type of machine cycle is about to be executed. The IMO signal tells whether this machine cycle is memory related or an input/output operation. The _S01 status signal ensures whether this cycle is a read or write operation. S ₀₁
and S ₁₁ status signals can be read /
It identifies one of three states: write or OP code fetch machine cycle and HALT state. Please refer to the manual mentioned above for details. The output of the AND gate 5 is connected to the D input terminal of the flip-flop 4. The clock terminal CK of the flip-flop 4 is supplied with an address latch enable signal ALE generated by the processor 2, and the preset terminal PR is supplied with an output pulled up from a +5 volt power supply. The Q output of the flip-flop 4 is supplied to the clock terminal CK of the flip-flop 3 at the subsequent stage. The D input terminal of the flip-flop 3 receives a DMA request signal (DMA REQ) from the outside (peripheral device).
is supplied to the DMA request terminal DRQ of the DMA controller 1 as a data request signal by the output of the flip-flop 3.

FIG. 2 is a diagram showing the relationship between DMA requests and machine cycles, and is shown for the purpose of comparing the operation of the present invention and the conventional operation. In the figure, a indicates a machine cycle of the processor 2 when there is no DMA request.
This is a machine cycle consisting of M ₁ , M ₂ , M ₃ , and M ₄ . b shows a machine cycle in the conventional processor 2 when there is a DMA request, and c shows a machine cycle obtained by the present invention when there is a DMA request.

Hereinafter, the operation of the present invention will be explained in detail using FIGS. 1 and 2. First, from the outside DMA
When the request signal arrives, a data request is attempted to be issued to the DRQ terminal of the DMA controller 1, but the clock of the flip-flop 3 is not generated unless a certain condition is met. Therefore DMA
A DMA operation is not executed simply by the arrival of a request signal. In order to obtain a clock for flip-flop 3, the signal entering the D input terminal (AND gate 5 output) of flip-flop 4 must be active and clock ALE must be generated.

Note that the clock ALE is an address latch enable signal generated by the processor 2 every machine cycle. Also, D of flip-flop 4
The AND gate 5 output supplied to the input terminal indicates the beginning of the machine cycle as described above,
This is the undoing (or decoding) output of processor 2 status.

When processor 2 enters machine cycle _M1 to execute a certain instruction, the AND condition of AND gate 5 is satisfied and the D input of flip-flop 4 becomes active. More machine cycles
The ALE signal generated in _M1 sets flip-flop 4, and the Q of flip-flop 4 is set.
Output becomes active. At this time, if the DMA request signal (DMA REQ) is active,
The output of flip-flop 3 becomes active, a data request is issued for the first time, and the DMA
A DMA request is transmitted to controller 1.
In other words, the data request signal output to the DMA controller 1 is synchronized with the machine cycle of the processor 2, and even if a burst data request occurs, the processor 2 can always process one instruction after processing the data request. Become. mentioned above
A diagram illustrating the relationship between the DMA request signal and the machine cycle of processor 2 is shown in FIG. 2c.

As explained above, the present invention synchronizes the machine cycle of the processor and the DMA request on an instruction-by-instruction basis.This allows the processor to process one instruction even though there is a DMA request.
Therefore, the processing efficiency of the processor can be improved. By doing so, it is possible to provide an effective countermeasure when it is necessary to improve the processing efficiency of the processor at the system processing speed even if there is a burst hold request.

[Brief explanation of drawings]

Figure 1 is a block diagram showing an embodiment of the present invention, Figure 2 is a block diagram showing an embodiment of the present invention.
The figure is a diagram showing the relationship between DMA requests and machine cycles. 1...DMA controller, 2...processor, 3, 4...flip-flop, 5...AND gate, 6...system bus.

Claims (1)

[Claims] 1. A processor with a hold function and a DMA controller are connected via a bus of the processor, and a gate that detects the first machine cycle based on a status signal output from the processor; a first flip-flop that stabilizes the obtained signal; and a second flip-flop that synchronizes a DMA request signal instructed from the outside with the machine cycle of the processor based on the output of the first flip-flop; 2 flip-flop outputs to the DMA controller.
A data processing device characterized in that it outputs a DMA request signal.