JPS60183667A - Information processing unit - Google Patents

Abstract

PURPOSE:To relieve the load of a CPU by holding the state of an execution section at program intermission while not saving it in case of transmission of pattern information so as to attain the high speed transfer of pattern information. CONSTITUTION:The execution section 102 transfers an instruction word stored in a program memory 103 to an instruction register 307, decodes it by an instruction decoder 308, an execution control section 309 controls each section and executes the program. In this case, when an I/O processing mode designation line 303 is at high level, an I/O request reception section 304 recognizes that the input/output request is an automatic data transfer request and informs it to the execution section 102. A control section 309 inhibits the update of a program counter 102-1, does not save the value of the counter 102-1 and a program status word 102-2 to a stack area of a data memory 104 and conducts processing while holding the value. Thus, the response time from the generation of input/output request to the data output is decreased, the pattern information is transferred in high speed and the load of the CPU is relieved.

Description

Detailed Description of the Invention [Technical field to which the invention pertains] The present invention relates to an information processing device, and in particular to a method for regularly inputting information in synchronous response to a signal input from outside the device or a signal generated inside the device. The present invention relates to an information processing device having an output function.

[Description of prior art]

Information processing systems using a data processing device such as a microcomputer as a control system include, for example, generation of dot character patterns synchronized with dot position signals in a dot printer, generation of motor drive patterns for each step time in step motor drive, and generation of a motor drive pattern for each step time in a step motor drive. Processing for regularly and sequentially outputting pattern information is required, such as outputting display segment information on a dynamic display side such as a light-emitting diode or the like. Generally, these processes are executed by interrupting (hereinafter referred to as interrupt processing) while the data processing device is executing a normal program (hereinafter referred to as main processing).

The block configuration of a conventional ti'i information processing device will be explained below with reference to FIG. 1 and an a-chart of an interrupt program for outputting pattern information shown in FIG. (The information processing device 7 is configured so that the pattern information output cycle 100 is supplied to the interrupt control unit 101. Program counter 102-1. Program status word 102-2. General-purpose register set 102. -3.The execution unit (CPU) 102 executes interrupt processing in response to a signal (interrupt request) transferred through an interrupt request line 101-1 provided between it and the interrupt control unit 101. In reality, there are interrupts from other peripheral devices, but they are omitted here.The synchronizing signal of the switching pattern output, that is, 1, is
0 may be input from outside the device or may be generated from peripheral hardware inside the device, such as a time signal from a timer, but the signal generation source is omitted and is shown in -C.
be.

In addition to this, the conventional information processing device has a program memory 103 that stores programs for main processing and interrupt processing.
．． Output pattern information (when created by the CPU,
(which may be supplied externally) and are interconnected by an internal bus 105. The data memory 104 stores in advance an output pattern storage area required for interrupt processing executed in response to a synchronization signal for pattern output, that is, pattern information to be transferred to the outside by interrupt processing. The address information specifying the output area and the information of the pattern 1a to be output are stored in the pattern output variable area 104-1. An output pattern storage area 104-2 is provided.

At the beginning of pattern information output and processing, pattern 1
0 included 1b1
It is detected by both parts 101. In response to the detection, the interrupt control unit 101 activates the interrupt request line 101-1 and notifies the execution unit 102 of a pattern output interrupt request. As a result, upon receiving the notification, the execution unit 102 starts pattern output interrupt processing.

In order to perform pattern information output processing (interrupt service) as shown in the flowchart of FIG. 2, the main processing being executed at that time must be temporarily interrupted. Therefore, it is necessary to preserve the internal state of the CPU at that time. Therefore, the program counter 102-1 indicating the internal state
．． Program status word 102-2. It is necessary to temporarily save the contents of the general-purpose register set 102-3 and the like to the stack (another memory area). After this process is completed, the interrupt service shown below is executed. Address information specifying the output pattern storage area 104-2 and output data number information specifying the number of patterns to be output are read from the unshuffled pattern output parameter area 104-1.

Next, the pattern information to be output is read from the pattern output parameter area 104-1 specified by the pointer, and the pattern output register 10 in the pattern output unit 106 is read out.
6-'2 and outputs it to output line 106-3 via baud) 106-1. The first woman who outputs pattern information, the address that specified the output data storage area 103-2 (W Ii is updated and the result is output as a pattern)
Kurame-4 area] Store in 04-1. Furthermore, the pattern output (by updating the output data number information read from the lamé-4 area 104-1, the pattern output vari-make area 10
4-1. The output data number information is investigated, and when it becomes a predetermined value, the address designation value of the output parameter area 104-1 and the output data number information are reset, and pattern information to be output next is generated. Perform pattern output completion processing such as. On the other hand, if the value is not the predetermined value, the information saved in the stack is transferred to the respective original program counters 102-1. Program status word 1.02-2. The interrupt processing is completed by returning to the general-purpose register set 102-3.

As described above, in the conventional information processing apparatus, when the transfer of the turn information and the output to the boat are executed by interrupt processing, this is accomplished by the notware processing as described above. Therefore, it is essential to save and restore the contents of the program card, program status word, and general-purpose register cents, and these processes involve the liver's pattern information transfer process, that is, from the memory to the board. The processing time required is much longer than that required for pattern transfer processing. Therefore, this reduces the main processing capacity of the CPU and is a major hindrance to realizing high-speed pattern information output.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an information processing device that transfers pattern information at high speed without the intervention of software interrupt processing and reduces the burden on the CPU.

[Structure of the invention]

The present invention provides an information processing apparatus including a transfer section that transfers pattern information, an execution section that transfers pattern information between the transfer section, and a memory section that stores processing data and a program. The present invention is characterized in that execution of the program is interrupted and a process of transmitting pattern information with the transfer unit is executed, and at this time, the transfer process is performed while the state of the execution unit at the time of interruption is maintained without being saved. That is.

That is, the transfer section has a first storage means, the supplement execution section has a second storage means, and the execution section transmits data between these first and second storage means, This data transmission is performed by interrupting the program processing being executed by the execution unit, and at that time, the execution unit can immediately perform the data transmission process without saving the state at the time of interruption to the stack. An information processing device that can perform the following operations is obtained.

Furthermore, the first storage means of the transfer section has at least two stages of register means connected in series therein, one of which is connected to the output port and the other is connected to the second storage means. . Data is stored in the first register means connected to the second storage means, and the data is transferred to the other second register means in response to a signal requesting the transmission process. . By doing this, when another request with a higher priority than the above-mentioned transmission processing request occurs, or when the transmission processing request cannot be immediately accepted, the requested transmission processing can be performed in the trench. During this period, the data preset in the first register means is controlled to be outputted to the cover via the second register means.

〔Effect of the invention〕

In the present invention, the conventional interrupt processing request is broadly interpreted,
Processing requests from peripheral devices or internal circuits (hereinafter referred to as I1)
0 request). The engineering β request is processed in two types of processing modes depending on the settings by the program. The first type of processing is conventional interrupt processing, in which billing is processed through software processing. The second processing state is data transfer processing from the data memory to the transfer unit, and this is performed without requiring the software processing described above.

Data transfer according to the second processing form (hereinafter referred to as automatic data transfer processing) is performed by peripheral devices and internal circuits.
When a request occurs, the normal program execution of the CPU is interrupted, and the various states of the CPU at that time (hereinafter referred to as status) and data are retained. Since this is realized by the CPU itself performing data transfer processing, special software for automatic data transfer processing is not required.

After the CPU finishes outputting the pattern to the boat through automatic data transfer processing, the CPU resumes execution of the interrupted program based on the retained status and data. Therefore, the interruption of the program is not visible to the software, and it appears as if automatic data transfer processing was automatically inserted during program processing.

Furthermore, by configuring the transfer unit with two stages of registers, when the transmission processing according to the second processing form cannot be executed immediately, it is possible to transfer data between the registers using that period. . This can be done by activating a shift operation between registers by a signal requesting the second processing form. As a result, the transmission process can be carried out without interruption, which is very effective, for example, when data for controlling a servo motor is processed in the second processing form.

[Explanation of Examples]

Figure 8g3 shows a detailed block diagram of an embodiment of the present invention, and this embodiment will be explained below.

The information processing apparatus includes an I10 request processing control section 301 which serves as an input section for output synchronization signal 100 of pattern information, and a program counter 102-1. Program status word 10
2-2. General-purpose register set 02-3, an execution unit including a kojitsu operation unit 306 (hereinafter referred to as ALU) 02, a program memory 103, a Bakun output parameter save area 104-1, and an output and a data memory 104 including a cover turn storage area 1 fl 4-2, and are interconnected by an internal bus 105. I10 inputs number 100 for pattern output synchronization f, .
In response to the signal 100, the request processing control unit 301 generates an I10 processing execution request signal 3()2 and an i10 processing processing mode designation signal 303. Furthermore, the I10 processing execution request signal 302 from the I10 request processing control unit 301 and the
10 Processing processing type f♂14 specification 1g No. 1g 303 is received to control the operation of the execution unit 102. An instruction decoder 308 that generates various control signals according to the contents of the instruction decoder 307; an execution control section 30 that controls the operation of the entire execution section according to the output of the instruction decoder 308;
9. A memory pointer (hereinafter referred to as MP) 3] that specifies the address of the data memory 104, a boat pointer (hereinafter referred to as PORTP) that specifies O-1 and the port, 310-2, and a terminal counter (hereinafter referred to as PORTP) that stores the number of automatic data transfers. automatic data transfer register 310.310-3 (hereinafter referred to as TC). A pattern output section 106 including an output register 10G-2 and a boat 106-1 for outputting pattern data. and pattern output line 106
-3. It is preferable that the pattern output section 106 has at least two stages of registers connected in series, as will be described later.

Any value can be set in the automatic data transfer register 310 by a program. In this embodiment, pattern output data storage area 104-1 (D7 host information is output to MP310-1 of automatic data transfer register 310 in advance, and PORTP310-2VC is output to MP310-1 of automatic data transfer register 310.
The designation information of 06-2 and the number of pattern outputs are stored in the TC 310-3.

Next, the operation will be explained with reference to the block diagram in FIG. The execution section is a program memo specified by the contents of the program counter 102-1. The instruction word stored at the address J103 is transferred to the instruction register 307, the instruction word transferred to the instruction register 307 is decoded by the instruction decoder 308, and the execution control section 309 controls each section to execute the program. Implementation has been realized. I10 request reception is part 3
04 is the I10 process execution request code 30 every time the instruction execution is completed.
2, and repeat the above operation when the level is 10''.

The I/Q request requesting unit 304 receives the I/Q processing execution request signal 30
2 is at a "high level" and at the same time J10
The level of the processing type bad designation signal 303 is sampled. If the level of the I10 immediate execution mode designation signal 303 is low level, the I10 request reception unit 304 recognizes the I10 request as conventional interrupt processing, that is, the first processing mode, and sends it to the execution unit. Inform.

Execution control unit 309 prohibits updating of program counter 102-1, and then saves program counter 102-1 and program status word 102-2 to the stack area of data memory 104. Execution control unit 309
starts execution of the interrupt processing program by setting the branch address caused by the interrupt in the program counter 102-1. When a series of program processing interrupt processing programs are completed, the data saved in the data memory 1o4 is reset to the program counter 102-1 and the program status word 102-2, thereby returning to the interrupted program processing. .

On the other hand, if the I/Q request reception unit 304 recognizes that the I10 request is an automatic data transfer request, that is, the second processing mode, if the I/Q request reception unit 303 is at a “high level”. and inform the execution department of this. Execution system M11 part 3
09 prohibits updating of the program counter 102-1,
Program counter 102-1. Without moving values such as program status word 102-2 to the stack area of data memory 104, the! , and then execute the process shown below.

■ The execution control unit 309 controls the MP of the automatic transfer register 310.
The output pattern data is read from the output data storage area 104-1 pointed to by PORTP 310-1 and transferred to the output register 106-2 specified by PORTP 310-2.
6-1 to output line 106-3.

- Add 1 to the value of MP310-1 using ALU3 Q5 and store it in MP310-1 again.

(2) Subtract 1 from the value of TC310-3 using AI and U306 and store it in TC310-3 again.

The above series of processes completes the automatic data transfer process for pattern output to the boat. That is, when automatic data transfer processing is started, the pattern output data of the data memory 104 specified by MP 310-1 is transferred to PORT.
The process of transferring the data to the output register 106-2 specified by P310-2 is performed.

When the value of TC310-3 is subtracted and becomes 0, the billing control unit 301 activates the I10 processing execution request signal 302 again, and at the same time activates the I10 processing mode designation signal 302.
3 is set to low level, an interrupt request is generated according to the first processing form, and pattern output completion processing is performed.

FIG. 4 shows a second embodiment in which the output register 106-2 of the embodiment shown in FIG. 3 is used as a first output register, and second output registers 106-4 are provided before and after this, and the register is configured in two stages. FIG.

The information output device operates in the same manner as the embodiment shown in FIG.

Generally, there are a plurality of I10 requests, and they are processed according to priority, and the reception of the one with the lowest priority 11j is put on hold. If a lower priority request occurs while processing a certain I10 request, the lower priority processing is suspended,
If the suspended request is a pattern information output request, there may be a delay from the request generation to the pattern output.

In the device shown in FIG. 4, pattern 17 is used as line output synchronization signal 100.
In synchronization with the activation level, the data held in the first output register 106-4 is transferred to the second output register 106-2 and outputted via the boat 106-1'c. . Therefore, if the pattern information to be output is set in the second output register 106-4, the pattern information can be output even if the request from the operator 10 is in a pending state.

In the embodiment of FIG. 4, when the request processing is completed and pattern information output processing becomes possible, the pattern information to be output next is transferred to the second register by automatic data transfer, as in the embodiment of FIG. 106-4.

As described above, in a device with priority control, by configuring the output boat in two stages, it is possible to perform output turn transfer processing with a lower priority even while processing with a higher priority is being executed, and from the occurrence of a pattern output request. Time delay in data output 1 can be suppressed.

According to the present invention, since pattern information is output through automatic data transfer processing, there is no need to worry about saving the program counter, program status word, etc., or performing branch processing using conventional interrupts. Data output to the boat becomes ijj function. Therefore, it is actually possible to perform pattern information output processing with a short response time from bill generation to data output.

Furthermore, even if I10 request reception is on hold, the second
If pattern information is set in the output register of I1,
Synchronizing with the occurrence of a 0 request, the value of the second output register is changed to the first
Since the data can be transferred to the output register of the board and output to the board, more efficient pattern transfer is possible. In this embodiment, an example is shown in which the priority order is uniquely set and the pattern output process is performed, but the same applies even if there are an initial number of requests and the priorities are different.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a conventional information processing device.
Figure 2 shows pattern output processing using conventional interrupts.
3 is a block diagram of an information processing apparatus according to a first embodiment of the present invention, and FIG. 4 is a block diagram of a second embodiment of the present invention. 100...Output synchronization signal of pattern information, 10
1...Interrupt control unit, 101-1...Interrupt line, 102...Execution unit, 102-1...
...Program counter, 102-2...
・Program status word, 102-3...
・General-purpose register set, 1o3...Program memory, 104...Data memory, 104-1
...Pattern output parameter save area, 104
-2... Output pattern storage area, 1o5...
... Internal lotus, 106 ... Pattern output L
10 a-1...Boat, 106-2, 106
-4...Pattern output register, 106-3.
... Output line, 301 ... I10 marriage processing control unit, 302 ... Engineering β processing execution request signal, 3o3 ... I10 processing processing mode designation signal ,3
04...I10 request reception is at Department 306...
...ALU, 307...Instruction register, 308
...Instruction decoder, 3o9...Execution control unit, 310...Automatic data transfer register, 3
10-1...Memory boi/ri, 310-2...
...Boat pointer, 3]0-3...Terminal counter. No 1 map Z area

Claims (1)

[Claims] (1) An output unit that outputs pattern information, a processing request control unit that detects a transfer processing request to the output unit, and an execution unit that performs processing and program processing based on the transfer processing request. , a memory section for storing processing data and programs, and the execution section is capable of interrupting program processing and transferring data to the output section in response to the processing request while maintaining the state of the execution section at that time. An information processing device characterized by: 2. The output unit that outputs pattern information includes a first and a second register, and is configured to transfer pattern information from the first register to the second register in response to generation of the transfer processing request. An information processing device according to claim 1, characterized in that: