JPH0157379B2 - - Google Patents

Description

Detailed Description of the Invention [Technical field to which the invention pertains] The present invention relates to an information processing device, and in particular to a method for regularly inputting information in synchronous response to a signal input from outside the device or a signal generated inside the device. The present invention relates to an information processing device having an output function.

[Description of prior art]

In an information processing system using a data processing device such as a microcomputer as a control system, for example, a dot character pattern is generated in synchronization with a dot position signal in a dot printer, a motor drive pattern is generated for each step time in a step motor drive, a fluorescent display tube, etc. Processing for regularly and sequentially outputting pattern information is required, such as outputting display segment information in dynamic display control of light emitting diodes and the like. Generally, these processes are executed by interrupting (hereinafter referred to as interrupt processing) while the data processing device is executing a normal program (hereinafter referred to as main processing).

The block configuration of a conventional information processing apparatus will be explained below with reference to FIG. 1 and a flowchart of an interrupt program for outputting pattern information, respectively. The information processing device outputs a synchronization signal 10 of pattern information.
0 is supplied to the interrupt control unit 101. Execution unit (CPU) 1 including program counter 102-1, program status word 102-2, and general-purpose register set 102-3
02 executes and controls interrupt processing in response to a signal (interrupt request) transferred through an interrupt request line 101-1 provided between the interrupt control unit 101 and the interrupt request line 101-1. In reality, there are also interrupt requests from other peripheral hardware, but they will be omitted here. In addition, the pattern output synchronization signal, ie, the signal 100, may be input from outside the device, or may be generated from peripheral hardware inside the device, such as a time signal from a timer, but the source of the signal is omitted. It is shown.

Conventional information processing devices also hold a program memory 103 that stores programs for main processing and interrupt processing, and pattern information to be output (sometimes created by the CPU, sometimes supplied from outside). The data memory 104 includes a data memory 104 which is interconnected by an internal bus 105. The data memory 104 stores in advance an output pattern storage area required for interrupt processing executed in response to a synchronization signal for pattern output, that is, pattern information to be transferred to the outside by interrupt processing. A pattern output parameter save area 104-1 and an output pattern storage area 104 in which address information specifying the memory area to be stored and the number of pattern information to be output are stored.
-2 is provided.

At the start of pattern information output and processing, the interrupt control unit 101 detects input of the pattern information output synchronization signal 100. In response to the detection, the interrupt control unit 101 activates the interrupt request line 101-1 and issues a pattern output interrupt request to the execution unit 102.
to notify. As a result, upon receiving the notification, the execution unit 102 starts pattern output interrupt processing.

In order to perform pattern information output processing (interrupt service) as shown in the flowchart in Figure 2,
The main processing being executed at that time must be temporarily interrupted. Therefore, it is necessary to preserve the internal state of the CPU at that time. Therefore, it is necessary to temporarily save the contents of the program counter 102-1, program status word 102-2, general-purpose register set 102-3, etc. that indicate the internal state to the stack (separate memory area). be. After this process is completed, the interrupt service shown below is executed. First, from the pattern output parameter area 104-1 to the output pattern storage area 104-
Address information specifying 2 and output data number information specifying the number of patterns to be output are read.
Next, read the pattern information to be output from the pattern output parameter area 104-1 specified by the pointer, set it in the pattern output register 06-2 in the pattern output section 106, and send it to the output line via the port 106-1. Output to 106-3. After outputting the pattern information, the address information specifying the output data storage area 104-2 is updated and the result is transferred to the pattern output parameter area 10.
Store in 4-1. Furthermore, the output data number information read from the pattern output parameter area 104-1 is updated and the pattern output parameter area 104-1 is updated.
-1 is newly stored. The output data number information is investigated, and when it reaches a predetermined value, the address designation value of the pattern output parameter area 104-1 and the output data number information are reset, and the next pattern information to be output is generated. Perform pattern output completion processing. On the other hand, if the value is not the predetermined value, the information saved in the stack is returned to the original program counter 102-1 and program status word 102, respectively.
-2, returns to general register set 102-3 and completes interrupt processing.

As described above, in the conventional information processing apparatus, when the transfer of pattern information and the output to a port are executed by interrupt processing, this is accomplished by software processing as described above. Therefore, it is absolutely necessary to save the contents of the program counter, program status word, and general-purpose register set, and to restore them.Moreover, these processes are essential pattern information transfer processing, that is, pattern transfer processing from memory to port. It takes a very long processing time compared to the time required for Therefore, this is
This reduces the main processing power of the CPU and is a major hindrance to realizing high-speed pattern information output.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an information processing device that transfers pattern information at high speed without the intervention of software interrupt processing and reduces the burden on the CPU.

[Structure of the invention]

The present invention provides an information processing apparatus including a transfer section that transfers pattern information, an execution section that transfers pattern information between the transfer section, and a memory section that stores processing data and a program. interrupting the execution of the program and performing a process of transmitting pattern information with the transfer unit;
At this time, the transmission processing is performed while the state of the execution unit at the time of interruption is held without being saved.

That is, the transfer section has a first storage means, the execution section has a second storage means, and the execution section performs data transmission between the first and second storage means, This data transmission is performed by interrupting the program processing being executed by the execution unit, and information that allows the execution unit to immediately perform the data transmission process without saving the state at the time of interruption to the stack. A processing device is obtained.

Furthermore, the first storage means of the transfer section has at least two stages of register means connected in series therein, one of which is connected to the output port and the other of which is connected to the second storage means. . Data is stored in the first register means connected to the second storage means, and the data is transferred to the other second register means in response to a signal requesting the transmission process. . By doing this, when another request with a higher priority than the above-mentioned transmission processing request occurs, or when the transmission processing request cannot be immediately accepted, the processing will be delayed until the requested transmission processing is performed. During this period, the data preset in the first register means is controlled to be outputted to the output port via the second register means.

〔Effect of the invention〕

In the present invention, a conventional interrupt processing request is broadly interpreted as a processing request from a peripheral device or an internal circuit (hereinafter referred to as an I/O request). Said I/
The O request is processed in two types of processing formats depending on the settings by the program. The first type of processing is conventional interrupt processing, in which I/O
Process the request. The second processing state is a data transfer process from the data memory to the transfer section, which is performed without requiring the aforementioned software processing. Data transfer according to the second processing form (hereinafter referred to as automatic data transfer processing) is performed when an I/O request is generated by a peripheral device or an internal circuit.
Interrupts the CPU's normal program execution and displays various states of the CPU at that time (hereinafter referred to as status)
Furthermore, since this is achieved by the CPU itself performing data transfer processing while retaining data, special hardware for automatic data transfer processing is not required.

When the CPU finishes outputting the pattern to the port through automatic data transfer processing, it resumes execution of the interrupted program based on the retained status and data. Therefore, the interruption of the program is not visible to the software, and it appears as if automatic data transfer processing was automatically inserted during program processing.

Further, by configuring the transfer section with two stages of registers, when the transmission processing according to the second processing form cannot be executed immediately, the data transfer between the registers can be performed using the period. Can be done. This can be done by activating a shift operation between registers by a signal requesting the second processing form. As a result, the transmission process can be executed without waste, which is very effective, for example, when data for controlling a servo motor is processed in the second processing form.

[Explanation of Examples]

FIG. 3 shows a detailed block diagram of an embodiment of the present invention, and this embodiment will be described below.

The information processing device outputs pattern information synchronization signal 1
I/O request processing control 301 which is the input part of 00
and an execution unit 1 including a program counter 102-1, a program status word 102-2, a general-purpose register set 102-3, and an arithmetic operation unit 306 (hereinafter referred to as ALU) having an arithmetic operation function.
02, a program memory 103, a data memory 10 including a pattern output parameter save area 104-1 and an output pattern storage area 104-2.
4 and are interconnected by an internal bus 105. I/ that inputs the pattern output synchronization signal 100
In response to the signal 100, the O request processing control unit 301 generates an I/O processing execution request signal 302 and an I/O processing execution mode designation signal 303. Furthermore, an I/O request reception unit 304 receives an I/O process execution request signal 302 and an I/O process execution mode designation signal 303 from the I/O request process control unit 301, and controls the operation of the execution unit 102; Instruction register 307 and instruction register 30 that hold instructions to be executed
an instruction decoder 308 that generates various control signals according to the contents of 7, an execution control section 309 that controls the operation of the entire execution section based on the output of the instruction decoder 308, and a memory pointer (hereinafter referred to as MP) 301 that specifies the address of the data memory 104. -1, a port pointer (hereinafter referred to as PORTP) 310-2 that specifies a port, and a terminal counter (hereinafter referred to as TC) 31 that holds the number of automatic data transfers.
an automatic data transfer register 310 comprising: 0-3;
Output register 106 for outputting pattern data
2 and port 106-1.
6, and a pattern output line 106-3.
It is preferable that the pattern output section 106 has at least two stages of registers connected in series, as will be described later.

Any value can be set in the automatic data transfer register 310 by a program. In this embodiment, the automatic data transfer register 310 is set in advance.
MP310-1 has address information of pattern output data storage area 104-1, PORTP310-
2 contains the specification information of the output register 106-2,
The number of pattern outputs is stored in each TC310-3.

Next, the operation will be explained with reference to the block diagram of FIG. The execution unit is usually a program counter 102.
The instruction word stored at the address in the program memory 103 specified by the contents of -1 is transferred to the instruction register 307, the instruction word transferred to the instruction register 307 is decoded by the instruction decoder 308, and the execution control unit 309 decodes each unit. It controls the system and executes the program. The I/O request receiving unit 304 sends an I/O processing execution request signal 30 every time instruction execution is completed.
2 is sampled, and when it is at "low level", the above operation is repeated.

The I/O request receiving unit 304 samples the level of the I/O processing execution mode designation signal 303 at the same time as detecting that the I/O processing execution request signal 302 is at "high level". If the level of the I/O processing execution mode designation signal 303 is “low level”, the I/O request receiving unit 304 recognizes the I/O request as conventional interrupt processing, that is, the first processing mode, and executes it. Inform the department.

The execution control unit 309 is the program counter 102
-1, then program counter 102-1 and program status word 10.
2-2 is saved to the stack area of the data memory 104. The execution control unit 309 starts execution of the interrupt processing program by setting the branch address caused by the interrupt in the program counter 102-1. When the interrupt processing program is finished through a series of program processing, the data memory 104
The data saved to the program counter 10
2-1 and program status word 102-
By resetting to 2, the interrupted program processing is resumed.

On the other hand, if the I/O processing execution mode specification line 303 is at "high level", the I/O request receiving unit 304
recognizes that the I/O request is an automatic data transfer request, that is, the second processing form, and notifies this to the execution unit. The execution control unit 309 prohibits updating of the program counter 102-1, and updates the program counter 102-1 and the program status word 10.
The following processing is executed while the value such as 2-2 is held as it is without being moved to the stack area of the data memory 104.

The execution control unit 309 is an automatic transfer register 310
Output data storage area 1 pointed to by MP310-1
Read output pattern data from 04-1
It is transferred to the output register 106-2 specified by PORTP 310-2 and sent to the output line 106-3 via port 106-1.

Add 1 to the value of MP310-1 using ALU 306 and store it in MP310-1 again.

The value of TC310-3 is subtracted by 1 using ALU306 and stored in TC310-3 again.

The above series of processes completes the automatic data transfer process for pattern output to the port. In other words, when the automatic data transfer process is started, MP3
Processing is performed to transfer the pattern output data of the data memory 104 specified by PORTP 310-1 to the output register 106-2 specified by PORTP 310-2.

When the value of TC310-3 is subtracted and becomes 0, the I/O request control unit 301 activates the I/O processing execution request signal 302 again and at the same time sets the I/O processing mode designation signal 303 to low level. , generates an interrupt request according to the first processing form, and performs pattern output completion processing.

FIG. 4 shows the output register 106 of the embodiment of FIG.
-2 is the second output register, and the first
An output register 106-4 is provided, and the register 2 is
FIG. 3 is a block diagram of a second embodiment having a stage configuration.

The information output device operates in the same manner as the embodiment shown in FIG.

Generally, there are a plurality of I/O requests, and they are processed according to priority, and those with lower priority are subject to acceptance control. If an I/O request with a low priority occurs while processing an I/O request, the process with a low priority is suspended, and if the suspended I/O request is a pattern information output request, the request is There may be a delay before the pattern is output.

In the device shown in Fig. 4, pattern information output synchronization signal 1
00 becomes active level, the data held in the first output register 106-4 is transferred to the second output register 106-2 and outputted via the port 106-1. . Therefore, by setting the pattern information to be output in the first output register 106-4, the pattern information can be output even if the I/O request is in a pending state.

In the embodiment shown in FIG. 4, when the high-priority I/O request processing is completed and pattern information output processing becomes possible, the pattern information to be output next is automatically transferred to the first output as in the embodiment shown in FIG. register 10 of
Store in 6-4.

As mentioned above, in devices with priority control,
By configuring the output ports in two stages, it is possible to perform output pattern transfer processing with a lower priority even while processing with a higher priority is being executed, and it is possible to suppress the time delay from generation of a pattern output request to data output.

According to the present invention, since pattern information is output through automatic data transfer processing, there is no need to perform conventional interrupt-based saving of the program counter, program status word, etc., branch processing, etc.
It becomes possible to output data to the port in synchronization with the reception of the O request. Therefore, pattern information output processing with a short response time from generation of an I/O request to data output can be realized.

Furthermore, even if I/O request reception is pending, if pattern information is set in the second output register first, the value of the second output register can be changed to the first output register in synchronization with the generation of an I/O request. Since it can be transferred to the output register and output to the port, more efficient pattern transfer is possible. Although this embodiment has shown an example in which a priority is uniquely set and pattern output processing is performed, the same applies even if there are a plurality of I/O requests with different priorities.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a conventional information processing device, FIG. 2 is a flowchart of pattern output processing using a conventional interrupt, and FIG. 3 is a block diagram showing the configuration of a conventional information processing device.
FIG. 4 is a block diagram of the information processing apparatus according to the second embodiment of the present invention. 100...Output synchronization signal of pattern information, 10
1...Interrupt control unit, 101-1...Interrupt request line, 102...Execution unit, 102-1...Program counter, 102-2...Program status word, 102-3...General-purpose register set,
103...Program memory, 104...Data memory, 104-1...Pattern output parameter save area, 104-2...Output pattern storage area, 105...Internal bus, 106...Pattern output unit, 106-1... ...Port, 106-2,10
6-4...Pattern output register, 106-3...
...Output line, 301...I/O request processing control unit, 302...I/O processing execution request signal, 303
...I/O processing execution mode designation signal, 304...
I/O request reception unit, 306...ALU, 307
...Instruction register, 308 ...Instruction decoder, 3
09...Execution control unit, 310...Automatic data transfer register, 310-1...Memory pointer, 31
0-2...Port pointer, 310-3...Terminal counter.

Claims (1)

[Scope of Claims] 1. An output unit that outputs pattern information, a processing request control unit that detects a transfer processing request, a program memory that stores a program, and an address in the program memory where an instruction to be executed is stored. an execution control section that decodes the instruction read from the program memory and generates control information necessary for executing the instruction; an execution section that executes the instruction in response to the control information; The execution control unit includes a program status register that stores the execution state of the execution unit and a data memory that stores pattern information to be transferred.
In response to the transfer processing request, updating of the contents of the program counter and the program status register is prohibited, and the contents of the program counter and the program status register are maintained as they are without being saved in the data memory, and An information processing device characterized in that the pattern information to be transferred is read from the data memory and transferred to the output unit without using instructions stored in the program memory. 2. An output section that has first and second registers and outputs the pattern information stored in the second register; a processing request control section that detects a transfer processing request; and an output section that outputs pattern information stored in the second register; an execution unit that executes program processing; and a memory unit that stores pattern information and a program to be transferred;
The execution section transfers the pattern information from the register to the second register, and when the transfer processing request is accepted, the execution section interrupts program processing and transfers the pattern information to be transferred while maintaining the state of the execution section at that time. An information processing apparatus characterized in that the information processing apparatus transfers the information to the first register. 3. An output unit that outputs pattern information, a processing request control unit that detects a transfer processing request, a memory unit that stores pattern information and a program to be transferred, and an execution unit that reads and executes a program from the memory unit. The execution unit has means for suspending program processing in response to the transfer processing request and transferring the pattern information to be transferred to the output unit while maintaining the state of the execution unit at that time, and When the processing based on the transfer processing request is executed a predetermined number of times, the processing request control section generates an interrupt processing request, and the execution section saves the state of the execution section at that time in the memory section in response to the interrupt processing request. An information processing apparatus characterized in that the information processing apparatus executes program processing based on the interrupt processing request.