JP2001005505A - Programmable controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain superior extensibility by equipping a 1st CPU with a cyclic executing means which cyclically performs a user program executing process and an I/O refreshing execution control process and an interruption execution control means which informs a 2nd CPU of the completion of refreshing after interruption. SOLUTION: The 1st (main) CPU 2 performs a common process, a user program executing process, an I/O refreshing process, and a peripheral service process as cycle processes, and refers to and updates an I/O memory 27 in the respective processes. The main CPU 2 refers to and updates corresponding areas (A, B, and C) of the I/O memory with successive reports of interruption levels 0 and 1 to 3 from a 2nd (sub)CPU 3. The sub-CPU 3 requests I/O refreshing and interruption task execution which are performed in arbitrary timing of the sub-CPU 3 in addition to peripheral service processes as cycle processes similar to the main CPU 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a programmable controller (generally referred to as a PLC or the like), and more particularly to a so-called multi-CPU type programmable controller.
Regarding the controller.

[0002]

2. Description of the Related Art PLCs in which a CPU can be extended as an option by adding a sub CPU to a main CPU have been conventionally known. This kind of PLC
, The roles of the main CPU and the sub CPU are generally divided into a scheduling mode in which the sub CPU operates as a coprocessor in response to an execution request from the main CPU, or both CPUs operate in parallel with each other on an equal basis. is there.

[0003]

However, the following problems have been pointed out in the conventional PLC having an expandable CPU.

(1) Sub CPU mounted as an option
It is difficult to reflect the above characteristic in the control operation of the entire PLC. In addition, in order to realize such a function, it is necessary to previously mount a scheduling function for realizing the control operation on the main CPU side, which naturally increases the price.

(2) In a PLC in which both CPUs operate in parallel, the operation is independent for each CPU, and data cannot be transferred at an arbitrary timing (synchronization processing is required). For this reason, the control performance of the CPU is usually reduced.

[0006] The present invention has been made in view of such conventional problems.
It is excellent in expandability, and after expansion, each CP
An object of the present invention is to provide a multi-CPU type PLC which can make the most of the functions of U and can be manufactured at a relatively low price.

[0007]

According to the first aspect of the present invention, a first CPU, a second CPU, and an I / O memory built in the first CPU are stored in a second CPU. CPU
An optional bus to enable access from
An interrupt line for interrupting the first CPU from the second CPU, wherein the first CPU cyclically executes a user program execution process and an I / O refresh execution process; Click execution control means and, when an interrupt request arrives from the second CPU, performs an I / O refresh execution process relating to a specific I / O area in the I / O memory by interruption, and thereafter, completes the refresh operation by the second CPU. Interrupt execution control means for notifying the CPU, and the second CPU
In response to this, a cyclic interrupt request is sent to the first CPU, and in response to the request, the completion of the refresh is notified from the first CPU. The programmable controller is provided with control means.

Here, "CPU" means a central processing unit of a programmable controller having at least a user program execution function. The specification of the “I / O area” to be refreshed by the interrupt may be fixed in advance in association with the interrupt, or the second CPU
May be separately specified by an interrupt request sent from the server. The term "programmable controller" includes a building block type including a CPU unit, an I / O unit, and a power supply unit, and an integrated type in which all circuit elements are housed in one housing. Including both. Furthermore, the term "programmable controller" as used in this claim particularly refers to the CPU unit itself in a building block type programmable controller (ie,
CPU unit that does not include a power supply unit or an I / O unit).

According to such a configuration, in the first CPU, the user program is cyclically executed with I / O refresh, and at the same time, the second CP is executed.
In U, the user program is also I / O by interrupt
Performed cyclically with refresh. Therefore, while each CPU independently executes the user program asynchronously, the update of the input / output data itself is reliably performed in the execution cycle of each user program, and as a result, the performance of each CPU is maximized. It is possible to realize high-precision control while maximizing the effect.

[0010] The invention described in claim 2 of the present application is the first invention.
The interrupt execution control means provided in the CPU has a function of accepting multiple interrupts of different levels, and each time an interrupt request of each level arrives, a specific I / O memory in the I / O memory according to the interrupt level. The I / O refresh execution processing relating to the / O area is performed by interruption, and thereafter, the completion of refresh is notified to the second CPU, and the cyclic execution control means provided in the second CPU has its own unique Having a function of transmitting multiple interrupt requests of different levels in a cycle, and performing a user program execution process corresponding to each level after waiting for notification of refresh completion in response to the interrupt request of each level; The programmable controller according to claim 1, wherein:

According to such a configuration, in the first CPU, the user program is cyclically executed with I / O refresh, and at the same time, in the second CPU, a plurality of user programs are respectively executed by the I / O by the interrupt. Performed cyclically with O-refresh and in a unique cycle. Therefore, while each CPU independently executes the user program asynchronously, the update of the input / output data itself is surely performed in the unit of the execution cycle of each user program.
High-precision control can be realized while maximizing the performance of U. In addition, since a plurality of user programs executed by the second CPU are input / output updated at optimum cycles, high-precision control is possible from this aspect as well.

[0012] The invention described in claim 3 of this application is the first invention.
3. The programmable controller according to claim 1, wherein the interrupt control means provided in the CPU includes a specific user program execution process in addition to the I / O refresh execution process.

According to such a configuration, the user program is cyclically executed with the I / O refresh in the first CPU, and at the same time, in the second CPU, a plurality of user programs are respectively executed by the I / O by the interrupt. O refresh (executed on the first CPU side) and execution of a predetermined user program (executed on the first CPU side)
And is cyclically executed in a unique cycle. Therefore, the execution of the user program on the second CPU side is linked with the execution of the user program on the first CPU side, so that a more versatile control can be performed.

[0014] The invention described in claim 4 of the present application is the second invention.
CPU is detachable from a connector including a bus line leading to an I / O memory in the first CPU and an interrupt line in the first CPU, and a user program executed by the first CPU is mainly 4. The programmable controller according to claim 1, wherein the ladder task and the user program executed by the second CPU are mainly data operation tasks.

Here, the "data operation task" includes, for example, a PID operation and a floating point operation.

According to such a configuration, the second CPU functions as an option for adding to the first CPU, and the first CPU specializes in I / O control and uses resources (such as user memory). Low cost and simple PLC because it can reduce the functions and functions (high-performance instruction support)
On the other hand, by adding a second CPU as needed to execute the data calculation task, it is possible to easily cope with higher functionality. In addition, the first CPU, which is the main CPU, is notified by an interrupt notification from a scheduling function built in the second CPU optionally mounted.
U can execute the processing of U
This can be reflected in the control operation of C as a whole.

According to a fifth aspect of the present invention, the first external connection terminal connected to the peripheral I / O bus and the I / O data in which an interrupt request flag and a refresh completion flag are stored in addition to at least I / O data. / O memory and a second memory for enabling external access to the I / O memory
And an external connection terminal, and a user program memory for storing the user program. The user program execution process and the I / O refresh execution process are cyclically performed for a specific user program stored in the user program memory. A cyclic execution control means for performing the operation, and an I / O when the interrupt request flag is set.
At least an interrupt execution control means for performing an I / O refresh execution process relating to a specific I / O area in the O memory by an interrupt, and thereafter setting a refresh completion flag. CPUs that can be added.

According to such a configuration, it is possible to function as a CPU of a programmable controller by itself, and also to provide an external
While performing the I / O refresh execution process relating to the O area, in response to the setting of the refresh completion flag, the other CPU refers to the contents of the I / O memory and executes the user instruction to execute the multi instruction. It can be extended to a CPU type PLC.

In the invention described in claim 6 of the present application, the interrupt execution control means has a function of receiving multiple interrupts having different levels, and each time an interrupt request flag of each level is set, the I / O is executed. 6. The CPU as claimed in claim 5, wherein an I / O refresh execution process for a specific I / O area in the memory is performed by interruption, and thereafter, a refresh completion flag is set. .

According to such a configuration, while a multiple interrupt request is given from the outside to perform the I / O refresh execution processing for the specific I / O area corresponding to the interrupt level, the refresh completion flag is set. In response to this, the CPU can be expanded to a multi-CPU type CPU device by executing a user instruction from another CPU with reference to the content corresponding to the interrupt level in the I / O memory.

According to a seventh aspect of the present invention, there is provided an external connector including an interrupt line and a data input / output bus connected to a CPU of the programmable controller according to the fifth aspect. And a user program memory in which a user program is stored, cyclically sends an interrupt request to the external connector, and waits for a refresh completion notification to be obtained via the external connector. An additional CPU for a programmable controller is provided with a cyclic execution control means for executing a process of executing a user program stored in a program memory.

According to this configuration, when connected to the CPU according to claim 5 and used, the updated contents of the I / O memory are updated while the contents of the I / O memory are updated by owning the initiative. The user can refer to and execute his / her own user program, and can achieve a desired extended function without impairing the function of the original CPU.

According to the invention described in claim 8 of this application, the cyclic execution control means has a function of transmitting multiple interrupt requests having different levels in each unique cycle,
8. The additional programmable controller according to claim 7, wherein a user program execution process corresponding to each level is performed after the completion of the refresh is notified in response to the interrupt request of each level. In the CPU.

According to such a configuration, in addition to the effects described in the preceding section, a plurality of extension user programs having different input / output response times can be optimally executed.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings. The entirety of a programmable controller according to the present invention is shown in the block diagram of FIG.

As shown in FIG.
The U device 1 includes a main CPU 2 (a CPU that can be added) as a first CPU and a sub CPU (an additional CPU) 3 that is a second CPU.

In this example, the main CPU 2 and the sub CPU 3 are configured such that various circuit components described later are mounted on dedicated circuit boards, respectively, and the circuit boards are housed in dedicated housings.

The housing of the main CPU 2 has peripheral I
A connector 21 is provided for communicating with the I / O memory 27 and a connector 22 for enabling interruption to the MPU 23 from outside.
On the other hand, the housing of the sub CPU 3 is provided with a connector 31 for leading out the internal MPU bus B4 and leading out the internal interrupt signal line L2.

In the figure, L1 is the main CPU 2
The interrupt signal line wired inside, L2 is the sub CPU
3, an interrupt signal line L3, an interrupt signal line connecting the connector 31 and the connector 22,
Is the MPU bus in the main CPU2, B2 is the main CPU
B3 is an optional bus connecting the bus arbiter 28 and the connector 22, B4 is an MPU bus in the sub CPU 3, and B3 is an optional bus connecting the bus arbiter 28 and the connector 22.
5 is an optional bus connecting the MPU bus and the connector 31, and B6 is an optional bus connecting the connector 31 and the connector 22.

In the main CPU 2, an MPU (Micro Pr
ocesser Unit) 23, system program memory 2
4, system work memory 25, user program memory 26, I / O memory 27, bus arbiter 28, and the like.

The MPU 23 controls the overall operation of the main CPU 2. The MPU bus B 1 has a system program memory 24 and a system work memory 2.
5, user program memory 26, I / O memory 27,
A bus arbiter 28 and the like are connected.

The system program memory 24 is constituted by a non-volatile ROM, and stores therein a system program for defining the entire functions of the main CPU 2. The MPU 23 described above operates according to this system program.

The system work memory 25 is composed of a RAM, in which system work data indicating the operation state of the main CPU 2 and the progress of processing is stored.

The user program memory 26 is composed of a PROM, a flash memory or the like, and stores therein a user program such as a ladder program created by a user.

The I / O memory 27 is composed of a RAM, and stores therein an on / off state of peripheral I / O connected to the main CPU 2, a result of data operation performed by a user program, and the like.

The path arbiter 28 includes two CPUs 2 and 3
Has the function of adjusting the memory access to the I / O memory 27 from the I / O memory 27, whereby the I / O memory 27 can be referenced and updated from the sub CPU module via the optional CPU bus B5 in addition to the main CPU 2. It has been.

The peripheral I / O bus connector 21 performs a function for the main CPU 2 to perform I / O refresh for a peripheral I / O module (not shown).

On the other hand, in the sub CPU 3, M
A PU 31, a system program memory 32, a system work memory 33, a user program memory 34, and the like are stored.

The MPU 31 controls the whole of the sub CPU 3. The MPU bus B 4 is connected to a system program memory 32, a system work memory 33, and a user program memory 34.

The system program memory 32 is constituted by a non-volatile ROM, in which a sub CPU 3
The MPU 31 operates according to this system program.

The system work memory 33 is composed of a RAM, and stores therein system work data indicating the operating state of the sub CPU 3 and the progress of processing.

The user program memory 34 is composed of a PROM, a flash ROM, etc.
The user program of PU3 is stored.

An optional CPU bus B6 and an interrupt signal line L3 are wired between the main CPU 2 and the sub CPU 3. They are connectors 22, 31
It is detachably connected via.

The optional CPU bus B6 is a sub CPU
3 is a bus line for referring to and updating the I / O memory 27 in the main CPU 2. On the other hand, the interrupt signal line L3 is a signal for requesting an interrupt process from the sub CPU 3 to the main CPU 2.

Next, the main CPU 2 and the sub CPU 3
The configuration of the system program (that is, the operation of the system) will be described in detail with reference to the drawings in FIG.

As shown in FIG. 2, the main CPU 2
Is a common process (step 201) as a cycle process.
-User program execution processing (step 202)-I /
The O refresh processing (step 203) and the peripheral service processing (step 204) are performed, and the I / O memory 27 is referenced and updated in each processing (main CPU independent processing). Here, the user program execution processing (step 202) and the I / O refresh processing (step 203) are performed as shown in FIG.
This is performed for the area D of the I / O memory 27 functioning as a shared memory. That is, those processes (step 2
02, 203), the area D of the I / O memory 27 is allocated in advance.

Further, the main CPU 2 receives other interrupt levels 0 and 1 to 3 from the sub CPU 3 (steps 231, 232 and 233) as other processing.
The I / O refresh processing and the execution of the corresponding ladder task are performed for each I / O channel used in the designated interrupt task (steps 211, 212, and 213). At that time, the corresponding area (area A, area A, (Area B, area C)
Is being referenced and updated. Here, regarding the I / O refresh and the ladder task of the priority level 1 (step 211), the I / O functioning as a shared memory
The area A of the O memory 27 is used. Also, regarding the I / O refresh and the ladder task of the priority level 2 (step 212), the I / O functioning as a shared memory
The area B of the O memory 27 is used. Further, with respect to the I / O refresh and the ladder task of the priority level 3 (step 213), the I / O function as a shared memory
The area C of the / O memory 27 is used.

On the other hand, in addition to peripheral service processing (step 221) as cycle processing similar to that of the main CPU 2, the sub CPU 3 requests I / O refresh and interrupt tasks to be executed at any timing of the sub CPU 3 (step 231). 232, 233).

Next, the main CPU 2 by the sub CPU 3
Will be described. Main C
When performing three operation loop processes of 10 ms, 100 ms, and 1000 ms cycles in the sub CPU 3 without synchronizing with the processing cycle of the PU 2, the sub CPU 3 interrupts the main CPU 2 with I / O refresh and priority levels. Request the execution of ladder tasks 1 to 3.

That is, as shown in the flowchart of FIG. 3, when an interrupt I / O refresh execution request (step 301) is made on the sub CPU 3 side by a timer interrupt (scheduling function), the main CPU
2 is interrupted by level 0, and in response to this, the main CPU 2 executes an I / O refresh execution process (step 311). When the I / O refresh execution processing (step 311) is completed, the sub CPU 3
Is notified to the sub CPU
When the sub CP is recognized by the side (YES in step 302).
On the U3 side, an interrupt ladder task execution request is made (step 303), and in response to this, the main CPU 2 executes an interrupt ladder task execution process (step 312). 3 are executed (step 304). Note that, among the above processes, the interrupt ladder task execution request (step 303) is selectively performed as necessary.

As a result, the main CPU 2 and the sub CPU 3
Data exchange between the main CPU 2
Directly refers to the I / O memory reflecting the result of the I / O refresh from the sub CPU 3, or directly updates the contents of the I / O memory from the sub CPU 3, and displays the result in the I / O memory.
It is possible to output to the peripheral I / O by refreshing.

The I / O memory can be used as a shared memory by the function of the path arbiter 28 shown in FIG.
Access to is possible.

FIG. 4 is a timing chart showing the processing sequence of the main CPU 2 and the sub CPU 3. The sub CPU 3 performs 10 ms loop operation processing,
ms loop operation processing, 1000 ms loop operation processing
Are executed in parallel, and when the execution timing of each process conflicts, the priority (10 ms process> 100 m process)
s processing> 1000 ms processing).

The main CPU 2 basically performs cycle processing (common processing / user program execution / I / O refresh / event processing (steps 201 to 204)).
When the interrupt notification (interrupt task execution request) is received from the sub CPU 3, the interrupt program corresponding to the requested interrupt task ID is executed (steps 211, 212, and 213).

10 ms processing, 100 ms processing, 1000
The contents of the ms process and the contents of the process when the main CPU receives an interrupt notification are shown in the flowchart of FIG. Regarding each loop processing on the sub CPU side, a timer interrupt is generated at the timing of each loop, and the processing is started.

When the process is started, first, the priority and the interrupt task ID are set in the interrupt request flag F1, and the interrupt signal is turned on (step 501). Here, interrupt level 0 means I / O refresh, and interrupt levels 1 to 3 mean ladder task execution. When an interrupt request is issued, both I / O refresh and ladder task execution are started.

When the interrupt signal is turned on, the main CP
The U2 is interrupted by hardware, and then the priority / interrupt task ID is obtained from the interrupt request flag F1 (step 511). After that, I / O refresh (step 513) or execution of an interrupt program (step 515) is performed based on the priority and the interrupt task ID. That is, when the interrupt level is 0, the refresh is executed each time (step 513), and thereafter, it is notified that the refresh is completed (step 514). Executes the corresponding ladder task (step 515).

Thus, the refresh completion flag F
2 is notified, it is confirmed that refresh has been completed each time on the interrupt task (step 502).
Data is fetched from the O memory (step 50).
3) Perform arithmetic processing based on the I / O data (step 504). The contents of the arithmetic processing include starting the tasks of the sub and main CPUs of the corresponding loop based on the scheduling parameters. The sub CPU side performs PID operation and floating point operation, and the main CPU side performs ladder sequence processing. Is included. Thereafter, the obtained operation result is reflected on the I / O memory 27 (step 505).

Note that the interrupt request flag, refresh completion flag, task completion flag, scheduling parameters, and the like are described in the I / O memory (main CPU
It is arranged on an area that can be accessed by both the sub CPU and the data specifications are set as shown in FIG.

That is, one word of the interrupt request flag is composed of an interrupt task ID composed of D0 to D7, and D8 to D8.
It is composed of a priority level composed of D11 and an interrupt task execution request composed of D12.

One word of the refresh and task completion flag is 1000 ms processing refresh completion assigned to D00 and 100 ms assigned to D01.
Processing refresh completed, 10m allocated to D02
s processing refresh completed, 10 assigned to D03
00ms task execution completed, 10 assigned to D04
0ms task execution completed, 10m assigned to D05
The task has been completed.

As for the scheduling parameters, the interrupt cycle type, the data area head address, and the start ladder task ID are stored in association with each other (for example, a PID operator).

As is clear from the above description, the embodiment of the present invention has the following effects.

(1) Sub CP installed as an option
U can execute the processing of the main CPU in response to the interrupt notification, and the I / O in which the main CPU and the sub CPU share the entire area with the interrupt notification flag and the scheduling parameter.
Since the program is arranged on the memory, the execution order of the program can be easily and dynamically specified. As a result, sub C
The characteristics of the PU can be reflected in the control operation of the entire PLC system.

(2) While operating independently for each CPU,
Since data update is instructed by an interrupt at an arbitrary execution timing of the sub CPU, data transfer is synchronized. Therefore, stable cycle accuracy of the entire PLC can be secured without being affected by the delay of the scan time of each CPU.

(3) As the main CPU, resources (user memory and the like) and functions (high-performance instruction support) can be reduced by specializing in I / O control, so that a low-cost and simple PLC can be provided.

In the above embodiment, the present invention is applied to a so-called building block type PLC. However, the present invention is also applied to a so-called integrated PLC in which all input / output circuits and power supply circuits are housed in one case. Of course, you can.

As is apparent from the above description, according to the present invention, the expandability is excellent, and after the expansion,
The functions of each CPU can be maximized,
Further, a multi-CPU type PLC that can be manufactured at a relatively low price can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing a configuration of a CPU device according to the present invention.

FIG. 2 is a general flowchart showing an outline of processing between a main CPU and a sub CPU.

FIG. 3 is a flowchart showing an I / O refresh by an interrupt request and an execution procedure of an interrupt ladder task.

FIG. 4 is a timing chart showing a processing sequence of a main CPU and a sub CPU.

FIG. 5 is a flowchart illustrating an operation from a request for interrupt processing to completion of interrupt processing.

FIG. 6 is a memory map showing a configuration of an interrupt request flag and a refresh completion flag.

[Explanation of symbols]

 1 CPU device 2 Main CPU 3 Sub CPU 21 Connector for peripheral I / O bus connection 22 Connector 23 MPU 24 System program 25 System work memory 26 User program memory 27 I / O memory 31 Connector 32 System program memory 33 System work memory 34 User Program memory F1 Interrupt request flag F2 Refresh completion flag L1, L2, L3 Interrupt line B3, B5, B6 Optional MPU bus B2, B4 Internal MPU bus

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hideo Shimokawa Omron Co., Ltd. (10) Hanazono Todocho, Ukyo-ku, Kyoto-shi, Kyoto (72) Inventor Sakae Nishijima 210 Nakanuma, Minamiashigara-shi, Kanagawa Prefecture Fuji Photo Film Co., Ltd. F-term (reference) 5H215 BB20 CC05 CX03 GG01 KK04 5H220 BB20 CC05 CX03 DD04 EE07 JJ16 JJ26 JJ29 JJ38 JJ59

Claims (8)

[Claims] A first CPU, a second CPU, and a first CPU.
The second CP for the I / O memory built in the CPU
An option bus for enabling access from the U and an interrupt line for interrupting the first CPU from the second CPU, wherein the first CPU has a user program execution process A cyclic execution control means for cyclically performing the I / O refresh execution processing and the I / O refresh execution processing;
Interrupt execution control means for performing I / O refresh execution processing relating to a specific I / O area in the O memory by interruption, and thereafter notifying the second CPU of refresh completion;
Is provided at least, and the second CPU cyclically sends an interrupt request to the first CPU, and waits for a notification of refresh completion from the first CPU in response to the request. And a cyclic execution control means for performing a user program execution process. 2. An interrupt execution control means provided in the first CPU has a function of accepting multiple interrupts of different levels, and each time an interrupt request of each level arrives, the interrupt execution control means in the I / O memory is specified. The I / O refresh execution processing relating to the I / O area is performed by interruption, and thereafter, the completion of the refresh is notified to the second CPU, and the cyclic execution control means provided in the second CPU is unique. In this cycle, it has a function of sending multiple interrupt requests of different levels, and waits for the completion of refresh to be notified in response to the interrupt request of each level, and executes the user program execution processing corresponding to each level. The programmable controller according to claim 1, wherein: 3. The method according to claim 1, wherein the interrupt control means provided in the first CPU includes a specific user program execution process in addition to the I / O refresh execution process. Programmable controller. 4. The I / O in the first CPU is connected to a second CPU.
It is detachable from a connector including a bus line leading to a memory and an interrupt line in the first CPU. A user program executed by the first CPU is mainly a ladder task, and is executed by a second CPU. The programmable controller according to claim 1, wherein the user program to be executed is mainly a data operation task. 5. An I / O for storing a first external connection terminal connected to a peripheral I / O bus and an interrupt request flag and a refresh completion flag in addition to at least I / O data.
A specific user stored in the user program memory, having a memory, a second external connection terminal for enabling external access to the I / O memory, and a user program memory storing the user program For a program, cyclic execution control means for cyclically performing a user program execution process and an I / O refresh execution process; and an I / O memory related to a specific I / O area in an I / O memory when an interrupt request flag is set. And / or an interrupt execution control means for performing an I / O refresh execution process by an interrupt and thereafter setting a refresh completion flag. 6. The interrupt execution control means has a function of accepting multiple interrupts of different levels, and each time an interrupt request flag of each level is set, an I / O memory related to a specific I / O area in the I / O memory is set. 7. The CPU as claimed in claim 6, further comprising: executing an / O refresh execution process by interruption, and thereafter setting a refresh completion flag. 7. An external connector including an interrupt line and a data input / output bus connected to a CPU of the programmable controller according to claim 6, and a user program storing a user program. And executing a user program stored in the user program memory while sending a cyclic interrupt request to the external connector and waiting for a refresh completion notification to be obtained via the external connector. A CPU for adding a programmable controller, further comprising a cyclic execution control unit for performing processing. 8. The cyclic execution control means has a function of sending multiple interrupt requests of different levels in each unique cycle, and waits for the completion of refresh to be notified for each level of interrupt request. 8. The additional CPU for a programmable controller according to claim 7, wherein a user program execution process corresponding to each level is performed.