JPH09114775A - Multiprocessor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the competition of a system bus and to improve the processing efficiency of the whole of a system by using the cache a slave MCU as a RAM. SOLUTION: A slave MCU 2 performs a setting so as to use the cache 22 in the slave MCU 2 as an incorporated RAM and the normal operation program for slave MCU 2 is loaded into the incorporated RAM 22. Next, the slave MCU 2 performs the initialization on the side of the slave MCU 2, becomes the waiting of a normal operation and moves the control to a master MCU 1. The master MCU 1 starts the normal operation, and at the same time, starts the normal operation of the slave MCU 2 by using a control line 15 between master/ slave and the master/salve shared work area in a RAM 3. Thus, since the slave MCU 2 performs the normal operation by the program in the incorporated RAM 22, a system bus 4 is not always accessed, the competition of the master MCU 1 and a bus is not caused to efficiently operate the system.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system using a plurality of microcontroller units (abbreviated as MCU in this specification) in parallel.

[0002]

2. Description of the Related Art In order to improve the processing capacity of a system,
A multiprocessor system including a plurality of arithmetic processing units (MCU) is used.

[0003]

In the conventional multiprocessor system, the same bus is used for a plurality of arithmetic processing units. Therefore, even if the arithmetic processing capability is improved, the bus competition occurs. Has the problem of reduced efficiency. Also, when real-time processing such as communication is required, when bus contention occurs during interrupt processing,
The processing speed may decrease, which may cause a problem.

[0004] The present invention has been made in view of the above points,
The purpose is to reduce contention of the system bus in a multiprocessor system and improve the processing efficiency of the entire system.

[0005]

In order to achieve the above-mentioned object, a multiprocessor system according to the present invention uses a cache in a slave MCU as a RAM to perform processing in the slave MCU and external input / output to / from the slave MCU. For processing, access to the external bus was prevented.
Further, when data transfer between the master MCU and the slave MCU is required, the system timer interrupt processing routine of the master MCU is used as a reference for periodical execution.

By doing so, the slave MCU
Is operating normally on the built-in RAM, the period during which bus contention occurs is reduced. Further, since the period during which bus contention occurs is controlled, the efficiency of processing of the entire system can be improved.

[0007]

Embodiments of the present invention will be described below. FIG. 1 is a configuration diagram of a multiprocessor system according to an embodiment of the present invention. In the figure, 1 is a master MCU, 2 is a slave MCU, and 3 is a RAM, which are interconnected by a system bus 4.
Further, in the master MCU 1, 11 is a microprocessor (hereinafter abbreviated as MP), 12 is a cache, and 13
Is a peripheral module such as a communication interface (hereinafter abbreviated as communication I / F), 14 is an external terminal, and the slave MC
In U2, 21 is an MP, 22 is a cache (built-in RAM), 23 is a peripheral module such as a communication I / F, 24
Is an external terminal. Reference numeral 15 is a master / slave control line.

FIG. 2 is a diagram showing a timing relationship during steady operation of the multiprocessor system according to the present embodiment. (1) of FIG. 2 shows processes 31 and 32 by the system timer interrupt of the master MCU 1, Figure 2 (2)
Is a processing routine 33, 34, 35, 3 of the master MCU 1.
6, 37, 38, 39, 40, and (3) in FIG. 2 is a process 4 in which the slave MCU 2 accesses the system bus 4.
2 shows the internal processing routines 43, 44, 45, 46, 47, 48 of the slave MCU 2,
49 is shown.

Next, the operation of this embodiment will be described with reference to FIGS. First, before starting the steady operation, the slave MCU 2 has the cache 22 in the slave MCU 2
Is set to be used as built-in RAM, and the built-in R
The steady operation program for the slave MCU2 is loaded into the AM22. Next, the slave MCU 2
Initializes the U2 side, waits for steady operation, and transfers control to the master MCU1. Master M
At the same time as starting the steady operation, the CU1 uses the master / slave control line 15 and the master / slave shared work area in the RAM 3 to start the steady operation of the slave MCU2.

In the steady operation, as shown in (1) of FIG. 2, the master MCU 1 has a system timer interrupt 31,
32 ... Occurs periodically, and the master MCU 1 executes a series of processing routines 33 to 38 with reference to the interrupt 31. This state is shown in (2) of FIG. On the other hand, the slave MCU 2 is operated by a program in the built-in RAM 22 and can execute processing in the slave MCU 2, for example, the communication I / F in the peripheral module 23 and the external terminal 24.
It executes communication processing using, and internal data calculation processing. Here, as an example, the processing routine of the communication processing is shown in (4) of FIG. 2, and the communication processing 43 to 49 is performed by the interruption from the communication I / F. At this time,
Since the slave MCU 2 does not access the system bus 4, contention of the bus with the master MCU 1 does not occur, and the interrupt processing 43 to 49 for communication that requires real-time processing can be performed at high speed.

On the other hand, since it is necessary to transfer the data received by the slave MCU2 to the master MCU1, the master MCU1 is one of a series of processing routines as shown in (2) and (3) of FIG. As a result, control is transferred to the slave MCU 2 through the master-slave control line 15,
At the same time, the bus right of the system bus 4 is released. As a result, the slave MCU 2 accesses the system bus 4 (41) and uses the master / slave shared work area in the RAM 3 to exchange data with the master MCU 1. Here, as indicated by 42, when the slave MCU 2 accesses the system bus 4 and a communication interrupt occurs during the data transfer processing, the communication processing requiring real-time processing is prioritized and the data transfer processing is performed. Is suspended.

When the data transfer process is completed, the slave MCU 2 transfers control to the master MCU 1 through the master-slave control line 15, and at the same time releases the bus right of the system bus 4. The master MCU 1 executes the remaining processing routines 34 to 38, and when all the processing routines are completed, it waits for the next system timer interrupt 32, and the same operation is repeated thereafter.

As described above, since the slave MCU 2 normally operates according to the program in the internal RAM 22, the system bus 4 is not constantly accessed and the master M
No bus contention with CU1 occurs. Also, the master MCU
Data exchange between 1 and the slave MCU 2 is performed by the master MCU 1 and the slave MCU 2 using the system bus 4 in a time division manner with reference to a periodic system timer interrupt. Therefore, bus competition of the system bus 4 does not occur, and the multiprocessor system can operate efficiently.

In the above description, the master MCU 1
Although the system timer interrupt is used as the operation standard of the display control unit 51 in the system in which the display device 52 is controlled by the display control unit 51 connected to the system bus 4 as shown in FIG. Vertical sync signal (generally about 60 Hz cycle) of the master M
It is better to use it as the operation standard of CU1. That is,
System timer interrupt processing 31, 32 in (1) of FIG.
Is changed to vertical sync signal interrupt processing. this is,
This is because the amount of processing relating to display control is large and it is more efficient for the system to operate in the vertical cycle that is the basis of display control. Here, in FIG. 3, the same parts as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted.

Next, an example of an embodiment in which the multiprocessor system according to the present invention is applied to an information terminal device will be described. FIG. 4 is a diagram showing the outline of the configuration of an information terminal device using a multiprocessor system according to the present invention. The same parts as those in FIGS. 1 and 3 are designated by the same reference numerals and the description thereof will be omitted.

In FIG. 4, 55 is an input control unit,
56 is an input device, 60 is an information terminal device, and 61 is a communication line. A communication line 61 is connected to the information terminal device 60 for transmitting and receiving information, and an input device 56 and a display device 52 are connected for user operation. The information terminal device 60 includes control of the display device 52 and the input device 56, which requires complicated processing and a large amount of processing, and communication transmission / reception processing that requires real-time processing but has a small processing amount.

Therefore, in the information terminal device 60 to which the multiprocessor system according to this embodiment is applied, the master MCU 1 is the display device 52 and the input device 56.
And the slave MCU 2 performs data transmission / reception processing through the communication line 61. With such a configuration, the operation efficiency of the multiprocessor system can be improved and the information processing capability of the information terminal device can be improved.

Further, in the above description, the master MC
Although the system configuration of two MCUs of U and slave MCUs has been described, the operation similar to the above description can be performed even if there are two or more slave MCUs, and the same effect can be obtained.

[0019]

As described above, according to the present invention,
Since the slave MCU is operating steadily on the built-in RAM, the period in which bus contention occurs is reduced. Moreover, since the period during which the bus contention occurs is controlled, the processing efficiency of the entire system can be improved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a multiprocessor system according to an embodiment of the present invention.

FIG. 2 is a timing diagram for explaining an operation in the multiprocessor system according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram of a multiprocessor system according to another embodiment of the present invention.

FIG. 4 is a configuration diagram of an embodiment when a multiprocessor system according to the present invention is applied to an information terminal device.

[Explanation of symbols]

1 Master MCU (Master Microcontroller Unit) 2 Slave MCU (Slave Microcontroller Unit) 3 RAM 4 System Bus 11,21 Microprocessor (MP) 12 Cache 13,23 Peripheral Module 14,24 External Terminal 15 Master-Slave Control Line 22 cache (built-in RAM) 31, 32 master MCU system timer interrupt processing 33-40 processing routine of master MCU 41, 42 system bus access of slave MCU 43-49 internal processing routine of slave MCU 51 display control unit 52 display device 55 Input control unit 56 Input device 60 Information terminal device 61 Communication line

Claims (5)

[Claims] 1. In a multiprocessor system in which a master side microcontroller unit (MCU) and one or more slave side MCUs are connected to the same system bus, a period during which the slave side MCU accesses the system bus. And a MCU on the master side controls a period during which the MCU on the slave side accesses the system bus. 2. The multiprocessor system according to claim 1, wherein the slave side MCU can access the system bus at a predetermined cycle of the master side MCU. 3. The multiprocessor system according to claim 2, wherein the timing at which the MCU on the slave side can access the system bus is the vertical display cycle of the display device. 4. The cache memory according to claim 1, 2 or 3, wherein a cache memory built in a slave MCU is used as a built-in RAM to exchange data between a master MCU and a slave MCU. A multiprocessor system characterized in that the MCU on the slave side operates on internal RAM except for access to the system bus. 5. A multi-processor system according to claim 1, wherein a data input device, a data display device, and a communication line are connected to the multi-processor system. A multiprocessor system characterized in that an MCU on the master side controls a display device of data, and an MCU on the slave side performs transmission / reception processing of data via a communication line.