JPH05342026A - Multiprocessor and synchronization control system for multiprocessor - Google Patents

Abstract

PURPOSE:To enable multi-task processing without lowering the efficiency of each CPU by synchronizing the CPU surely at real time. CONSTITUTION:This system is provided with two CPU 1 and 2 for performing multi-task processing and since multiprocessor processing is performed by providing state registers 1b and 2b to set an interruption starting state for each CPU, data registers 1c and 2c to set data for exchanging processing between the CPU, and interruption starting means 1a and 2a to start interruption processing, synchronization control and data exchange chin be efficiently performed through the two kinds of accessable registers at high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor device for processing information using a microcomputer,
Particularly, the present invention relates to a multiprocessor device capable of efficiently performing multitask processing and its synchronous control system.

[0002]

2. Description of the Related Art When performing multitask processing in a single CPU system, processing of each task is executed at a fixed cycle and in a prescribed order.
Therefore, in the above system, when it is necessary to perform processing while synchronizing tasks, one task issues a synchronization request to another task via a flag on the shared memory and receives the request. When the processing order of tasks came around, the synchronization request was accepted and the processing was to be continued. Therefore, a delay occurs from the generation of the synchronization request to the execution, and the processing efficiency is low.

Therefore, a multiprocessor device having a plurality of CPUs has been proposed so that another task can process one task requiring synchronization. In a conventional multiprocessor device, a method of synchronizing via a dual port memory accessible from both CPUs has been used.

[0004]

However, in the above-mentioned conventional multiprocessor device, it is necessary to constantly monitor the dual port memory, and there is a problem that the monitoring is not practically real-time. ..

The present invention has been made in view of the above circumstances, and multi-task processing can be performed reliably and in real time between CPUs, and multi-task processing can be performed without reducing the efficiency of each CPU. An object of the present invention is to provide a processor device and a synchronous control method thereof.

[0006]

According to a first aspect of the present invention for solving the above-mentioned problems of the prior art, in a multiprocessor device, a first CPU for activating an interrupt and a second CPU for activating an interrupt are provided. CPU, an interrupt state register for setting an interrupt activation state for each CPU, a data register for setting data transferred between the CPUs, and an interrupt activation means for activating interrupt processing. There is.

According to a second aspect of the present invention for solving the problems of the conventional example, in the synchronous control system for a multiprocessor device according to the first aspect, the first CPU interrupts the second CPU. The activation state is confirmed by the interrupt state register on the second CPU side, and if it is not the interrupt activation state, the data to be delivered is set in the data register on the first CPU side, and the data on the first CPU side is set. It is characterized in that the interrupt starting means carries out interrupt starting to the second CPU.

According to a third aspect of the present invention for solving the above-mentioned problems of the conventional example, in the synchronous control system of the multiprocessor device according to the first aspect, the second CPU is a control circuit from the first CPU. When the interrupt is received, the second C
The interrupt state register on the PU side is set to an interrupt activated state, data is read from the data register on the first CPU side, processing is executed, and when the processing is completed, the interrupt on the second CPU side is executed. It is characterized by resetting the status register.

[0009]

According to the first aspect of the present invention, the CPU has two CPUs for performing multitask processing, and an interrupt state register for setting an interrupt activation state for each CPU, and a CPU.
Since it is a multiprocessor device having a data register for setting data for passing processing between them and an interrupt starting means for starting interrupt processing, synchronous control and data transfer are performed through two types of registers that can be accessed at high speed. It can be done efficiently.

According to the invention of claim 2, the first CP
U sets the interrupt activation state of the second CPU to the second CPU
2. The multi-processor according to claim 1, wherein the interrupt state register of FIG. Since the synchronous control system of the processor device is used, the synchronization can be reliably achieved, and unnecessary data sets and interrupt activation processing do not occur, and the efficiency of the CPU can be improved.

According to the invention of claim 3, the second CP
When U receives an interrupt from the first CPU, it sets the interrupt status register on the second CPU side to the interrupt activated state, reads the data register on the first CPU side, executes the process, and the process ends. Then, since the interrupt control register on the second CPU side is reset, the synchronous control system of the multiprocessor device according to claim 1 is used, so that another task process is not interrupted during execution of the task process. Therefore, it is not necessary to monitor the interrupt from the first CPU, and real-time processing can be realized.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a schematic configuration diagram of a multiprocessor device according to an embodiment of the present invention. The multiprocessor device of this embodiment comprises two central processing units CPU1 and CPU.
2 and interrupt starting means 1a provided for each CPU,
2a, interrupt status registers 1b and 2b, and interrupt data registers 1c and 2c.

The CPU 1 has an interrupt activation means 1a for the CPU 2, an interrupt state register 1b indicating the interrupt activation state of the CPU 1, and a data register 1c for setting data to be passed to the CPU 2, and similarly the CPU 2
Is an interrupt activation means 2a for the CPU 1, an interrupt state register 2b indicating an interrupt activation state of the CPU 2,
It has a configuration including a data register 2c for setting data to be delivered to the CPU 1.

Next, the outline of the processing operation of the synchronous control in the multiprocessor device of this embodiment will be described with reference to FIGS. 2 and 3.
Use to explain. FIG. 2 is a flowchart showing the processing of the synchronous control of the CPU 1 when the CPU 1 makes an interrupt request to the CPU 2, and FIG. 3 is a flowchart showing the processing of the synchronous control of the CPU 2.

As shown in FIG. 2, when the CPU 1 wants to issue an interrupt request to the CPU 2, the CPU 1 synchronously controls the interrupt status register of the CPU 2 in order to identify the interrupt activation status of the CPU 2. 2b is read (101), the CPU 2 determines whether or not the interrupt is being activated (102), and if it is being activated, this processing is repeated until it is not activated, and if not activated, it is necessary to synchronize. Data is set in the data register 1c for synchronization control (103), and finally the interrupt activating means 1a activates an interrupt to the CPU 2 (10
4), the processing of the CPU 1 ends.

Correspondingly, when the CPU 2 receives an interrupt request from the CPU 1, as shown in FIG. 3, it first sets in the interrupt status register 2b of the CPU 2 that the CPU 2 is in the interrupt starting state (201). ). Next, the synchronous data is read from the synchronous control data register 1c of the CPU 1 (202), the process is executed according to the read data (203), and finally the interrupt status register 2b of the CPU 2 is reset (204), the CPU
The process of 2 ends.

According to the multiprocessor device and its synchronization method of the present embodiment, the task processing is distributed to the two CPUs 1 and 2, so that tasks requiring synchronization can be processed by different CPUs. There is an effect that the efficiency of the CPU can be increased.

Further, when the synchronous control is performed between the CPUs, the state of each CPU is checked and the data is passed through the register which can be accessed at high speed, so that the delay in the synchronous control can be minimized. ..

Further, the CPU 1 which activates the interrupt confirms the state of the CPU 2 which is activated the interrupt by the interrupt state register 2b, and then sets the data and activates the interrupt. There is an advantage that the data space and loss time due to interrupt failure are eliminated, and the memory and CPU can be used efficiently.

Further, since the CPU 2 side receiving the interrupt sets the interrupt state in the interrupt state register 2b, an interrupt relating to another task process will not be applied during the task process, so it is necessary to monitor the interrupt. In other words, there is an effect that the efficiency of the CPU can be increased and the real-time processing property can be realized.

[0021]

According to the first aspect of the present invention, there is provided an interrupt state register which has two CPUs for performing multitask processing, and sets an interrupt start state for each CPU.
Since the multiprocessor device has the data register for setting the data for passing the processing between the CPUs and the interrupt starting means for starting the interrupt processing,
There is an effect that synchronous control and data transfer can be efficiently performed through two types of registers that can be accessed at high speed.

According to the invention of claim 2, the first CP
U sets the interrupt activation state of the second CPU to the second CPU
2. The multi-processor according to claim 1, wherein the interrupt status register is used to check, and if the interrupt is not activated, the data to be delivered is set in the data register of the first CPU and the interrupt activation means of the first CPU performs interrupt activation. Since the synchronous control method is used for the processor device, there is an effect that the synchronization can be surely achieved, unnecessary data sets and interrupt activation processing do not occur, and the efficiency of the CPU can be improved.

According to the invention of claim 3, the second CP
When U receives an interrupt from the first CPU, it sets the interrupt status register on the second CPU side to the interrupt activated state, reads the data register on the first CPU side, executes the process, and the process ends. Then, since the interrupt control register on the second CPU side is reset, the synchronous control system of the multiprocessor device according to claim 1 is used, so that another task process is not interrupted during execution of the task process. Therefore, it is not necessary to monitor the interrupt from the first CPU, and it is possible to achieve real-time processing.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a multiprocessor device according to an embodiment of the present invention.

FIG. 2 is a process flowchart of the CPU 1 of this embodiment.

FIG. 3 is a processing flowchart of the CPU 2 of this embodiment.

[Explanation of symbols]

1 ... CPU1, 1a ... Interrupt starting means of CPU1,
1b ... CPU 1 interrupt status register, 1c ... C
Data register for synchronous control of PU1, 2 ... CPU
2, 2a ... CPU2 interrupt activation means, 2b ... C
PU2 interrupt status register, 2c ... CPU2 synchronous control data register

Claims (3)

[Claims] 1. A first CPU that activates an interrupt, a second CPU that activates an interrupt, an interrupt state register that sets an interrupt activation state for each CPU, and data that is passed between the CPUs. A multiprocessor device characterized by having a data register for setting and an interrupt activating means for activating interrupt processing. 2. The first CPU is the second CPU
The interrupt activation state of the second CPU side is confirmed by the interrupt state register of the second CPU side, and if it is not the interrupt activation state, the data to be delivered is set in the data register of the first CPU side, and the first CPU side 2. The synchronous control system for a multiprocessor device according to claim 1, wherein the interrupt activation means activates an interrupt to the second CPU. 3. The second CPU is the first CPU.
Receives an interrupt from, sets the interrupt status register of the second CPU side to the interrupt activation status,
2. The interrupt state register on the second CPU side is reset when the data is read from the data register on the first CPU side to execute a process and the process ends. Synchronous control method for multiprocessor system.