JPH0351935A - Test method for dual port memory - Google Patents

Abstract

PURPOSE:To stop the access given from a processor of the remote side in a memory test state without performing the complicated inter-processor communication by stopping the working of the remote side processor in terms of hardware. CONSTITUTION:When a processor 1 performs a memory test of a dual port RAM 3, for example, an output 'HLT request' of an I/O port 4 is produced to a processor 2. The processor 2 stops temporarily the execution of an instruction as long as the processor 2 is ready to accept the 'HLT request' and shifts to an ideal state. At the same time, the processor 2 returns the 'HLT acknowledge' to the port 4. The processor 1 detects the 'HLT acknowledge' at the port 4 and confirms the temporary stop of the processor 2. When the processor 2 stops, the processor 1 can freely test all spaces of the RAM 3. Thus it is possible to stop the process of the remote side processor and to test this processor without performing the complicated inter-processor communication to the remote side processor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for testing a dual-port memory, and particularly to a method for testing a dual-port memory in a device in which two processors share the dual-port memory.

[Conventional technology]

Traditionally, the testing method for this kind of dual-port memory is
Even when one processor is accessing the dual-port memory, the other processor can access the dual-port memory asynchronously (by time-sharing resources), so (1) dual-port memory is primarily used. Method of testing using one processor (2) There is a method in which two processors stop processing on the other side through inter-processor communication with the other processor, and then test.

[Problem to be solved by the invention]

The conventional dual-port memory testing method described above is
In the case of method (1), it is possible to evaluate the memory element itself of the dual-port memory, but it is not possible to discover failures in the address decoder, bus control circuit, etc. on the side where the test is not executed, so the coverage rate of the test is low. There are drawbacks.

In the case of method (2), the drawbacks of method (1) are resolved, but in order to keep the other processor idling, a mechanism for synchronizing both processors, such as interprocessor communication or semaphores, is required. The disadvantage is that the software structure needs to be introduced and the software structure becomes complicated. If semaphores are implemented on dual-port memory, there are often restrictions on testing them. (Divide the memory and test so as not to destroy the semaphore area, etc.) [Means for solving the problem] The memory test method for the dual-port memory of the first invention is based on the method in which two processors have a bus arbitration function. In a device with a loosely coupled multi-processor configuration that uses a dual-port memory with a dual-port memory as a shared memory area, one of the processors prohibits the other processor from accessing the memory and reads/writes the memory element of the dual-port memory. It has circuitry and means for performing the test.

A memory test method for a dual-port memory according to a second invention is a method for testing a memory of a dual-port memory in a device having a loosely coupled multiprocessor configuration in which two processors use a dual-port memory with a bus adjustment function as a shared memory area. The dual port memory has means for inhibiting memory access of the processor by activating an interrupt program and performing read/write inspection of the memory element of the dual port memory.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an example of a dual port memory and its peripheral circuits for explaining a first embodiment of the present invention.

Processor l and processor 2 are dual port}
They share RAM 3 and are interconnected via I/O port 4. The dual-port RAM 3 has a built-in bus arbitration function between the two processors 1 and 2 and controls access competition, allowing the processors to read and write memory asynchronously without each processor being aware of accesses from the other. Therefore, if one of the processors were to read and write all the space in the dual-port RAM 3 for a memory test while each processor 1 and 2 is executing processing, the other processor could destroy the execution environment. Negative effects may occur, such as a runaway, or a write to a memory element during a memory test occurring from the other processor, which may appear as a write failure.

Therefore, in this embodiment, dual baud}
When it becomes necessary to perform a memory test of RAM3,
Output “HLT request” from I/O port 4 to the processor
is generated, and the I/O port 40 input is scanned and waits for the processor 2 to enter the pause state.

If the processor 2 is in a state where it can accept an "HLT request", it temporarily stops executing instructions, shifts to an idle state, and returns an "HLT acknowledge" to the I/O port 4.

Processor l can detect this at I/O port 4 and confirm that processor 2 has been temporarily stopped. Since most microprocessors have this "HLT request/acknowledge" mechanism built-in, it is possible to utilize it.

Once processor 2 has stopped, processor 1 is free to test all the space in dual-port RAM 3.

The reverse is also true when a memory test from processor 2 is required.

Which program/sa do you start the memory test from? In this case, it is impossible for the stopped processor to continue processing because its execution environment has changed.
The processor on the activation side notifies the operator of the test results without canceling HLT, and also notifies the operator of a message requesting restart of the system.

FIG. 2 is a block diagram showing a second embodiment of the invention.

The processor l shares the dual port RAM 3 with the processor 2 and is connected via the I/O baud 4A, and a part of the signal from the I/O baud 4A is decoded by the interrupt controller 5 and sent to the processor 2. A signal is input to processor 2 and similarly decoded by interrupt controller 6 .

When a need arises for a memory test in the processor L, the "master memory test" program is activated, issues a "memory test request" to the I/O port 4A, and sends a request from the I/O port 4A to the interrupt controller 6. Generates a memory test interrupt.

? It is decoded by the memory test interrupt controller 6 and starts the interrupt program "slave memory test" on the processor 2.

The interrupt program “Slave Memory Test” tests the memory space of all dual port RAM3 and
O-Boat 4A is used to return results and HLT (
Stop.

Processor 1 takes in the test results of processor 2,
After storing it in the register, the entire memory space of the dual port RAM 3 is tested and the result by the processor 2 is displayed or notified to the operator.

After the test is completed, processor 1 issues a system initialization interrupt to I/O board 4A, and the "master memory test" program ends.

The system initialization interrupt that has entered the I/O port 4A activates a "system initialization program" on the processors 1 and 2 as an interrupt service by the interrupt controllers 5 and 6.

〔Effect of the invention〕

As explained above, the present invention is capable of halting the operation of the other processor using hardware as in the first embodiment, or controlling it using a simple interrupt program as in the second embodiment. By configuring the hardware, it is possible to stop access from the other processor during a memory test without performing complex inter-processor communication, and with almost no consideration given to the other party's application program ( This has the effect of being able to perform memory tests (about setting interrupts enabled/disabled). Further, according to the second embodiment, after the test is completed,
The system can be initialized and restarted automatically.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
The figure is a block diagram showing a second embodiment of the present invention. 1...Processor, 2...Processor, 3...Dual port RAM, 4,4A...
...I/O port, 5...Interrupt controller, 6...Interrupt controller.

Claims (1)

[Claims] 1. In a device with a loosely coupled multiprocessor configuration in which two processors use dual port memory with a bus arbitration function as a shared memory area, one processor accesses the memory of the other processor. A method for testing a dual-port memory, comprising a circuit and means for performing a read/write test on a memory element of the dual-port memory while prohibiting the above-mentioned. 2. In a device with a loosely coupled multiprocessor configuration in which two processors use dual port memory with a bus adjustment function as a shared memory area, one processor starts a program that interrupts the memory access of the other processor. 1. A method for testing a dual-port memory, comprising means for performing a read/write test on a memory element of said dual-port memory by prohibiting said dual-port memory from performing a read/write test.