JP3187117B2 - One-chip microcomputer with built-in multiprocessor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a one-chip microcomputer used for executing various programs, and more particularly, to a multi-processor built-in one-chip having a technology for executing a plurality of programs in parallel on one chip. Related to microcomputers.

[0002]

2. Description of the Related Art Conventionally, one-chip microcomputers have been widely used for execution processing by programs used in various control fields such as manufacturing, measurement and inspection.

FIG. 2 is a diagram showing a configuration of a control system using the one-chip microcomputer. As shown, the main memory 1 stores a plurality of programs 1a.
And an execution thread 1c having program execution information such as a start address and initial values of registers and the like in order of execution priority of each program,
One-chip microcomputer 3 via memory bus 2
It is connected to the.

The one-chip microcomputer 3 has
A memory controller 4 for controlling access between the main memory 1 and the main body of the one-chip microcomputer 3, and a processor 5 for processing a program by referring to the main memory 1
And an input / output control unit 6 for controlling input / output between the processor 5 and an input / output device system outside the one-chip microcomputer 3.

The external input / output device system includes an input / output control unit 6
And a plurality of input / output devices 9 connected to the input / output bus 7 via a plurality of interfaces 8 , respectively.

[0006]

However, in the one-chip microcomputer 3 as described above, since there is only one processor 5 for processing a program, when executing a plurality of programs 1a, each program can be executed in parallel. There is a problem that parallel execution processing cannot be performed regardless of whether or not the processing is performed.

A plurality of programs 1a can be executed in parallel by mounting the individual one-chip microcomputers 3 in parallel. In this case, a special control circuit and software for controlling the plurality of microcomputers are required. There is a problem you need.

Since these control circuits and software perform complicated control such as interrupt control in parallel execution processing, for example, when one microcomputer processes a program, it is conscious of the processing of another microcomputer. It requires skill.

Further, when a control system is created, a plurality of microcomputers and their control circuits are added, so that there is a problem that the number of mounted components is increased and the reliability of the control system is reduced.

As a technique for solving these problems, it is conceivable to provide various control circuits and the like on one chip. However, while it is difficult to create such a complicated integrated circuit, it is difficult to form a parallel circuit with a simple configuration. A one-chip microcomputer capable of executing processing has not yet been proposed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has a multi-processor built-in one-chip microcomputer capable of completely executing a plurality of programs in parallel with a simple configuration without providing an external special control circuit. The purpose is to provide.

Another object of the present invention is to provide a one-chip microcomputer with a built-in multiprocessor that can execute an arbitrary program interrupt processing when a plurality of programs are processed in parallel.

[0013]

According to a first aspect of the present invention, a plurality of programs stored in a main memory and processable by any built-in processor in a single chip are read out in order of priority and are respectively processed in parallel. And, when the program registers execution information of a new program, a suspend instruction is sent to any other internal processor, and when an interrupt instruction is received from another internal processor, the current instruction is sent.
Execution information related to the currently executing program is stored in the main memory.
After returning , the program in the main memory is not allocated to another internal processor, processes the highest priority program, and has already sent or received the suspend instruction.
If there are no other built-in processors those other built-in
Interrupt instruction to any of the built-in processors
A plurality of built-in processors to be transmitted, and when one built-in processor of the plurality of built-in processors accesses the main memory, the other built-in processor does not access the main memory; A memory access control means for causing the other internal processor to access the main memory when the access to the internal processor has been completed, and the execution and interruption instructions sent from any of the plurality of internal processors to the other. a synchronous bus to notify the embedded processor, when sending the processing results of each internal processor to the outside, each embedded processor with respect to input and output devices and a output control means for access, the embedded processor it Re accesses the main memory, and a plurality of programs Which is a multi-processor-containing 1-chip microcomputer in parallel execution.

The input / output control means includes: when an interrupt request is received from a certain input / output device in order to interrupt another processing program from outside during parallel execution of a program by each built-in processor, Interrupt control means for registering execution information including the priority of the program in the main memory, and interrupting the parallel execution of the program by each built-in processor via the synchronous bus, and again executing the parallel execution of the program in priority order; It is provided with a configuration.

[0015]

Therefore, the invention corresponding to claim 1 takes the above-described means, and when a plurality of built-in processors execute parallel execution processing of each program, a certain built-in processor executes a program of a new program . when registering the execution information is sent an interrupt instruction to any other internal processor, in this optional embedded processor, receives an interrupt instruction from the certain internal processor, up currently running
After returning the execution information related to the program to the main memory,
Processes the highest priority program in main memory that is not assigned to another internal processor .
Other than those that have not sent or received the suspend command
Other internal processors, if any
Any interruption instruction to the internal processor sends out the, with is accessed by the memory access control means to the main memory of each embedded processor, input and output control means to the external input and output device each embedded processor it is accessed, and the synchronization bus by transmitting the execution and interruption instruction between the respective embedded processor, can be completely parallel execution of multiple programs in one-chip.

When an external interrupt control is performed, the interrupt control means registers the execution information of the interrupt processing program in the main memory when an interrupt request is received from a certain input / output device, and sets up the synchronous bus. While the parallel execution processing of each processor is interrupted through the respective processors, the interrupted processors execute the parallel execution processing of the programs again in priority order including the interrupt processing program by referring to the main memory. Any program can be interrupted during processing.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration of a control system using a one-chip microcomputer with a built-in multiprocessor according to the present invention. The same parts as those in FIG. 2 are denoted by the same reference numerals, and a detailed description thereof will be omitted. Only the different parts will be described.

That is, the device of the present invention comprises a plurality of built-in processors 1 instead of the one-chip microcomputer 3.
1, comprising a memory access control means 12, a synchronous bus 13, an input / output control means 14, and an interrupt control means 14a.
A chip microcomputer 15 is provided to execute a plurality of programs in the main memory 1 completely in parallel in one chip.

The plurality of built-in processors 11 read out the plurality of programs 1a in order of priority and perform parallel execution processing from a start address. The processor 11a sends execution and interruption instructions to each other based on the programs. Execution control unit 11b capable of specifying a start address
And

[0020] The memory access control means 12, an external memory bus 2, is connected to each processor unit 11a and the output control unit 14 of the embedded processor 11, while for access by each processor 11 to the main memory 1, It controls access of the input / output control means 14 to the main memory.

That is, the plurality of built-in processors 11
When the internal processor 11 _i is accessing the main memory, the other internal processor 11 is not allowed to access the main memory 1, and when the internal processor 11 _i has finished accessing the main memory 1, , And causes the other built-in processor 11 to access the main memory 1. In the case of interrupt processing by the input / output control unit 14 described later, the access of the input / output control unit 14 is prioritized over the access of the other internal processors 11.

The synchronous bus 13 is a bus for connecting the execution control section 11b and the input / output control means 14 of the plurality of built-in processors 11 in parallel with each other to transmit the execution and interruption instructions to each built-in processor.

Here, the input / output control means 14 is connected to the external input / output bus 7, each processor section 11a of the built-in processor 11, and the synchronous bus 13, and when each built-in processor 11 sends out a processing result to the outside. each embedded processor 11 to output device 9 has the function to access further interrupt control unit 1 for the interrupt processing
4a.

[0024] The interrupt control unit 14a is, from a certain output device 9 _i when receiving an interrupt request register interest information of the interrupt processing program in the execution thread 1c of the main memory 1, and the synchronization bus 13 Has the function of interrupting the parallel execution processing of each built-in processor 11 via the.

Next, such a multiprocessor built-in 1
The operation of the chip microcomputer will be described.
First, execution information of a program to be executed by the built-in processor 11 is registered in the execution thread 1c in the main memory 1 in order of priority. Here, the program execution information, execution priority of each program, and means information of an initial value such as the start address and register such, the registration, by a command from the program or the external input-output device input from 9 _i, This is performed via the output control means 14 and the memory access control means 12.

[0026] If the registration is performed before executing the program, each processor unit 11a, respectively to the main memory 1 through the memory access control unit 12 accesses, in order of priority that is registered in the execution thread 1c perform parallel execution processing program from the start address, and sends to the output device 9 of the outer portion through the output control means 14 results.

Next, a case where registration is performed during execution of a program will be described. First, when another program is registered according to an instruction from a certain program, the built-in processor 11 _i stores execution information including the priority of the another program in the main memory 1 via the memory access control means 12. And interrupts the parallel execution processing of an arbitrary one of the other internal processors 11, for example, the internal processor 11 _{i + 1} via the execution control unit 11b and the synchronous bus 13.

Built-in processor 11 whose processing has been interrupted
_{i + 1} returns the execution information relating to the currently executing program to the execution thread 1c, and designates the start address for re-executing the currently executing program to the execution thread 1c, and thereafter refers to the main memory 1. By doing so, the priority of the different program is compared with the priority of the currently executing program, a program with a higher priority order is selected and executed in parallel, and among the other built-in processors 11, The parallel execution process of any one other than the built-in processor 11 _i , for example, the built-in processor 11 _{i + 2} is interrupted.

Similarly, each of the built-in processors 11 sequentially compares the priorities of the currently executing program and the program priorities in the execution thread 1c including the priorities of the other programs. Since the high-priority program is processed in parallel, the separate program can be interrupted without interrupting the parallel execution of the entire one-chip microcomputer 15 during the parallel execution of the program.

Second, a case where an interrupt program is registered from a certain input / output device 9 _i will be described in the same manner as in the first case. First, when the interrupt control means 14 a receives an interrupt request from a certain input / output device 9 _i via the interface 8 and the input / output bus 7, execution information of the interrupt processing program is main- tained via the memory access control means 12. Register with the execution thread 1c in the memory 1, and
The parallel execution process of any one of the other built-in processors 11, for example, the built-in processor 11 _{i + 1} is interrupted via the synchronous bus 13 and each execution control unit 11b.

Built-in processor 11 whose processing has been interrupted
_{i + 1} returns the execution information relating to the currently executing program to the execution thread 1c, and designates the start address for re-executing the currently executing program to the execution thread 1c, and thereafter refers to the main memory 1. By doing so, the priority of the interrupt processing program is compared with the priority of the program currently being executed, and a program with a higher priority order is selected for parallel execution processing. The parallel execution process of any one other than the built-in processor 11 _i , for example, the built-in processor 11 _{i + 2} is interrupted.

Similarly, each of the built-in processors 11 sequentially executes one execution thread 1c including the priority of the program currently being executed and the priority of the interrupt processing program.
, And the higher priority programs are executed in parallel, so that the interrupt processing program can be executed without interrupting the parallel execution of the entire one-chip microcomputer 15 during the parallel execution of the programs. Can be interrupted.

[0033] As described above, according to this embodiment, when a plurality of embedded processor 11 is executed in parallel processing of each program, is accessed by the memory access control means 12 to the main memory 1 to the embedded processor with input and output control unit 14 is each embedded processor 11 to the external input-output device 9 is accessed, and, by synchronization bus 13 transmits the execution and interruption instruction between the respective processors, one complete A plurality of programs can be processed in parallel in a chip.

When another program is to be interrupted by an instruction from the program, the built-in processor 11 _i registers the execution information of the other program in the main memory 1, and The parallel execution processes of the internal processors 11 are sequentially interrupted, and the interrupted internal processors 11 sequentially refer to the main memory 1 and execute the programs in parallel in the priority order including the other programs. Computer 1
5, any program can be interrupted without interrupting the parallel execution of the entire program.

[0035] Similarly, when the output control unit 14 performs interrupt control, the interrupt processing main memory 1 execution information of the program when receiving an interrupt request from the output device 9 _i which there is an interrupt control unit 14a Register with and
The parallel execution processes of the internal processors 11 are sequentially interrupted via the synchronous bus 13, and the interrupted internal processors 11 sequentially refer to the main memory 1 and execute the programs in parallel in priority order including the interrupt processing program. Therefore, any program can be interrupted without interrupting the parallel execution of the entire one-chip microcomputer 15.

Next, a second embodiment will be described. This second embodiment, the execution thread 1c of the external main memory 1, a plurality programs by priority, or by embedded processor, each <br/> embedded processor 11 and input to respect the plurality of execution threads This is a configuration in which a memory access control unit for accessing the output control unit 14 is provided.

Since the memory access control means is provided corresponding to a plurality of execution threads, even if the ratio of parallel execution processing is increased due to system expansion or the like, a plurality of programs are executed in parallel in one chip. be able to.

As described above, according to the second embodiment,
Since the memory access control means corresponding to a plurality of execution threads is provided, the ratio of parallel execution processing in one chip can be increased, and the speed of parallel execution processing can be improved.

Next, a third embodiment will be described.
A plurality of external memory bus 2 and an input-output bus 7, the memory access control means and the embedded processor 11 and the input-output control unit 14 to access to their memory bus, each embedded processor for those input-output bus 11 is a configuration in which the input and output control means for access to.

By providing these memory access control means and input / output control means corresponding to the plurality of external buses, the ratio of parallel execution processing by each built-in processor 11 is increased, and the program in the entire one-chip microcomputer 15 is controlled. Can be improved in parallel execution processing speed.

As described above, according to the third embodiment,
Since the memory access control means and the input / output control means corresponding to the expansion of the external system are provided, even if the ratio of the parallel execution processing increases, each of the built-in processors 1
Since access to 1 turtle-memory and input-output device, it is possible to improve the processing speed with an increase in said ratio.

Although the present invention has been described in the context of interrupting a program, each built-in processor 11 is sequentially interrupted to execute a program with a higher priority in parallel. The same can also be implemented by interrupting and executing a higher priority program in parallel. In addition, the present invention can be implemented with various modifications without departing from the scope of the invention.

[0043]

As described above, the present invention has the following effects.

According to the first aspect of the present invention, a plurality of built-in processors are provided.
When a program executes each program in parallel,
At the Rossesa, the program is a new programExecution information
InformationIf you register, interrupt any other built-in processor
Instruction, and this optional internal processor
When an interrupt instruction is received from the built-in processor,Currently running
After returning the execution information related to the program to the main memory
ToOther internal processors with programs in main memory
Process the highest priority program that is not assigned to
ReasonOther than sending or receiving the suspend command
Other internal processors, if any.
Send a suspend instruction to any of the embedded processors
And the memory access control means names each built-in processor.
MemoryAAccess and I / O control
Means to connect each built-in processor to an external input / output deviceA
Access and a synchronous bus between each embedded processor.
Execution and abort instructions are now transmitted, so external
Without providing a special control circuit, multiple
A multiprocessor that can execute programs completely in parallel
It is possible to provide a one-chip microcomputer with a built-in memory.

According to a second aspect of the present invention, when performing an external interrupt control, the interrupt control means registers the execution information of the interrupt processing program in the main memory when receiving an interrupt request from a certain input / output device. While the parallel execution processing of each built-in processor is interrupted via the synchronous bus, each of the interrupted built-in processors executes the parallel execution processing of the programs again in priority order including the interrupt processing program by referring to the main memory. A multi-processor built-in one-chip microcomputer capable of interrupting an arbitrary program when the above-mentioned program is processed in parallel.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a control system using a one-chip microcomputer with a built-in multiprocessor according to the present invention.

FIG. 2 is a diagram showing a configuration of a control system using a conventional one-chip microcomputer.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Main memory, 1a ... Plurality of programs, 9 ... I / O device, 10 ..., 11 ... Plurality of built-in processors, 12 ...
Memory access control means, 13: synchronous bus, 14: input / output control means, 15: one-chip microcomputer with built-in multiprocessor.

Continuation of front page (56) References JP-A-62-210564 (JP, A) JP-A-60-254358 (JP, A) JP-A-62-152064 (JP, A) JP-A-2-244252 (JP) JP-A-3-257634 (JP, A) JP-A-3-144847 (JP, A) JP-A-58-87645 (JP, A) JP-A-1-121968 (JP, A) 1-270147 (JP, A) JP-A-3-17756 (JP, A) JP-A-52-67930 (JP, A) JP-A-64-1048 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 15/16-15/177

Claims (2)

(57) [Claims] 1. A plurality of programs which are stored in a main memory and can be processed by any built-in processor in one chip are read out in order of priority and are respectively processed in parallel, and the program executes execution information of a new program. When registering, an interrupt instruction is sent to any other internal processor, and when an interrupt instruction is received from another internal processor , execution information related to the program currently being executed is stored.
After returning to the main memory, the program in the main memory processes the highest priority program that has not been allocated to another internal processor and has already sent or
If any other internal processor is not receiving it,
To any of the other embedded processors
A plurality of built-in processors for sending a suspend instruction, and when one built-in processor is accessing main memory, the other built-in processors are not allowed to access the main memory;
When the access to the main memory of the certain built-in processor is completed, the memory access control means causes the other built-in processor to access the main memory; a synchronous bus to notify the execution and interruption instruction to another embedded processor, when sending the processing results of each internal processor to the outside, and a output control means for access by contrast input and output device each embedded processor accesses to each of the integrated processor, respectively it main <br/>-memory, and multi-processor-containing one-chip microcomputer, which comprises parallel execution processing a plurality of programs. 2. An input / output control means for receiving an interrupt request from a certain input / output device in order to interrupt another processing program from outside during parallel execution of a program by each built-in processor. Register the execution information including the priority in the main memory, and
2. A multi-processor built-in 1-chip as claimed in claim 1, further comprising an interrupt control means for causing each of the built-in processors to interrupt the parallel execution of the program via the synchronous bus and to execute the parallel execution of the program again in the order of priority. Microcomputer.