JPS63265353A - Multi-processor system - Google Patents

Abstract

PURPOSE:To instantaneously stop and restart the operations of slave processors by executing the output control of a bus holding request signal to each slave processor via a bus holding request line by a master processor. CONSTITUTION:When the operations of slave processors 2a-2n are interrupted, the bus holding request signals are outputted to a bus holding request line 6 via a bus holding request line control circuit 8 of the master processor 1 and then sent to the bus holding circuit 9 of processors 2a-2n respectively. Thus the execution of programs are inhibited by the circuits 9 for processors 2a-2n. When the operations of the processors 2a-2n are started again, the output of the bus holding request signal given from the circuit 8 is stopped. Thus the execution of programs inhibited by the circuits 9 are released and the operations of processors 2a-2n are restarted. In this case, the stop and restart of operations of processors 2a-2n are carried out almost simultaneously with the control of the output state of the bus holding request signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiprocessor system having a master processor and a plurality of slave processors.

[Prior Art] FIG. 4 is a block diagram showing a conventional multiprocessor system disclosed in, for example, Japanese Unexamined Patent Publication No. 55-39908. In the figure, 1 is a master processor, 2a, 2b
, . . . , 2n are all slave processors whose operations are controlled by the master processor 1, 3 is a data bus line that connects the master processor 1 and the slave processors 28 to 2n, and 4 is the master processor 1 and slave processor 2a. A single interrupt request line, 5, which couples .about.2n to each other, is a shared memory connected to each master processor 1 and slave processors 28 to 2n via data bus line 3.

Next, the operation will be explained. I want to interrupt the execution of slave processors 28 to 2n by master processor 1.
In this case, the master processor 1 first uses the shared memory 5
After a program writes a re-interruption request to the transmission area for each slave processor 2a to 2n within, the interrupt request s4 is made significant and an interrupt request is generated. This interrupt request is input to master processor 1 and all slave processors 28-2n.

Then, each slave processor 28 to 2n sequentially reads the transmission area in the shared memory 5 assigned to each processor 2a to 2n according to the usage priority of the data bus 11A3, judges the contents, and executes it programmatically. Interrupt.

In addition, master processor 1 controls slave processor 2.
When resuming execution of a to 2n, the master processor 1 uses the shared memory 5 as in the case of the above-mentioned interruption request.
After a program writes a restart request to the transmission area for each slave processor 28 to 2n, one interrupt request is generated, and each slave program 2a to 2n resumes execution programmatically by reading each transmission area. .

[Problems to be Solved by the Invention] Conventional multiprocessor systems are configured and controlled as described above, and control for suspending and resuming execution of the slave processors 2a to 2n is realized by a program. It is impossible to control the execution of the slave processors 2a to 2n at the same time, and there are problems in that a complicated program is required.

This invention was made to solve the above-mentioned problems, and provides a multiprocessor system in which a master processor can immediately control execution suspension and resumption of slave processors without using a program. The purpose is to

[Means for Solving the Problems] A multiprocessor system according to the present invention includes a single bus hold request line between a master processor and each slave processor, and transmits a bus hold request to the bus hold request line. A bus hold request line control circuit for controlling signal output is provided in the master processor, and program execution is prohibited while receiving a bus hold request signal from the bus hold request line control circuit via the bus hold request line. A bus hold circuit is provided in each of the slave processors mentioned above.

[Function] In the multiprocessor system according to the present invention, when a request is made to interrupt the execution of each slave processor.

The bus hold request line control circuit of the master processor outputs a bus hold request signal to the bus hold request line and sends it to the bus hold circuit in the slave processor, and this bus hold circuit inhibits program execution in the slave processor. . Also,
When a request is made to resume execution of the slave processor, by stopping the output of the bus hold request signal from the bus hold request line control circuit, the inhibited state of program execution by the bus hold circuit is released, and the execution of the slave processor is canceled. will be resumed.

[Embodiment of the Invention] An embodiment of the invention will be described below with reference to the drawings. 1st
In the figure, the same reference numerals as in FIG. 4 indicate the same or equivalent parts, 6 is a single bus hold request line that connects the master processor 1 and slave processors 2a to 2n, and 7 is a bus hold request line for each of the processors 1, 2a to 2n. The core microprocessor LSI, 8 is microprocessor LSI 7
A bus hold request line control circuit (see FIG. 2) in the master processor 1 controlled by the bus hold request line 6, which controls the significance/insignificance of the bus hold request line 6 (the significant state corresponds to the output state of the bus hold request signal). It is. 9 is a bus hold circuit in each slave processor 28 to 2n (see FIG. 3), and while the bus hold request line 6 is significant (while the bus hold request signal is being output), the bus hold circuit in each slave processor 2a to 2n is This prohibits program execution.

FIG. 2 shows an example of the configuration of the bus hold request line control circuit 8. In FIG. 2, 10 is a D flip-flop, and 11 is an inverter type driver that receives the Q output of the D flip-flop 10. The output thereof is connected to the bus hold request line 6. Further, 12 is a bus hold request set line for setting the D flip-flop 10, 13 is a bus hold request reset line for resetting the D flip-flop 10, and 14 is an initialization signal input line for the master processor 1.

Furthermore, FIG. 3 shows an example of the configuration of the bus hold circuit 9. In FIG. 3, 15 indicates a bus hold request line 6.
Inverter type receiver with input, 16 is OR
The output of the receiver 15 and the internal bus hold request line (directly connected to the bus hold request line 6) 17 of each slave processor 2a to 2n are input to the gate, and its output is used as the bus usage right of the microprocessor LSI 7. It is connected to the control terminal (HOLD).

Next, the operation will be explained. When the master processor 1 wants to interrupt the execution of the slave processors 28 to 2n, the master processor 1 first makes the bus hold request set line 12 significant and switches the D flip-flop 1o.
By setting , the bus hold request line 6 is made significant (that is, the bus hold request signal is output).

When the bus hold request line 6 is present or active, the receiver 15 and the OR
The bus right control terminal (HOLD) of the microprocessor LSI 7 becomes significant through the gate 16, and after a few microseconds, the microprocessor LSI 7 relinquishes the right to use the data bus, suspends processing, and prohibits the execution of a new program. .

In addition, master processor 1 controls slave processor 2.
When restarting execution of steps a to 2n, master processor 1 switches bus hold request reset line 13 from L level to H level and resets D flip-flop 10, thereby inadvertently disconnecting bus hold request line 6. (i.e., stop outputting the bus hold request signal)
.

When the bus hold request IIA6 becomes invalid, the receiver 15 and O
The bus right control terminal (HOLD) of the microprocessor LSI 7 becomes inactive via the R gate 16, and after a few microseconds, the microprocessor LSI 7 starts programming from the next process after the process for which the bus right was relinquished due to an interrupt request. Resumes execution.

In this way, in the past, interrupt/resume requests were realized by a program by writing to or reading from the shared memory 5, but according to this embodiment, the bus hold request signal from the master processor 1 is realized without using a program. By controlling the output state of the slave processors 2a to 2n, execution suspension and resumption in the slave processors 2a to 2n can be controlled immediately almost simultaneously with the output of the request signal.

In the above embodiment, the master processor 1 and the slave processors 28 to 2n each have a built-in microprocessor LSI 7, but the bus hold request line control circuit 8 and the processors 2a to 2n are prohibited from using a new bus. Any configuration may be used as long as the bus hold circuit 9 can be configured.

[Effects of the Invention] As described above, according to the present invention, a master processor and each slave processor are interconnected by a bus hold request line, the master processor is provided with a bus hold request line control circuit, and the slave processor is provided with a bus hold request line control circuit. Since the processor is provided with a bus hold circuit, it is possible to suspend and resume execution in the slave processor almost simultaneously with controlling the output state of the bus hold request signal without using a program.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a multiprocessor system according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing a configuration example of a bus hold request line control circuit in the above embodiment, and FIG. FIG. 4 is a circuit diagram showing an example of the configuration of a hold circuit. FIG. 4 is a block diagram showing a conventional multiprocessor system. In the figure: 1-master processor, 2a; 2b,..., 2n--slave processor, low-pass hold request line, 8--bus hold request line control circuit,
9-Bass hold circuit. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] In a multiprocessor system consisting of a master processor and a plurality of slave processors controlled by the master processor, a single bus hold request line is provided between the master processor and each of the slave processors, and the master processor A bus hold request line control circuit is provided for controlling the output of a bus hold request signal to the bus hold request line, and
Each of the slave processors is provided with a bus hold circuit that inhibits program execution while receiving a bus hold request signal from the bus hold request line control circuit via the bus hold request line. processor system.