JPH1165994A - Bus control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To first execute bus access based on a bus access request having the higher priority than a bus request, with which the bus access under execution at present is executed, when such a bus access request is issued. SOLUTION: When the bus access request having the higher priority than the bus access request, with which the bus access under execution at present is executed, is issued, a bus access interrupting means A interrupts the bus access under execution at present and after that bus access is interrupted, the bus access based on the said issued bus access request is first executed by a first bus access executing means B and after that bus access is finished, the said interrupted bus access is executed again by a bus access re-executing means C.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus control circuit.

[0002]

2. Description of the Related Art Conventionally, a bus control circuit which receives a bus access request from a CPU (Central Processing Unit) or the like and performs bus arbitration and bus access control judges whether or not bus access is possible. If it is, according to the set priority, the bus access requester having issued the bus access request has the highest priority and executes the bus access.

There is a case where it is desired to temporarily suspend a bus access being executed from a certain bus access request and execute a bus access by another (highly urgent) bus access request in advance. Conventionally, even if another bus access request is issued, it is not possible to execute the bus access by the bus access request unless the user waits until the currently executed bus access ends.

[0004] For this reason, for example, one disclosed in Japanese Patent Publication No. 1-402017 has been proposed. This relates to a multi-processor in which a plurality of processors share one bus, and issues a bus acquisition acknowledgment to a processor with a lower priority in a provisional manner, and the processor actually starts access by the bus acquisition acknowledgment. If a processor with a higher priority issues a bus acquisition request before this, the processor with a higher priority is made to use the bus.

[0005]

However, in the device described in Japanese Patent Publication No. 1-4017, the acquisition of a bus for a processor having a lower priority is approved (the use of the bus is permitted) and then the processor is actually executed. Only within a short time before the user starts using the bus can the bus acquisition approval be revoked. In other words, once a low-priority processor starts using the bus, a high-priority processor cannot use the bus until the use ends.

According to the present invention, when a bus access request issued with a higher priority than a bus access request that has caused a currently executed bus access is issued, the bus access request by the bus access request is issued. The purpose is to enable access to be performed in advance.

[0007]

According to the present invention, there is provided a bus control circuit for receiving a bus access request and performing bus arbitration and bus access control.
As shown in the functional block diagram of FIG. 1, when a bus access request having a higher priority than the bus access request that caused the currently executing bus access to be executed is issued, the currently executing bus access is interrupted. Bus access suspending means A for causing the bus access to be executed in advance of the bus access request issued after the bus access is interrupted by the means A;
A bus access re-executing means C for re-executing the interrupted bus access after the bus access executed by the means B is completed.

Further, when the bus access is interrupted by the bus access interrupting means A, it is preferable to provide a dummy access executing means for performing a dummy access in order to keep the device-specific timing regulation. Alternatively, it is preferable to provide a state determination unit that determines whether the currently executed bus access is in a state in which the bus access can be interrupted.

In the bus control circuit according to the present invention, when a bus access request having a higher priority than the bus access request that has executed the currently executed bus access is issued, the bus access suspending means A of FIG. Interrupts the currently executing bus access, and after the bus access is interrupted,
The bus access preceding execution means B executes the bus access according to the issued bus access request in advance, and after the bus access is completed, the interrupted bus access is executed by the bus access re-execution means. Since C is re-executed, system performance can be improved and hardware resources can be simplified.

[0010] For example, when comparing read access and write access to the main memory, the relevance to the next operation is generally higher in read access. That is, the read access to the main memory is performed to use the data obtained by the read access in the immediately subsequent data processing, so that the subsequent processing stops until this data is obtained. Often.

On the other hand, with regard to write access to the main memory, this write data is not often used in the immediately subsequent processing, and is therefore stored in a write buffer instead of the main memory write. In advance, it is possible to execute the write to the main memory later without deteriorating the processing performance. Therefore, the performance can be improved by interrupting the currently executed write access and executing the read access first.

As another example, in a DMA controller that reads data from a main memory and outputs the data to the outside at a fixed cycle, the time from when a read access request is obtained until read data is obtained is obtained. Since the capacity of a FIFO (first in first out) memory as a buffer is determined based on the worst case, if the time of the worst case can be shortened, the capacity of the FIFO memory can be reduced and hardware resources can be simplified. .

Further, when the bus access is interrupted by the bus access interrupting means A, if a dummy access is performed in order to observe the timing regulation specific to the device, a device having a timing regulation such as a minimum pulse width can be used. On the other hand, the adverse effects of the interruption do not occur. Alternatively, if it is possible to determine whether or not the currently executed bus access is in a state in which the bus access can be interrupted, it is possible to perform an access optimized for the specification of the bus access target, and to ease design constraints in circuit design. Can be.

[0014]

Embodiments of the present invention will be specifically described below with reference to the drawings. FIG. 2 is a block diagram showing a configuration example of a control system in an electronic device including a bus control circuit embodying the present invention.

In FIG. 2, reference numeral 1 denotes a CPU (Central Processing Unit), which has a cache memory therein.
Therefore, access to the outside occurs only when instructions or data cannot be supplied from the internal cache memory. A bus control circuit 2 receives a bus access request from the CPU 1 and performs bus arbitration and bus access control. Reference numeral 3 denotes a ROM, 4 denotes a DRAM, and 5 denotes an SRAM.

Reference numeral 106 denotes an extension board (extension board).
It is connected via a general-purpose expansion connector (not shown). In this case, the same expansion board is not always connected, but an arbitrary one is selected from various expansion boards depending on the application and can be connected. In other words, various specifications will be connected.
7 is a CPU bus, and 8 is a local bus.

FIG. 3 is a diagram showing a detailed example of an external interface signal of the bus control circuit 2. In FIG. 3, SA
D, CMD, CACK_, and EVAL_ are signals of the CPU bus 7 and signals for interfacing with the CPU 1. The description of the individual characteristics of these signals will be complicated and will not be described because they are not directly related to the present invention.

The other signals are as follows. First, LAAddr is an address bus signal for SRAM5, ROM3, and expansion board 6, and SRAMCS_ is SR
The chip select signal for AM5, ROMCS_ is R
A chip select signal EXTCS_ for the OM3 is a chip select signal for the extension board 6.

OE_ and WE_ are SRAMs, respectively.
5 are an output enable signal and a write enable signal commonly used in the extension board 5 and the extension board 6. RA, R
AS_, CAS_, and RWE_ are control signals for the DRAM 4, RA is an address bus signal, and RAS_ is a low signal.
An address strobe signal, CAS_ is a column address strobe signal, and RWE_ is a write enable signal.

EXACK_ is a signal asserted by the extension board 6 when the extension board 6 is accessed, and indicates that the current bus access may be terminated by assertion of this signal. This is to make the access time of the extension board 6 flexible. EXENABLE_ is
This indicates whether or not the extension board 6 is in a state in which interruption is possible, and the extension board 6 drives.

An underbar (_) at the end of a signal name indicates that the signal is active low. Further, this bus control circuit functions as the bus access suspending means A, the bus access preceding execution means B, and the bus access re-execution means C of claims 1 to 3 shown in FIG. Further, it also functions as the dummy access execution means of claim 2 or the state determination means of claim 3.

FIG. 4 shows an extension board write request (write request to the extension board 6) and the DR in the bus control circuit 2.
FIG. 9 is a diagram illustrating an operation when an AM read request (a read request to the DRAM 4) occurs.

In FIG. 4, at the beginning, it is on the far left,
Move to the right over time. The location where the CPU request is written indicates the content of the request issued by the CPU 1 at that time, and the portions where the extension board and DRAM are written are control signals for the extension board 6 and DRAM 4 respectively. (Excluding the data bus) shows the contents of the operation at that time.

LD indicates what the data bus is currently using. EXENABLE_ is
This is a signal driven by the extension board 6 indicating whether or not the extension board 6 is in a state in which it can be interrupted. STOP is a bus control circuit 2 for interrupting the currently executed access.
The internal signal PENDING is an internal signal of the bus control circuit 2 indicating that the operation is suspended.

First, when viewed from the left, the CPU 1
Request to the expansion board 6 from the server (bus access request)
Has been issued. Then, this request is permitted, and write access (bus access) to the extension board 6 is executed. During execution of the write access, a read request (another bus access request) to the DRAM 4 is issued from the CPU 1 as a new request.

In this embodiment, the read request from the DRAM 4 is set higher in priority than the write request to the extension board 6, and the signal EXENABLE
Since it is indicated that interruption is possible through E_, the bus control circuit 2 determines that the currently executed write (bus access) to the extension board 6 is in an interruptable state (indicated as interruptable). If not, it is determined that the interrupt is not possible.) An interrupt request is issued internally, and a read from the DRAM 4 is performed with the status indicating that the interrupt is being set.
Start access (bus access). Then, after the read access is completed, the interrupted write access (bus access) to the extension board 6 is executed again.

FIG. 5 shows an SRAM in the bus control circuit 2.
Write request (write request to SRAM5) and DR
FIG. 9 is a diagram illustrating an operation when an AM read request (a read request to the DRAM 4) occurs. Here, first, a write request to the SRAM 5 (a bus access request)
Is issued, and a write access (bus access) to this is started.

Thereafter, a read request (another bus access request) to the DRAM 4 is issued, and the read request to the DRAM 4 is more effective than the write request for executing the write access to the SRAM 5 being executed at that time. In this embodiment, since the priority is high, the write access to the SRAM 5 is interrupted, and the read access from the DRAM 4 is stopped.
Start access.

The write access to the SRAM 5 is continuously executed in the form of a dummy access. this is,
This is executed to keep the minimum pulse width and the like of the timing regulation of the SRAM 5. However, data bus (LD)
Are shared with the DRAM 4 and are used for read access from the DRAM 4.

Therefore, the data written in the SRAM 5 is undefined. However, since the dummy write (dummy access) is performed so as to satisfy the minimum timing specification for the SRAM 5, after the read access from the DRAM 5 is completed, the write access to the SRAM 5 is re-executed. Data will be correct.

[0031]

As described above, according to the bus control circuit of the present invention, when a bus access request having a higher priority than the bus access request that has executed the currently executed bus access is issued. Suspending the currently executed bus access, suspending the bus access, executing the bus access according to the issued bus access request in advance, and terminating the bus access after the bus access ends. Since the re-executed bus access is performed, system performance can be improved and hardware resources can be simplified.

Further, according to the bus control circuit of the present invention, when the bus access is interrupted, the dummy access is performed in order to observe the timing regulation unique to the device. Even for a certain device, there is an effect that the adverse effect of the interruption is not generated. According to the bus control circuit of the third aspect of the present invention, it is determined whether or not the currently executed bus access is in a state in which the bus access can be interrupted. In addition, it is possible to relax design constraints in circuit design.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing a basic configuration of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a control system in an electronic device including a bus control circuit embodying the present invention.

FIG. 3 is a diagram showing a detailed example of an external interface signal of the bus control circuit 2 of FIG. 2;

FIG. 4 is a diagram showing an operation when an extended board write request and a DRAM read request occur in the bus control circuit 2 of FIG. 2;

FIG. 5 is a diagram showing an operation when an SRAM write request and a DRAM read request are generated.

[Explanation of symbols]

 1: CPU (Central Processing Unit) 2: Bus control circuit 3: ROM 4: DRAM 5: SRAM 6: Expansion board 7: CPU bus 8: Local bus

Claims (3)

[Claims] 1. A bus control circuit for receiving a bus access request and performing bus arbitration and bus access control, wherein the bus access request has a higher priority than the bus access request that has executed the currently executed bus access. Is issued, a bus access suspending means for suspending the bus access currently being executed, and after the bus access is suspended by the means, the bus access by the issued bus access request is executed in advance. A bus control comprising: a bus access preceding execution means; and a bus access re-execution means for re-executing the interrupted bus access after the bus access executed by the means is completed. circuit. 2. The bus control circuit according to claim 1, wherein
A bus control circuit, comprising: a dummy access execution unit for performing a dummy access in order to observe a timing regulation specific to a device when the bus access is interrupted by the bus access interruption unit. 3. The bus control circuit according to claim 1, wherein
A bus control circuit, comprising: status determination means for determining whether a currently executed bus access is in a state in which it can be interrupted.