JPH022449A - Information processor - Google Patents

Abstract

PURPOSE:To reduce the cost of hardware by allowing a processor to trap memory access to a specific area in a common memory and transmit the trapped specific area to a bus control part and allowing the bus control part to apply the using right of a common bus or release it. CONSTITUTION:It is supposed that a processor P1 executes an IN1 instruction to be a test and set request instruction faster than other processor Pn. The IN1 instruction of the processor P1 sends a bus using request signal to a bus control part 40, receives a bus use allowing signal from the bus control part 40 and sends the IN1 instruction to a common bus 50 and a common memory Rm receives the IN1 instruction and executes prescribed processing. On the other hand, a trap device 30 traps the IN1 instruction flowing on the common bus, identifies and interprets the specific area in the common memory for plural processors and sends a bus holding signal to the bus control part 40 through a bus holding line 60.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device in a computer complex system using a common bus coupling method.

[Conventional technology]

In recent years, research has been conducted in various places to develop computer systems with excellent cost performance by combining multiple computers.
The results are highly anticipated. In a computer complex system, in addition to the problems of the connection form between computers and the scheduling of tasks, the problem of how to effectively use memory, input/output devices, files, etc. is also an important point. The advantage of a computer complex system using a common bus is that the cost of attached hardware is comparatively low.
In addition, the system is highly expandable, especially the shared memory method in multiprocessor systems.
It is extremely effective in solving synchronization problems between processors, exclusion problems, and improving the processing power and reliability of the entire data sharing system.

A problem here arises when multiple processors use one shared memory at the same time, that is, when one processor's task competes with another processor's task to access one shared memory. In this case, some tasks have a character that must be executed continuously, and a test-and-set function is required to prevent resources from being taken over by other tasks while the task is being executed.

[Problem to be solved by the invention]

Conventional methods of this type generally involve preparing a common table for a plurality of processors on a common bus and managing resources using software for each processor or an operating system that manages the entire system. In other words, when a processor monopolizes shared memory for a period of time (test-and-set operation), the operating system uses the resources in response to processor input/output instructions. A flag unique to the processor is set at the address of the corresponding table, and when the processor finishes the test and set operation, the flag unique to the processor that is the table master is set down, and while the flag is set, the resource is not transferred to other processors. This is a method of prohibiting the use of .

This method has the drawback that it places a burden on the software or operating system of each processor and reduces the throughput of the entire system.
This has the extremely unreasonable disadvantage that a control section is required to control the system, which increases hardware costs.

[Means to solve the problem]

The present invention was developed in view of the various drawbacks mentioned above, and takes full advantage of the effectiveness of computer complex systems based on the common bus coupling method, and provides relatively simple hardware that allows conventional software to be used as is and does not place any burden on the operating system. The purpose is to provide an information processing device that can be realized using the following methods.

〔Example〕

The details of the test and set apparatus of the present invention will be explained below with reference to the drawings.

FIG. 1 shows the configuration of this test and set device.

Multiple processors (pt~pa) and shared memory (Rm
) and the trap device 30 are each connected in parallel to a common bus 50 to which a bus control section 40 is added. Furthermore, the trap device 30 and the bus control unit 4.0 are connected by a bus holding line 60, and the timing of using the processor's resources is performed asynchronously, so that the processor and the bus control unit 4.0 are connected to each other by a bus holding line 60. It transfers the use request signal to the bus control section 40, receives a spring use permission signal from the bus control section 40, and outputs various signals to the common bus 50 at the input/output timing of each processor.

In this manner, the bus control unit 40 grants the processor the right to use the common bus 50 for each command output by each processor, and at the same time continues to use the common bus 50 by a bus hold signal from the trap device 30, which will be described later. It has a function to make it perform.

FIG. 2 shows the configuration of the trap device 30.

The trap device 30 traps input/output commands to a specific area in the shared memory flowing on the common bus 50, writes the memory circuit 32 in the trap device 30, and sends them to the bus control unit 40 via the bus holding line 60. It sends a bus hold signal. Also, a trap device! 30 traps input/output commands outside a specific area in the shared memory flowing on the common bus 50, resets the memory circuit '32, and stops the hold signal sent to the bus controller 40. Trap-M2O in which the instruction interpretation circuit 31 is connected to the common bus 50
An instruction to access a specific address area of the shared memory flowing above, a so-called test and set request instruction,
This is a decoder that detects an instruction to access a specific address/outside area of the shared memory, a so-called test and set release instruction.

The memory circuit 32 is constituted by an R-S flip-flop circuit, etc., and is set by a test and set request command decoded by the command interpretation circuit 31 and reset by a test and set cancellation command also decoded by the command interpretation circuit 31.

Next, the operation of the information processing apparatus according to the present invention will be explained with reference to FIGS. 1 and 2.

To simplify the explanation, two processors P 1 rP2
An example will be explained in which the shared memory Rm is used in conflict with each other. Input commands and output commands to a specific area of the shared memory of the processor P1 are INI and 0UTI, respectively, and input commands to outside the specific area of the shared memory of the processor P2,
Let the output commands be IN2 and 0UT2, respectively. In other words,
IN2.0UTI is a test and set request command, and IN2,0UT2 is a test and set release command. Therefore, the instruction interpretation circuit 31 in the trap device 30
Then, it is necessary to ensure that each IN command and OUT command is decoded into a predetermined command.

Suppose that processor P executes an INI instruction earlier than processor P2. The INI command of the processor P□ sends a bus use request signal to the bus control unit 40, receives a bus use permission signal from the bus control unit 40, and sends the INI command to the common bus 50, and the shared memory Rm receives the INI command. Execute predetermined processing. On the other hand, the trap device 30 may trap the INI instruction flowing on the common bus 50, and may be provided with a function of identifying and interpreting a specific area on the shared memory of a plurality of processors.

In this way, by simply setting a specific area in the processor's shared memory in advance, certain processing can be performed continuously without resources being taken over by other processors. Particularly in computer complex systems, care must be taken to protect resources, but this method can be realized with relatively simple hardware by using the test-and-set method.

Furthermore, if there are many instructions registered as test-and-set instructions in the instruction interpretation circuit 31 in the trap device 30, it is conceivable to add a memory or a dedicated processor to perform the series of processes. Furthermore, a means for prohibiting all processors from using the common bus 50 when erroneous data or instructions flow on the common bus 50 can be easily added.

〔Effect of the invention〕

The present test and set device described above is an information processing device that takes full advantage of the effectiveness of the common bus connection method, and is extremely effective in practical use.

31... Command interpretation circuit, 32... Memory circuit.

Claims (1)

[Claims] A plurality of processors and a shared memory that can be accessed by the processors are each connected in parallel to a common bus, and the address of the shared memory of the processor is transmitted to the common bus for each memory access to space. In the information processing device, a memory access to a specific area of the common memory during memory access by the processor on the common bus is trapped and transmitted to the bus control unit. , giving the right to use the common bus to the processor, and subsequently giving the right to use the common bus to successive accesses of the processor to a specific area of the shared memory, and specifying the shared memory of the processor; An information processing device characterized in that an access to an area outside the area is trapped, and the bus control unit releases the right to use the common bus continuously to the processor.