JPS6232561A - Control system for multiprocessor system - Google Patents

Abstract

PURPOSE:To improve the processing capability of the entire system by disposing a message-communication area on the two-port memory of respective processors. CONSTITUTION:In the communication areas C12-C32 of CPUs 1-3 a flag 101 indicates that a message from a message-issuing processor of the CPUs 1-3 is being processed or that the message is already processed, and a message area 102 stores an notification information from the issuing processor. Accordingly, an access to the memory from inside the processor is made possible, and the compitition for the common bus signal line is decreased, and an inter- processor message exchange is made possible.

Description

[Detailed Description of the Invention] [Industrial Field of Application] This invention relates to a control method for a multiprocessor system in which information is exchanged between multiprocessors. [Prior Art] FIG. This is a block diagram equivalent to that showing the conventional control method shown in Publication No. 55-39908, and in the figure, 1 to 3 are +1 to ÷3 CPUs, 4 is a common bus signal line, 5 is a shared memory, C12, C13, C2
Reference numerals 1, C23, C31 and C32 indicate communication areas within the shared memory 5 for exchanging information between the respective processors of the CPUs 1 to 3. 6 is a single interrupt request signal that interconnects each processor.

Next, the operation will be explained with reference to FIG. First, it is assumed that a factor has occurred that should be notified from the +1 CPUUI to the +2 CPU2. ◆The CPU 1 writes notification information to the communication area C21 of the shared memory 5, and sets a toggle flag in this area, that is, a flag indicating that the message in the communication area C21 is unprocessed. Thereafter, an interrupt request signal is output to the interrupt request line 6 in order to issue an interrupt request. Here, the +2 CPU 2 performs the following operations as interrupt processing in response to this interrupt input. First, communication area C21
, and determines whether information has been notified from the CPU of Na1. Here, in this conventional example, +1 CPU
Since there is information from , this information is taken in and processing is performed according to the content. In this case, since interrupt input is also made to the other CPUs 3 to 3, each processor checks the communication area addressed to itself and determines whether there is a message from the processors 3 to 3. For example, +3 CP
U3 checks the contents of the communication areas C31 and C32, and performs invalidation processing if, for example, there is no message addressed to itself.

[Problem that the invention seeks to solve]

Since the conventional multiprocessor system control method is configured as described above, each CPU must check the area of the shared memory 5 each time, and furthermore, it is necessary to interrupt each time even if the message notification is not addressed to itself. It is necessary to access an area of shared memory for each occurrence. Therefore, there are problems in that overhead due to contention on the shared bus signal line 4 increases and unnecessary invalidation processing is executed.

This invention was made to solve the above-mentioned problems, and it reduces the load on the shared bus signal line, and
The purpose of this invention is to obtain a control method for a multiprocessor system that can eliminate unnecessary invalid processing.

[Means for solving problems]

The control method for the multiprocessor system according to the present invention controls the inter-processor message communication area between two of each processor.
Each processor is provided with an interrupt request circuit located in the port memory area and for generating an interrupt only to the other processor when a message is notified.

[Effect]

The message communication area in the present invention is arranged in a two-port memory area, thereby allowing memory access from within the processor, reducing contention on the shared bus signal line, and enabling message exchange between processors.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, -1 to 3 are CPUs divided by 1 to ◆3, 4 is a shared bus signal line, and 7 to 9 are interrupt request circuits provided in each CPU I to 3. Figure 2 shows the communication area C of each CPUI~3.
12 to C32. A 7 lag 101 indicates whether a message from CPUI to 3, which is a message issuing processor, is being processed or has been processed, and a message area 102 indicates a notification from an issuing processor. Information is stored. FIG. 4 is a detailed configuration diagram showing an example of the interrupt request circuits 7 to 9. In FIG. 1, 201 is a setting switch, 202 is an address matching circuit, and 203 is an AND
It is a circuit.

Next, the operation of the above-mentioned embodiment will be explained with reference to the drawings. In FIG. 1, it is assumed that a state is reached in which information should be notified from the CPU 1 of Na1 to the CPU 2 of +2. At this time, the CPU of S1 is the sum of +2 CPU as shown in the flowchart of Figure 3.
Flag 101 of the communication area C21 on the 2-port memory of No.2
If the 7lag 101 is not set, set the flag 101 (step 302), the message area 10 of the communication area C21.
2 (step 303), then ÷2 C
An interrupt request is made to PU2 (step 304). This interrupt request is output by interrupt request circuits 7 to 9 shown in the block diagram of FIG. The +2 CPU2 is specified by the interrupt instruction (execution of the OUT instruction) executed by the +1 CPU.

In FIG. 4, since a value equal to the specified value is set in the setting switch 201, only the CPU 2 of -◆2 decodes the interrupt instruction and generates an interrupt. The setting switch 201 is set to a different unique value for the other CPUs 1.3.

Therefore, no interrupt occurs to CPUI,3.

When the interrupt occurs, the CPU 2 executes the interrupt process shown in the flowchart of FIG. First, the flag 101 in the communication area C21 is checked (step 401), and if it is set, the message in the communication area C21 is fetched to indicate that there has been a notification from the CPU 1 in step 1 (step 402), and based on the message content. Then, processing is performed (step 403). Thereafter, the flag 101 in the communication area C21 is reset (step 404), thereby making it possible to receive a message from the +1 CPU1 again from 9 onwards. Incidentally, the flag of the communication area C23 is subsequently checked (step 405), and if there is a message from the CPU 3 of the CPU 3, the same processing is performed (steps 406 to 408).

Note that although the above embodiment shows the case where three CPUs are provided, more processors are connected to the shared bus signal line 4.
Alternatively, each partner processor may have its own message communication area.

〔Effect of the invention〕

As described above, according to the present invention, since the message communication area is arranged on the two-port memory of each processor, contention on the shared bus can be prevented, and interrupt requests between processors can be transmitted using the shared bus signal. It can be realized by the interrupt request circuit in the processor without having to have it as an interrupt request circuit, and it is possible to notify interrupts individually, eliminating the need to execute unexpected interrupt processing, and improving the processing capacity of the entire system. be.

[Brief explanation of the drawing]

FIG. 1 is a block diagram according to an embodiment of the present invention, FIG. 2 is a state diagram showing a message format in this invention, and FIG.
4 is a detailed configuration diagram for explaining details of the interrupt request circuits 5 to 9 in FIG. 1, and FIG. 5 is an embodiment of the invention. A flowchart for explaining an example, and FIG. 6 is a block diagram of a conventional control method. 1 to 3 are CPUs (processors), 7 to 9 are interrupt request circuit units, C12, C13, C21, C23° C31, C32
is a communication area (message exchange area). In each figure, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] In a control method for a multiprocessor system having a plurality of processors connected to a common bus signal line, a message exchange area between the processors is arranged in a 2-port memory area of each processor, and an interrupt is generated in each processor. The two-port memory on each processor is used as a communication area to exchange information between the respective processors, and after writing the transmission information in this communication area in advance, the interrupt request circuit generates an interrupt request circuit. A control method for a multiprocessor system characterized in that an interrupt request is generated from a circuit to a partner processor.