JPS62266639A - Interface device for input/output device - Google Patents

Abstract

PURPOSE:To improve the throughput of an entire system by giving a local memory to an I/O device in terms of an interface between the I/O device and a CPU. CONSTITUTION:The I/O device 3 is provided with the local memory 4. When the I/O device 3 accesses the local memory 4, said memory is isolated from a system bus 5, and data is transmitted only between the I/O device 3 and the local memory 4, Without stopping the CPU1, an I/O access is attainable. Accordingly the system has two types of busses, the system bus 5 for the CPU1 and I/O buses 61-63 for the I/O device 3. Only when the CPU1 accesses the local memory 4, for instance, the system bus 5 is connected to the I/O buses 62 and 63. Thus the CPU1 can do other data processing while the I/O device 3 accesses the local memory 4.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an interface device between an information processing unit (hereinafter referred to as a CPU) and an input/output device (hereinafter referred to as an IO device) constituting a system. .

[Conventional technology]

Conventionally, in systems using a CPU such as a microprocessor, the interface between the CPU and IO devices is directly connected to the system bus, which is the CPU bus, and supports polling, interrupts, and direct memory access (hereinafter referred to as D).
It is interfaced using techniques such as MA.

[Problem that the invention seeks to solve]

In the conventional interface method described above, when the number of communications between the system and the outside increases and the frequency of input/output (hereinafter referred to as IO) access increases, the usage efficiency of the system bus, which is the CPU path, decreases and the system processing The drawback is that the throughput, which indicates the amount of data available, decreases.

For example, in a system using DMA, when accessing IO, the CPU is stopped and the system bus is released, and the processing device directly transmits data to and from memory via this system bus. ■When the 0 device is accessing memory, the CPU is stopped, so the CPU throughput decreases. In particular, as the frequency with which IOO devices access memory increases, the execution time of the CPU becomes shorter (and the throughput decreases).

Since the throughput decreases in KDMA processing as well, interrupts and polling result in a situation where the CPU hardly executes the main program, and in the worst case, the processing slows down and becomes impossible.

The industrial interface device of the present invention solves the above-mentioned problems, and by providing an IOO device with its own local memory, it relieves the bottleneck of the CPU system bus and improves system throughput. The purpose is to

[Means for solving problems]

In a system having an information processing unit and a system bus connected to the information processing unit, the interface device of the present invention includes: a first input/output path connecting an input/output device to a local memory; A second input/output path that connects the local memory to the system bus, and a bus switching unit that selects between the second input/output path and the first input/output path. do.

Therefore, the input/output device can be operated without stopping the operation of the information processing unit.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, in which an information processing unit (hereinafter referred to as CPU) 1 and a main memory 2 constituting the system are connected to a system bus 5. As shown in FIG.

Input/output devices that are interfaced externally (hereinafter referred to as
IOO device) 3 is an input/output path (hereinafter referred to as an IOO device).
bus switching unit 7. The bus switching unit 7 is connected to the system bus 5 via the bus 63. Reference numeral 4 denotes a local memory for the work 0 device 3, and the memory 4 is connected to the bus switching unit 7 via an IO path 62.

Note that the IO data device 3 is directly controlled as shown in the figure.
The system bus 5 can be accessed using the control signal csl, or, although not shown, the system bus 5 and the 10 bus 61, 63 can be connected and accessed.

In addition, in FIG. 1, the address control unit 8 constituting the IO device 3 is connected to the local memory 4 of the IO device 3.
It is provided when you do not have an interface to access the address, and it is used to automatically generate an address.

The operation of the above embodiment will now be explained. For example, first
According to the control signal CrL2Vc from the system bus 5, the local memory 4 is connected to the system bus 5 side by connecting the work paths 62 and 63, and an input/output message is written.

Next, for example, the control signal CrL2 controls the process 0 path 6.
When 1 and 62 are connected, a coprecipitation and IO device 3 control signal CrL1 is output, and data is transferred between the local memory 4 and the IO device 3 by DMA. After this process is finished, the IO device 3 notifies the CPU 1 of the completion using the control signal cn1 and the system bus 5.
After this, the CPU 0 bus 62.6:3 is connected and the CPU 1
processes the data in the local memory 4. When performing the above operation, when there is a conflict in the use of local memory 4,
Since it would be extremely wasteful to put one of the paths in a waiting state, the IO paths 61 to 63 are switched in a time-sharing manner only when there is contention. This allows the wait state to be minimized.

The above can be explained using (a), (b), (
Figure (a) shows when the IO device 3 local memory 4 is accessed, and Figure (b) shows when the CPU 1 accesses the local memory 4.
When accessing the local memory 4, Figure (C) shows the access timing in case of access conflict.

Furthermore, although the local memory 4 is normally directly connected to the IO device 3, it is connected to the system bus 5 only when accessed by the CPU 1.

As described above, the feature of this embodiment is that the IO device 3 has a local memory 4, and when the IO device 3 accesses the local memory 4, it is disconnected from the system bus 5 and the IO device 3 is connected to the local memory 4. Data transmission is performed only between the local device 3 and the local memory 4 to enable KIO access without stopping the CPU 1. Therefore, in the system there is a system bus 5 for CPU 1.
There is a class 21i of 0 paths 61 to 63 for device 3 for 0, and for example, when CPU 1 accesses local memory 4 -j-rutoki f! -n, system bus 5 and IO bus 62 and 63 are connected. As a result, when the work device 3 accesses the local memory 4, the CPU 1 can perform other data processing.

In addition, according to the control signal cn4 from the IO device 3,
CPU 1 moves to data processing from device 0,
In this case, the system bus 5 and the bus 62, 63 are connected to access the local memory 4 and process data.

〔Effect of the invention〕

“As explained above, the present invention provides a device for
By providing the IO device with local memory in the interface with the U, input/output processing of the IO device can be performed without stopping the CPU, and the throughput of the entire system can be increased. (The CPU only controls the IO device, and the actual input/output processing of the 0 device is performed completely separately from the CPU. This has the effect of maximizing the processing power of the CPU.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is an explanatory diagram showing the operation of the same. 1...CPU (information processing unit), 2
・・・・・・・・・ Main menu, 3...
・・・・・・Device for engineering 0 (input/output device 2.
4...Local memory, 5
...System bus, 61~ta...
IO path, 7...Path switching section.

Claims (1)

[Claims] A system having an information processing unit and a system bus connected to the information processing unit, comprising: a first input/output bus connecting an input/output device to a local memory; and a first input/output bus connecting the local memory to the local memory. An input/output device comprising: a second input/output bus connected to the system bus; and a bus switching section that selects between the second input/output bus and the first input/output bus. Device interface equipment.