JP2000298652A - Multiprocessor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute plural processes more efficiently than a single processor and to make the area of a multiprocessor smaller. SOLUTION: This multiprocessor is provided with plural processors 3 and 4, an instruction memory 1 and a data memory 2 which are shared by the plural processors 3 and 4 and an computing unit 6 shared by the processors 3 and 4. It is further provided with an arbitration circuit 5 which arbitrates the memories 1 and 2 and the unit 6 so as to be accessed by only one processor at a simultaneous time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor equipped with a plurality of processors. In particular, in a one-chip multiprocessor in which a plurality of processors are mounted on a single LSI, a multiprocessor capable of efficiently executing a plurality of processes while suppressing an LSI area by sharing a circuit among the plurality of processors. It is about.

[0002]

2. Description of the Related Art A typical means for executing a plurality of processes on a single processor including a single processor is based on an OS (basic software).
There are those that execute various applications on the above. The OS executes each application in units of processing of a certain program (hereinafter, referred to as processes). Since only one process can be executed on one processor at a time, it is as if multiple processes are being executed at the same time by finely switching the processes to be executed every certain time.

FIG. 9 shows a state of processing running on a processor when two processes are executed in a time-division manner. 4001 and 4002 denote two different processes A and 400, respectively. B, 4
Reference numeral 003 indicates processing necessary for switching between two processes (hereinafter, referred to as “process switch”). A general method for switching processes in a time-division manner is to use an interrupt from a timer. For example, count the number of interrupts from the timer, and when it reaches a predetermined count value,
Perform a process switch. In the process switch, from a processor's point of view, necessary information in a process (a program counter (PC) value, a stack pointer address, a general-purpose register, and a program state word (PSW)) related to a process executed before switching is performed. Save to memory, data (PC value, stack pointer, general-purpose register,
Restoration of the information in the PSW from the data memory is performed. Therefore, when the process switch is executed, several tens to several hundreds of instructions are executed in the processor, so that it takes time to switch to the next process, and high-speed processing cannot be performed.

[0004] As one of the techniques for solving this problem and executing various processes at high speed, there is a multiprocessor system. In this technique, required processing is distributed to a plurality of processors and processed in parallel to increase the processing speed. Recent LSI integration technology has made it possible to mount this multiprocessor system on a single LSI, and to realize a multiprocessor system at low cost. However, while the multiprocessor can achieve high-speed processing, there is a problem that a plurality of processors each have hardware resources such as an instruction memory, which is disadvantageous in area. As means for solving this problem, for example, there is a one-chip microcomputer disclosed in Japanese Patent Application Laid-Open No. 62-24356. In Japanese Patent Application Laid-Open No. Sho 62-24356, in particular, ROM and RAM are shared to make the area more advantageous, and the ROM, RAM
Discloses a multiprocessor system capable of executing a program efficiently by shifting the timing of accessing.

[0005]

As described above, when a plurality of processes are executed by a conventional single processor,
Process switch occurs. For this reason, the user consumes time for processing that is not actually needed, and there is a problem that high-speed processing cannot be realized. In a multiprocessor, the above problem can be solved by dividing the processes executed by each processor. However, since each processor has independent hardware resources, the area is disadvantageous. There was a point. In this regard, ROM, R
We used a means to share memory such as AM,
In response to recent demands for processor area savings, sharing this memory alone is not sufficient, and there has been a demand for a multiprocessor technology that achieves further area savings. SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to realize a processor which can be efficiently executed even when a plurality of processes are executed and which saves area. And

[0006]

A multiprocessor according to the present invention includes a plurality of processors and a memory shared by the plurality of processors, and further includes a computing unit shared by the plurality of processors. The arithmetic unit is provided with means for arbitrating so that only one processor accesses the arithmetic unit at the same time. Specifically, it has the following features.

[0007] An instruction memory for storing instruction codes, a data memory for storing data to be operated on and operation results, a plurality of processors not including an operation unit, and an operation unit for performing operations in accordance with control data from the processors. The instruction memory, the data memory, and the arithmetic unit are shared by a plurality of the processors, and have means for accessing each of them at the same time by at most one processor only. I do.

[0008] The present invention is characterized in that it has means for switching an instruction memory, a data memory, and a processor that can use an arithmetic unit at regular intervals.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 1 and 2 are block diagrams of a one-chip multiprocessor showing an embodiment of the present invention. For simplicity of description, a case where there are two processors will be described here as an example. In the figure,
1 is an instruction memory for storing an instruction code, 2 is a data memory for storing data to be operated and execution results of an instruction, and 3
Is a processor # 0 that executes an instruction according to an instruction code, and does not include an arithmetic unit inside. 4 is processor #
1, which does not include an arithmetic unit inside similarly to the processor # 0 (3). 5 is an arbitration circuit, which stores instruction memory 1,
It is determined which processor uses the data memory 2 and the arithmetic unit 6. That is, the arbitration circuit 5 arbitrates not only for the shared memory (the instruction memory and the data memory) but also for the use of the arithmetic unit 6. Reference numeral 6 denotes an arithmetic unit, which includes an adder, a multiplier, and the like required when executing an arithmetic instruction. The arithmetic unit is shared by the processors # 0 (3) and # 1 (4). Reference numerals 301 and 401 denote memory access units which are used to read (fetch) an instruction code from the instruction memory 1 or to transfer data between a register and a memory in a load / store instruction. Access to Instruction decoders 302 and 402 decode the read (fetched) instruction code and transmit an appropriate control signal to the instruction execution units 303 and 403 and the arbitration circuit 5. Reference numerals 303 and 403 denote instruction execution units that send control signals and necessary data to the arithmetic unit 6 in accordance with control signals sent from the instruction decoder unit 302 and the arbitration circuit.
The calculation result executed by the calculator 6 is latched and written to the general-purpose registers 320 and 420. Also, 310, 41
Reference numeral 0 denotes a control register, which is an instruction memory 1 of an instruction code to be read (fetched) next to the currently executing program.
It is composed of a program counter that holds the above address, a program status word that holds information such as the state of the processor, and the like. 320 and 420 are general-purpose registers, each of which is a register that temporarily holds operation result data, operation target data, and the like. FIG. 1 shows a configuration in which the instruction memory 1, the data memory 2, and the arithmetic unit 6 are connected to the processors # 0 (3) and # 1 (4) via a common bus. In FIG.
The arithmetic unit 6 is connected to each processor via a bus different from the instruction memory 1 and the data memory 2. 1 has a merit that the number of buses can be reduced because the buses are shared. On the other hand, in FIG. 1, there is a demerit that data transmission and reception are crowded because the bus is common, and the configuration of FIG. 2 is different from the bus used for the arithmetic unit 6 and the shared memory (instruction memory and data memory). Therefore, there is an advantage that data transmission and reception can be performed smoothly.
These configurations can be selected according to the purpose of use and the use conditions of the processor.

FIG. 3 shows a configuration of a pipeline of operation instructions in the processors # 0 (3) and # 1 (4), which is composed of four stages of pipelines. In FIG. 3, reference numeral 20 denotes a period during which an instruction is read (fetched) (hereinafter, referred to as an “IF stage”).
Reference numeral 1 denotes a period during which the instruction is decoded (hereinafter, referred to as “D stage”), reference numeral 22 denotes a period during which the decoded instruction is executed (hereinafter, referred to as “E stage”), and reference numeral 23 denotes a result of the operation written in the register. This is the period of return (hereinafter, referred to as “W stage”). Next, the operation will be described. Since the basic operations of the processor # 0 (3) and the processor # 1 (4) are the same, the processor # 0 (3) will be described unless otherwise specified. IF stage 20
Then, the instruction code at the address indicated by the PC counter is read from the instruction memory 1 via the memory access unit 301. Next, in the D stage 21, the read instruction code is decoded by the instruction decoder unit 302, and the decoded result is sent to the instruction execution unit 303. At this time, if the instruction code to be executed is an arithmetic instruction, a request signal for accessing the arithmetic unit 6 in the next stage is sent to the arbitration circuit 5. Then, in the E stage 22, the arithmetic unit 6 receives the data to be operated and the operation based on the control signal output from the instruction decoder unit 302 and an acknowledge signal indicating that the access from the arbitration circuit 5 is permitted. A control code indicating the type is transmitted.
The arithmetic unit 6 performs an operation in accordance with the received data and control code, and then sends the operation result to the instruction execution unit 303. Finally, in the W stage 23, the instruction execution unit 303
Writes the calculation result received from the calculator 6 into the general-purpose register 320. In the arbitration circuit 5, the processor # 0
(3) Arbitration when the processor # 1 (4) uses the resources of the instruction memory 1, the data memory 2, and the arithmetic unit 6 is performed. The processor using the resource sends a request signal corresponding to each resource to be used to the arbitration circuit 5, and upon receiving the request signal, the arbitration circuit 5 uses the acknowledgment signal indicating permission of use. Is sent to the processor that permits it. The arbitration circuit 5 sends an acknowledgment signal to the processor that has issued the request signal first for each resource. It sends a NORID signal and sends a signal to the other processor to deny access. The priority may be fixed, for example, or the priority may be changed between the processors in order.

FIG. 4 shows the state of the pipeline when the processor # 0 (3) and the processor # 1 (4) execute a series of different operation instructions. 3
0, 32, and 34 are a series of operation instructions executed in this order in the processor # 0 (3).
Reference numerals 3 and 35 are a series of operation instructions executed in this order in the processor # 1 (4). Processor # 0
(3) Since the processor # 1 (4) outputs a request signal of the instruction memory 1 to the arbitration circuit 5 at the same time, and the arbitration circuit 5 returns an acknowledge signal to the processor # 0 (3). The IF stage of the operation instruction 31 executed on the processor # 1 (4) side is the processor # 0
It waits until the IF stage of the (3) side operation instruction 30 is completed, and continues for two clock cycles. Similarly,
The operation instruction 32 executed by the processor # 0 (3) also lasts for two clock cycles because it waits until the IF stage of the operation instruction 31 executed by the processor # 1 (4) is completed. , 34, and 35. Next, in the E stage of the operation instruction 32, the processor # 0 (3) receives the acknowledge signal from the arbitrator 5 and uses the operation unit 6, but the operation process requires two clock cycles. For this reason, the E stage of the operation instruction 32 and the E stage of the operation instruction 33 overlap. In this case, the processor # 1 (4) sends a request signal for accessing the arithmetic unit 6 to the arbitration circuit 5, but the arithmetic unit 6 has already sent the processor # 1.
Processor # 1 (4) because it is used by (0)
Is rejected and waits until the E stage of the operation instruction 32 is completed. Therefore, processor # 1
The E stage of the operation instruction 33 of (4) lasts for two clock cycles, and thereafter, the operation instructions 34 and 35 also continue for two clock cycles.

FIG. 5 shows a state in which two processes are executed in the one-chip multiprocessor according to the present embodiment. 41 is processor # 0
In (3), reference numeral 42 denotes a process being executed by each of the processors # 1 (4). Reference numeral 40 denotes a state when the same processing is executed by time-division control in a single processor, and is shown for comparison with 41 and 42. In the one-chip multiprocessor according to the present embodiment, when contention for resources used by a plurality of processors occurs, the corresponding pipeline stage is extended, so that the process A (4001) and the process B
Although the processing time is long with (4002) alone, it is possible to execute the processing in parallel by two processors when there is no competition or when the instruction memory, the data memory, and the operation unit are not used. Therefore, since the process switch 4003 does not occur, the overall processing time is greatly reduced. Also,
Since the arbitration circuit of the present invention can perform arbitration not only for the memory but also for the arithmetic unit 6, the arithmetic unit 6 can be shared by the processors. As a result, the area can be significantly reduced as compared with the case where each processor has an arithmetic unit therein. In particular, when a large number of processors are arranged, this greatly contributes to space saving.

As described above, when a plurality of processes are executed, a process can be efficiently executed without causing a process switch, and a memory and an arithmetic unit are configured to be shared by a plurality of processors. Thus, a space-saving one-chip multiprocessor can be realized.

Embodiment 2 FIG. In the first embodiment,
When each processor uses resources (instruction memory 1, data memory 2, and arithmetic unit 6) shared by a plurality of processors, it issues a request to the arbitration circuit, and the processor permitted to use by the arbitration circuit In this embodiment, a target resource is used, and a processor which can use the resource at a predetermined time interval is switched next. In this embodiment, the arbitration circuit 5 has a timer counter, and switches the processor that is permitted to use the resource at certain time intervals. That is, not only the instruction memory 1 and the data memory 2 but also the arithmetic unit 6 switches the processor to be used every time. FIG.
Is a block diagram for explaining the operation of transmitting and receiving signals between the processor and the arbitration circuit in this embodiment,
7 and 8 are processors # 0 from the arbitration circuit 5, respectively.
(3) Control signals output to the processor # 1 (4), and 9 and 10 are control signals output to the arbitration circuit 5 from the processors # 0 (3) and # 1 (4), respectively. . The control signals 7 and 8 are signals indicating whether or not each processor is permitted to use the current resource. The control signals 9 and 10 indicate that each processor is currently using the resource. It is a signal indicating whether or not it is running.

Next, the operation will be described. When the timer counter reaches a certain value, the timer counter is reset and starts counting again.
Asserts the control signal 7 to the processor # 0 (3). When the control signal 7 is asserted, the processor # 0 (3) asserts the control signal 9 to the arbitration circuit 5. At this time, the control signals 8, 10 remain negated. Further, when the timer counter again reaches a certain value, the timer counter is reset again, and the arbitration circuit 5 sends the control signal 7 to the processor # 0 (3).
To negate. Processor # 0 (3) outputs control signal 7
Is negated, the instruction currently being processed is temporarily stopped, the use of the resource is stopped, and the control signal 9 is negated. When the control signal 9 is negated, the arbitration circuit 5 asserts the control signal 8 and the processor # 1 (4)
Allows to use resources. When the control signal 8 is asserted, the processor # 1 (4) asserts the control signal 10 and executes processing until the control signal 8 is negated again. Hereinafter, in a similar manner, the processor # 0 and the processor # 1 alternately perform the processing at certain time intervals. FIG. 7 shows a pipeline according to the present embodiment. Each stage of IF, D, E, W and each operation instruction of 30, 31, 32, 33, 34, 35 are the same as those in the first embodiment. Is the same as The processor # 0 (3) and the processor # 1 (4) alternately share resources (instruction memory 1, data memory 2, arithmetic unit 6) at regular intervals.
And while one processor is using the shared resource, the other processor is not using the shared resource. FIG. 8 shows a state where two processes are executed in the one-chip multiprocessor according to the present embodiment. 43 is a processor #
At 0 (3), 44 indicates a process being executed by processor # 1 (4), respectively. Reference numeral 40 denotes a state when the same processing is executed by time-division control in a single processor, and is shown for comparison with 41 and 42. Reference numeral 4004 denotes a period during which one processor is operating and the other is temporarily suspended. In the case of this embodiment, the time required to process the two processes themselves is the same as when the processes are executed by a single processor, but since no process switch occurs, the overall processing time is reduced. I have. As described above, the configuration is such that the operating processor is switched at regular intervals, so that the process can be executed efficiently without the occurrence of a process switch. In addition, since contention for resource use requests from the processors does not occur, the arbitration circuit and the timing control of the processors can be realized by simple circuits. Further, it is possible to reduce the power consumption by stopping the supply of the clock to the suspended processor.

[0016]

As described above, according to the one-chip multiprocessor of the present invention, when a plurality of processes are executed, processing can be executed efficiently without causing a process switch. In addition, since the arithmetic unit is configured to be shared by a plurality of processors, a space-saving one-chip multiprocessor can be realized. Further, not only the memory but also the arithmetic unit is completely switched at regular time intervals by a timer, so that a space-saving one-chip multiprocessor that can execute processing efficiently can be easily realized. Is possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a one-chip multiprocessor of the present invention.

FIG. 2 is a block diagram showing a one-chip multiprocessor of the present invention.

FIG. 3 is a pipeline diagram of operation instructions in the one-chip multiprocessor of the present invention.

FIG. 4 is a pipeline diagram when an operation instruction is simultaneously executed by two processors in the one-chip multiprocessor of the present invention.

FIG. 5 is an operation diagram when two processes are executed in the one-chip multiprocessor according to the first embodiment of the present invention;

FIG. 6 is a configuration diagram of an arbitration circuit and a processor in a one-chip multiprocessor according to a second embodiment of the present invention.

FIG. 7 is a pipeline diagram when two processors simultaneously execute an operation instruction in the one-chip multiprocessor of the present invention.

FIG. 8 is an operation diagram when two processes are executed in the one-chip multiprocessor according to the second embodiment of the present invention;

FIG. 9 is an operation diagram when two processes are executed in a conventional single processor.

[Description of Signs] 1 instruction memory, 2 data memory, 3 processor #
0, 301 memory access unit, 302 instruction decoder unit, 303 instruction execution unit, 4 processor # 1, 401
Memory access unit, 402 instruction decoder unit, 403
Instruction execution unit, 5 arbitration circuit, 6 arithmetic unit, 20 pipeline IF stage, 21 pipeline D stage, 22 pipeline E stage, 23 pipeline W stage, 30-35 operation instruction, 40-4
4 Process processing, 4001 Process A, 4002
Process B, 4003 Process switch, 4004
Operation suspension period.

Claims (7)

[Claims] 1. A plurality of processors, a shared operation unit used by the plurality of processors, and another processor shared by the other processors while one of the plurality of processors uses the shared operation unit. A multiprocessor comprising an arbitration circuit for controlling an arithmetic unit to be unusable. 2. The arbitration circuit sends a signal permitting use of the shared operation unit of the one processor to the one processor, and rejects use of the shared operation unit of the other processor. 2. The multiprocessor according to claim 1, wherein the multi-processor sends the data to the other processor. 3. The multiprocessor according to claim 1, wherein the arbitration circuit switches between the one processor capable of using the shared arithmetic unit and the other processor at regular time intervals. 4. A plurality of processors, a shared operation unit used by the plurality of processors, a shared memory used by the plurality of processors, and one processor of the plurality of processors stores the shared operation unit. While using it, control is performed so that another processor cannot use the shared arithmetic unit, and while one of the plurality of processors is using the shared memory, another processor uses the shared memory. A multiprocessor comprising an arbitration circuit for controlling use of the multiprocessor. 5. The arbitration circuit sends, to the one processor, a signal permitting use of the shared operation unit of the one processor with respect to use of the shared operation unit, and sets the shared processor of the other processor to use the shared operation unit. A signal for refusing use of a computing unit is sent to the other processor, and a signal for allowing use of the shared memory of the one processor is sent to the one processor for use of the shared memory, and 5. The multiprocessor according to claim 4, wherein a signal for rejecting use of the shared memory by one processor is sent to the other processor. 6. The arbitration circuit switches at regular intervals between the one processor and the other processor that can use the shared operation unit for use of the shared operation unit, and the arbitration circuit determines the use of the shared memory. 5. The multiprocessor according to claim 4, wherein control is performed by switching the one processor and the other processor that can use a shared memory at regular intervals. 7. The multiprocessor according to claim 4, wherein said shared operation unit and said plurality of processors are separately connected to a connection between said shared memory and said plurality of processors.