JPS61264467A - Control system for multi-processor system - Google Patents

Abstract

PURPOSE:To avoid the invalid processing of another processor by providing an interruption request circuit at the interruption receiving side and producing an interruption only to the processor at the remote side when the information is exchanged between processors. CONSTITUTION:A CPU #1 unit 1 writes the information to be transmitted to an information exchange area C2 of a shared memory 9 and executes an interruption instruction OUT-02H against a CPU #2 unit 2. The unique value discriminating CPU#1-CPU#3 is set previously to a setting circuit 10. For instance, 02H is set with the unit 2. Therefore the 02H is delivered to an address line 11 and the coincidence signal is delivered only from a coincidence detecting signal 13 of the unit 2. Then an interruption signal INT is produced as the output of an AND circuit 14 which secures an AND with an OUT signal 12 produced by an interruption instruction. While no interruption signal is produced for units 1 and 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control method for a multiprocessor system including a plurality of processor units connected to a common bus line.

[Conventional technology]

FIG. 3 is a block diagram showing the control system of a multiprocessor as disclosed in, for example, Japanese Patent Publication No. 55-39908. In the figure, 1 to 3 are CPU 1 unit to CPU 3 units, 7 is a common bus line, 8 is a single interrupt request line. 9 is a shared memory, CPU◆1 unit 1~CP
It has information exchange areas 01 to C3 between U+3 units 3.

Next, the operation will be explained. For example, when it becomes necessary to transmit an event from CPU 1 unit 1 to processor processor 2 unit 2, CPU 1 unit 1 writes the event information to information exchange area C2 of shared memory 9, and then sends an interrupt request. Output to interrupt request line 8. In response to the occurrence of this interrupt, the CPU units 1 to 3 read the contents of their respective information exchange areas 01 to C3, and
Determine whether or not the interrupt is addressed to you. As a result of this judgment,
CPU 1 unit 1, and C that are not addressed to the interrupt
The CPU 3 unit 3 processes this interrupt as an invalid interrupt, but the CPU φ2 unit 2 determines that the interrupt is addressed to itself and executes processing based on the contents of the information exchange area C2.

[Problem that the invention seeks to solve]

Conventional multiprocessor control systems are configured in two or more ways, so every time each processor unit generates an interrupt for another processor unit, all processors must process the interrupt.65. However, there is a problem in that only one processor unit is performing valid processing, and other processors must execute invalid processing.

This invention was made in order to solve the above-mentioned problems, and in a multiprocessor control method that exchanges information between multiprocessors, it eliminates invalid processing for uninvolved processors and improves the performance of the entire system. It is an object of the present invention to provide a multiprocessor control system that improves the performance of the computer and eliminates the need for interrupt signal lines between processors.

[Means for solving problems]

In the control method of the multiprocessor system according to the present invention, an interrupt request circuit that sends an interrupt signal is provided on the interrupt receiving side of a plurality of processor units, and after an event is transmitted between the plurality of processor units, a common interrupt request circuit is provided. The interrupt command is executed by sending an interrupt signal onto the connected common bus line.

[For production]

The interrupt request circuit in this invention is not provided in the processor on the interrupt generation side, but on the interrupt reception side, so that only the interrupt reception side performs interrupt processing when an interrupt occurs. Additionally, interrupt processing by unrelated processor units will not be executed unexpectedly.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 to 3 are CPUs l to CPUφ3 units, 4 to 6 are interrupt request circuits, 7 is a common path line, 9 is a shared memory, and CPU≠1. The CPU 3 has information exchange areas 01 to C3 between units 1 to 3.

FIG. 2 is a block diagram showing details of the interrupt request circuits 4 to 6 in FIG. 1, and in the figure, 10 is a setting circuit;
11 is an address line, 12 is an OUT signal, 13 is a coincidence detection circuit, and 14 is an AND circuit.

Next, the operation will be described in the case where an event is transmitted from the CPU, )1 unit 1 to the CPU+2 unit 2.

The information to be transmitted by the CPU+1 unit 1 is transferred to the shared memory 9.
2, and executes an interrupt command to the CPU 2 unit 2. A normal input/output instruction (OUT instruction) is used as the interrupt instruction. By executing this instruction, CP
An interrupt signal (IN
T) is given to CF'U of CPU2 unit 2, and C
The interrupt processing of the PU2 unit 2 will be executed.

Next, the operation of the interrupt request circuits 4 to 6 will be explained. In FIG. 2, the setting circuit 10 includes CPU◆1 to CP in advance.
A unique value identifying Uφ3 is set. for example,
HolH, CPU+2 with CF'U+1 unit 1! Near) 2fUO2H.

For CPU+3 unit 3, it is 03H (hexadecimal).

In this case, the interrupt instruction executed by CPU unit 1 is O
It is UT 02H. Therefore, address line 11 has 0
Since 2H is output, a match signal is output only from the match detection circuit 13 of the CPU 42 unit 2, and the interrupt signal (INT) is output from the AND circuit 14 which performs AND with the OUT signal 12 associated with the interrupt command. is generated, and no interrupt signal is generated for CPU 1 unit 1 and CPUφ3 unit 3.

Although the above embodiment shows an example in which three CPUs are connected to a common bus, even if more CPUs are connected and the information communication area on the shared memory is prepared for each other processor. In many cases, the same effects as in the above embodiment can be achieved.

〔Effect of the invention〕

As described above, according to the present invention, in a multiprocessor system, the interrupt request circuit is provided in the interrupt reception side of the plurality of processor units, so that the interrupt request circuit is provided in the interrupt reception side of the plurality of processor units. Only one processor can generate an interrupt, other processors do not have to perform invalid processing, and there is no need to add interrupt signal lines to the common bus line, so it is possible to use a small number of common bus lines and This has the advantage of being able to reduce the size of the device.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a multiprocessor system showing an embodiment of the present invention, Fig. 2- is a block diagram showing details of the interrupt request circuit shown in Fig. 1, and Fig. 3 is a block diagram of a conventional multiprocessor system. It is. In the figure, 1 to 3 are CPU units (processor units), 4 to 6 are interrupt request circuits, 7 is a shared bus line, 9 is a shared memory, 10 is a setting circuit, 13 is a coincidence detection circuit, 14 is an AND circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Patent applicant Mitsubishi Electric Corporation (2 others) Diarrhea 1 Figure CI, C2, C3: Product information exchange area Figure 2 Figure 3 Procedural amendment (voluntary) 1985 Engineering 8/2'As

Claims (2)

[Claims] (1) In a control method for a multiprocessor system that is composed of a plurality of processor units and in which information is exchanged on a common bus line to which the plurality of processor units are coupled, an interrupt request that sends an interrupt signal on the common bus line. When a circuit is provided on the interrupt reception side of the plurality of processor units and an event is transmitted between the plurality of processor units, the information to be transmitted is written in an information exchange area connected to the common bus line, and then 1. A control method for a multiprocessor system, characterized in that an interrupt command is executed by sending an interrupt signal from the interrupt request circuit. (2) The interrupt request circuit includes a setting circuit that sets a value for identifying a plurality of processor units, and is connected to this setting circuit, and is connected to an address input from an address line of a common bus line and a setting circuit that sets a value for identifying a plurality of processor units. A coincidence detection circuit that detects coincidence with a value and outputs a coincidence signal, and an AND (
2. The control method for a multiprocessor system according to claim 1, further comprising an AND circuit that performs an AND) logic and generates an interrupt signal.