JPS58114141A - Fault reporting system for multimicroprocessor - Google Patents
Fault reporting system for multimicroprocessorInfo
- Publication number
- JPS58114141A JPS58114141A JP56210244A JP21024481A JPS58114141A JP S58114141 A JPS58114141 A JP S58114141A JP 56210244 A JP56210244 A JP 56210244A JP 21024481 A JP21024481 A JP 21024481A JP S58114141 A JPS58114141 A JP S58114141A
- Authority
- JP
- Japan
- Prior art keywords
- microprocessor
- fault
- circuit
- microprocessors
- master
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Hardware Redundancy (AREA)
- Multi Processors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はマルチマイクロプロセッサの制御方式に関し、
特に電子計算機電子交換機の制御における障害通知方式
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multi-microprocessor control method,
In particular, it relates to a fault notification system in the control of electronic computer exchanges.
従来この種のマルチマイクロプロセッサにおいては、個
々のマイクロプロセッサが障害になった場合、障害にな
ったマイクロプロセッサカ主マイクロプロセッサか従マ
イクロプロセッサかによって、再開の方式が異ってい友
。そのため、障害処理および緊急回路が複雑になる欠点
がありた。Conventionally, in this type of multi-microprocessor, when an individual microprocessor becomes faulty, the restart method differs depending on whether the faulty microprocessor is the main microprocessor or the slave microprocessor. Therefore, there was a drawback that the fault handling and emergency circuits were complicated.
本発明の目的は障害マイクロプロセッサが主マイクロプ
ロセッサか従マイクロプロセッサかを区別せず、マイク
ロプロセッサ群内のどのマイクロプロセッサが障害にな
って４障害処理を簡略化し緊や、回路も容易にできるよ
うにしたマルチマイクロプロセッサにおける障害通知方
式を提供するものである。The purpose of the present invention is to simplify the process of handling four failures and simplify the circuit design, regardless of whether the faulty microprocessor is a main microprocessor or a slave microprocessor. This provides a failure notification method for multi-microprocessors.
不発ｔｓｏマルチマイクロプロセッサにおける障害通知
方式は、複数個のマイクロプロセッサからなるマイクロ
プロセッサ群と、該ｉイクロプロセフサ群の制御および
該マイクロプロセッサ群の１つく主マイクロプロセッサ
権を指定するカウンタを有する共通制御部と、マイクロ
プロセッサ群と共通制御部を接続する信号線とを有し、
マイクロプロセッサ群の１つのマイクロプロセッサの障
害によシ主マイクロプロセッサ権を指定するカウンタを
移行させるとともにマイクロプロセッサ群の全マイクロ
プロセッサに同時割込みを発生させ障害情報を通知する
ことを特徴としている。The failure notification system in a misfired TSO multi-microprocessor includes a microprocessor group consisting of a plurality of microprocessors, and a common control unit having a counter that controls the i-microprocessor group and designates the right of one main microprocessor of the microprocessor group. and a signal line connecting the microprocessor group and the common control unit,
The present invention is characterized in that, in the event of a failure in one microprocessor in a microprocessor group, a counter that designates the master microprocessor right is transferred, and simultaneous interrupts are generated to all microprocessors in the microprocessor group to notify failure information.
久に図面を参照して本発明の実施例について説明する。Embodiments of the present invention will now be described with reference to the drawings.
第１図は本発明の一実施例を示すブロック図である。複
数個のマイクロプロセッサ２０，２１，２２゜２３から
なるプロセッサ群２は共通母線３と個別に接続された障
害監視信号線４０，４１．４２．４３と共通割込信号線
５によ如共通制御部ｌと接続されている。共通制御部１
は上記、複数個のマイクロブロセッサ２０，２１，２２
．２３の障害監視を行なう障害検出回路１０と主マイク
ロプロセッサ指定カウンタ１１と上記複数個のマイクロ
プロセッサ２０゜２１．２２．２３へ割込みを発生させ
る割込み制御回路１２と共通母線インタフェース回路１
３とを有している。マイクロプロセッサ２０を主マイク
ロプロセッサとしマイクロプロセッサ２２が障害になっ
たとすると、障害監視信号線４２を通して障害検出回路
１０にて検出され九障害情報は、共通制御部１の主マイ
クロプロセッサ指定カウンタ１１と割込制御回路１２；
（通知される。主マイクロプロセッサ指定カウンタ１１
は、障害情報によって主マイクロプロセッサ権を移行さ
せマイクロプロセッサ２１を指定し共通母線インタフェ
ース回路１３に表示する。さらに割込み制御回路１２は
共通割込み信号線５を通じて個々のマイクロプロセッサ
２０，２１．２％２３へ割込みを同時に発生させ、マイ
クロプロセッサ２２の障害を通知する。個々のマイクロ
プロセッサ２０．２１．２２．２３は同一の割込みプロ
グラムにより主マイクロプロセッサ権の移行と新系構成
における同一の処理によって処理を再開する。 ゛
次に再開処理の一実施例を説明する。マイクロ７’ ａ
−にッサ２０，２１．２３２３における同レベルの割込
みプログラムは、共通割込み信号線５の情報によって起
動される。該割込みプログラムは、まず新生マイクロプ
ロセッサが自マイクロプロセッサかどうかを確認するた
めに、共通制御部１の共通母線インタフェース回路１３
に表示されている主マイクロプロセッサ指定カウンタ１
１．の内容を共通母線３を経由して読み取る。読み取っ
た内容が自マイクロプロセッサと同じがどうか比較し、
同じであ゛つた場合は、主マイクロプロセッサの個有処
理と各マイクロプロセッサ共通の処理を行ない、同じで
なかりた場合は各マイクロプロセッサ共通の処理だけを
行逐い処理を再開する。FIG. 1 is a block diagram showing one embodiment of the present invention. A processor group 2 consisting of a plurality of microprocessors 20, 21, 22, 23 is commonly controlled by fault monitoring signal lines 40, 41, 42, 43 and a common interrupt signal line 5 which are individually connected to a common bus 3. It is connected to part l. Common control unit 1
is the above, the plurality of microprocessors 20, 21, 22
．． 23, a main microprocessor designation counter 11, an interrupt control circuit 12 that generates interrupts to the plurality of microprocessors 20, 21, 22, and 23, and a common bus interface circuit 1.
3. If the microprocessor 20 is the main microprocessor and the microprocessor 22 becomes faulty, the fault detection circuit 10 detects the fault through the fault monitoring signal line 42 and the fault information is shared with the main microprocessor designated counter 11 of the common control unit 1. control circuit 12;
(Notified. Main microprocessor designated counter 11
transfers the main microprocessor right based on the fault information, designates the microprocessor 21, and displays it on the common bus interface circuit 13. Furthermore, the interrupt control circuit 12 simultaneously generates interrupts to the individual microprocessors 20, 21.2% 23 through the common interrupt signal line 5, and notifies the microprocessors 22 of a failure. The individual microprocessors 20.21.22.23 resume processing by transferring the main microprocessor authority using the same interrupt program and performing the same processing in the new system configuration. Next, an example of restart processing will be described. micro 7' a
- Interrupt programs at the same level in the processors 20, 21, and 2323 are activated by information on the common interrupt signal line 5. The interrupt program first uses the common bus interface circuit 13 of the common control unit 1 to check whether the new microprocessor is the own microprocessor.
Main microprocessor designated counter 1 displayed in
1. The content of is read via the common bus 3. Compare whether the read contents are the same as the own microprocessor,
If they are the same, the processing unique to the main microprocessor and the processing common to each microprocessor are performed; if they are not the same, only the processing common to each microprocessor is performed one by one, and processing is resumed.
本発明は以上説明したように、障害マイクロプロセッサ
が主マイクロプロセッサか、従マイクロプロセッサかを
区別せず、マイクロプロセッサ群内のどのマイクロプロ
セッサが障害になっても主マイクロプロセッサ権を移行
し上記マイクロプロセッサ群の全マイクロプロセッサに
割込みＫよって障害情報を通知することによシ、緊急回
路を容易くでき、障害処理を一つにできる効果がある。As explained above, the present invention does not distinguish whether the faulty microprocessor is the main microprocessor or the slave microprocessor, and transfers the main microprocessor authority to the above-mentioned microprocessor regardless of which microprocessor in the microprocessor group becomes faulty. By notifying all the microprocessors in the processor group of failure information by means of interrupt K, it is possible to simplify the emergency circuit and have the effect of unifying failure handling.
第１図は本発明のマルチマイクロプロセッサにおける障
害通知方式Ｏブロック図である。
１・・・・・・共通制御部、２・・・・・・マイクロプ
ロセッサ群、３・・・・・・共通母線、５・・・・・・
共通割込み信号線、ｌＯ・・・・・・障害検出回路、１
１・・・・・・主マイクロプロや、を指オヵわ２．１２
、：、）割えみ、制御。路、１３・・・・・・共通母
線インタフェース回路、２０，２１゜２２．２３・・・
・・・マイクロプロセッサ０，１，２，３．４Ｑ。FIG. 1 is a block diagram of a failure notification system O in a multi-microprocessor according to the present invention. 1...Common control unit, 2...Microprocessor group, 3...Common bus line, 5...
Common interrupt signal line, lO...fault detection circuit, 1
1..The main micro-pro and the fingers are turned off.2.12
, :, ) Wari , control. Circuit, 13... Common bus interface circuit, 20, 21゜22.23...
...Microprocessor 0, 1, 2, 3.4Q.
Claims (1)
サ群と、諌マイクロプロセッサ群の制御および該マイク
ロプロセッサ群の１つに主マイクロプロセッサ権を指定
するカウンタを有する共通制御部と、マイクロプロセッ
サ群と共通制御部を接続する識号線とを有し、マイクロ
プロセッサ群の１つのマイクロプロセッサの障害によ如
主マイクロプロセッサ権を指定するカウンタを移行させ
るとともにマイクロプロセッサ群の全マイクロプロセッ
サに同時割込みを発生させ障害情報を通知することを特
徴とするマルチマイクロプロセッサにおける障害通知方
式。A microprocessor group consisting of a plurality of microprocessors, a common control unit having a counter that controls the microprocessor group and designates main microprocessor authority to one of the microprocessor groups, and a common control unit that controls the microprocessor group and the common control unit. When one microprocessor in the microprocessor group fails, a counter that specifies the master microprocessor right is transferred, and a simultaneous interrupt is generated to all microprocessors in the microprocessor group to transmit failure information. A failure notification method for multi-microprocessors characterized by notification.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56210244A JPS58114141A (en) | 1981-12-28 | 1981-12-28 | Fault reporting system for multimicroprocessor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56210244A JPS58114141A (en) | 1981-12-28 | 1981-12-28 | Fault reporting system for multimicroprocessor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58114141A true JPS58114141A (en) | 1983-07-07 |
Family
ID=16586166
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56210244A Pending JPS58114141A (en) | 1981-12-28 | 1981-12-28 | Fault reporting system for multimicroprocessor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58114141A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6249467A (en) * | 1985-06-05 | 1987-03-04 | タンデム コンピユ−タ−ズ インコ−ポレ−テツド | Multiprocessor communication |
| JPH038047A (en) * | 1989-06-06 | 1991-01-16 | Nec Corp | Multi-cpu monitoring system |
-
1981
- 1981-12-28 JP JP56210244A patent/JPS58114141A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6249467A (en) * | 1985-06-05 | 1987-03-04 | タンデム コンピユ−タ−ズ インコ−ポレ−テツド | Multiprocessor communication |
| JPH038047A (en) * | 1989-06-06 | 1991-01-16 | Nec Corp | Multi-cpu monitoring system |
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