JPS6112580B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multiprocessor failure handling method for distributing loads or distributing functions in an information processing apparatus.

An example of the prior art that is considered to be closest to the present invention will be explained with reference to FIG. In FIG. 1, n processors (PU1 to PUn) ₁₁ to 1n are organically coupled by a common bus 3, and this common bus 3 further includes a common memory (CM) 5, a data channel (DCH) 6, It represents a typical multiprocessor coupled with a dedicated input/output control unit (P10C) 7. Each processor 11 to 1n is connected to a corresponding individual memory (LM) 2 ₁ to 2n, and LM2 ₁ to 2
It operates according to an individual program stored on the computer. Therefore, in a load-balanced multiprocessor, multiple processors share the same type of processing, and the corresponding LM2 ₁
~2n stores the same kind of programs.

In a functionally distributed multiprocessor, different types of programs corresponding to respective processing functions are stored on each LM2 ₁ to 2n. Therefore, the basic configuration shown in FIG. 1 is generally adopted for both the load distribution type and the function distribution type.

The key points in the configuration of this multiprocessor are which processors share the processing requests from the information processing request source, for example, DCH6 or PIOC7, how to detect a failure in a processor, and how to restore it to normal status. It can be said that the processing can be taken over to a suitable processor.

Regarding the first point, even in the conventional system, a method is adopted in which processing is assigned to each processor by, for example, priority processing or cyclic processing, and in terms of hardware, this function is shared by the common bus control unit (CBC) 4. Ta.

Regarding the second point, in the conventional system, the general idea was to provide each processor with a fault detection and shutdown function.

However, this method requires additional hardware for each processor in order to provide a self-control function to the processor that is causing the problem. It is also possible that interference caused by the failed processor, for example, the common memory access request signal may be stacked in the requested state, thus preventing other processors from using the common bus 3, and thus preventing the multiprocessor from using the common bus 3. There was a risk that the entire SETUSA system would go down.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art and provide an economical and highly reliable multiprocessor.

In a multiprocessor in which processors are connected via a common bus, the present invention detects a failure in each processor at an early stage through a centralized monitoring control bus provided between the individual processors, and removes the failed processor. Electrically separated from the common bus,
Furthermore, by being equipped with a centralized monitoring control section having a function of transferring the load to a normal processor, an economical and highly reliable multiprocessor is constructed.

The entire configuration of one embodiment of the present invention will be explained with reference to the functional block diagram of FIG. FIG. 2 shows the multiprocessor of the present invention, which is equipped with a centralized supervisory control unit (CSC) 8 that detects failures in each processor early and performs failure handling, in contrast to conventional multiprocessors. It is. The CSC 8 is connected to each of the processors 1 ₁ to 1n by a centralized monitoring control bus 9 and a common bus 3. A certain processor 1 ₁ ~
1n or individual memories 2 ₁ to 1n connected to this
2n encounters a fault, the CSC 8 detects the occurrence of the fault via the centralized monitoring control bus 9, and centrally monitors and controls the CSC 8 to issue a fault handling command to the faulty processor depending on the degree of the fault. Departs via bus 9. It also issues an interrupt request to other normal processors through the common bus 3 to transfer the load on the faulty processor.

Next, the specific configuration and operation of the CSC 8 will be explained using FIGS. 3 and 4.

In FIG. 3, n processors 1 ₁ to 1n
Among them, the i-th processor is shown as a representative example on the left, and the CSC is shown on the right. Processor 1 ₁
-1n are generally configured using a built-in program control system, and although the entire configuration is omitted, only the portion having an interface with the CSC 8, which is particularly relevant to the present invention, is shown in the figure.

The fault detection circuit (ED) 10 is a part in which the processor itself performs the function of detecting an abnormal state. (a) Detection of processor clock interruption (b) Detection of program runaway by fault detection timer (c) Parity detection of individual memory Fault detection such as error detection is performed, and the fact that these faults have been detected is reported to the control circuit (CONT) 21 in the CSC 8 via the fault report signal line 11. Control circuit 2
1 analyzes the cause of the processor failure, and in the case of severe failures such as (a) and (b), prevents the failure of the failed processor 1i from affecting other processors via the common bus 3. In order to do so, the processing unit stop signal line 1
In addition to stopping the operation of the faulty processor via line 5, it is directly connected to common bus 3 via processing section disconnection signal line 16, and electrically controls the input and output of signals to processor 1i. Bus transmitter 19 and bus receiver 2
0 to electrically disconnect from the common bus 3.

Next, the control circuit 21 checks various registers that indicate the state of the faulty processor at the time of the fault, such as a program counter (PC) 11 that shows the execution address of the built-in program, and the presence or absence of an external interrupt to the processor. The contents of the interrupt register (ISF) 12 indicating the cause of the failure, the status register (STR) 13 indicating the cause of the failure, etc. are read via the data line 17 in the central monitoring control bus 9, and the contents of these registers are reported to the queue register 22. Accumulate sequentially inside. At this time, the register selection line 18 is used to notify the selection of registers.

When the reading of the above fault information is completed, the control circuit 21 sets a display bit of the corresponding number in the fault processing unit display register 23 to indicate that the corresponding processor has fallen into a fault.

Next, the CSC 8 sends the i-th processor 1i to the normal processor via the common bus 3.
An interrupt request is issued to report that a failure has occurred. In response to this, the contents of the failure processing unit display register 23 and report queue register 22 stored in the CSC 8 are controlled by the control circuit 21 through the common bus control line 26 and sent from the bus transmitters 24 and 25 to the common bus. Among the normal processors, a processor capable of starting an abnormality processing analysis program reads this and executes an abnormality processing analysis.

The above series of operations is shown in the operation diagram of FIG.

As explained above, by introducing the centralized monitoring and control unit CSC into a multiprocessor, it is possible to eliminate the possibility that a failure in one processor will cause the entire multiprocessor system to go down, which was the problem with the conventional system. This has made it possible to dramatically increase the operating rate of multiprocessors.

Furthermore, since the centralized monitoring and control unit can be realized with a small amount of hardware compared to a built-in program type processor, it is possible to achieve dramatic economical savings compared to the case where similar functions are realized using a processor. I can do it.

[Brief explanation of the drawing]

Fig. 1 is a functional block diagram showing a typical configuration example of a conventional multiprocessor, Fig. 2 is a functional block diagram of a multiprocessor showing an embodiment of the present invention, and Fig. 3 is a functional block diagram showing the main points of the present invention. FIG. 4 is a functional diagram showing an example of the configuration of the functions of a certain centralized monitoring control section, and FIG. 4 is an operation diagram showing a part of fault detection and fault processing. 1 ₁ to 1n: Processor, 2 ₁ to 2n: Individual memory, 3: Common bus, 9: Centralized monitoring control bus, 1
0: Failure detection circuit, 11: Program counter,
12: Interrupt register, 13: Status register, 1
9, 24, 25: bus transmitter, 20: bus receiver, 8: central monitoring control section, 21: control circuit, 22: report queue register, 23: failure processing section display register, 26: common bus control line.

Claims (1)

[Claims] 1. In a multiprocessor that organically connects multiple processors through a common bus, and connects input/output control units, common memory, etc. to this common bus, and exhibits processing capabilities exceeding those of the individual processors, the above-mentioned In addition to the common bus, a centralized monitoring control bus is provided, through which faults in individual processors can be detected at an early stage, and in the case of a major fault, the operation of the faulty processor will be stopped, and at the same time the faulty processor will be stopped. Electrically separated from the common bus,
It also reads the contents of the register that indicates the state of the faulty processor at the time of the fault occurrence, stores the faulty processor number, notifies other normal processors of the stored fault information, and analyzes the abnormality processing. A failure handling method for a multiprocessor characterized by increasing system reliability by being equipped with a centralized monitoring and control unit that has a function to