JPS6320633A - Information processor - Google Patents

Abstract

PURPOSE:To prevent another processing of a microprogram control part from being hindered to facilitate analyzing the trouble of a hardware control part by preventing interrupts other than forecasted interrupts. CONSTITUTION:If an interrupt factor (c) is turned on in a hardware control part 1 because of trouble or the like, an interrupt permitting circuit 14 outputs '0' to a signal line 34 because value '11' for the occurrence of an interrupt factor (a) is held in a register 22. Therefore, a microprogram control part 2 is not interrupted through the interrupt factor (c) is turned on, and another processing executed in the microprogram control part 2 is not hindered. Since the microprogram control part 2 gives no instructions to the hardware control part 1, information before giving of extra instructions is held as contents of the hardware control part 1.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an information processing device, and in particular to a microprogram control unit and a hardware control unit that interrupts the microprogram control unit and operates according to instructions from the microprogram control unit. The present invention relates to an information processing device including the following.

[Conventional technology]

In recent years, the number of information processing devices using microprogram control has been increasing, and one type of device that uses microprogram control is a microprogram control section and hardware that operates according to instructions from the microprogram control section. Wear control part? There is a device that performs the following operations.

The hardware system f:4 normally performs processing using its own 4]J interrupt, but when judgment or processing by the microprogram control unit is required, an interrupt is sent to the microprogram control unit in the form of an interrupt. The interrupt request is raised with information for determining the type of the interrupt, and the operation is suspended until an instruction is received from the microprogram control unit. On the other hand, the microprogram control section determines what is the cause of the interrupt in the hardware control section, and issues an instruction to the hardware control section according to the interrupt. The hardware control section resumes processing according to instructions from the microprogram control section, and continues processing until the microprogram control section makes a decision and processes again.

[Problem that the invention seeks to solve]

In the conventional information processing apparatus described above, even if the hardware control section erroneously raises an interrupt request due to a failure or the like, the microprogram control section gives an operation instruction in response to the raised interrupt request. However, if an interrupt is raised by mistake due to a malfunction or other cause, the interrupt cause will not be reset even if the microprogram control unit issues an operation instruction to the hardware control unit, and the There was a problem in that it interfered with the pond processing executed by the program control section. Further, there is a problem in that the inside of the hardware control section changes depending on the operation instructions of the microprogram control section, which complicates failure analysis of the hardware control section.

[Means for solving problems]

The device of the present invention includes a microprogram control unit, outputs an interrupt request consisting of an interrupt request signal and specific information specifying the interrupt to the microprogram control unit, and responds to an operation instruction corresponding to the interrupt request supplied from the microprogram control unit. and a hardware control unit that operates in response to the information processing device, a prediction signal generation unit that generates a prediction signal corresponding to an interrupt factor that is predicted to occur next in response to the supply of the specific information. , a prediction match that is provided for each of a plurality of interrupt factors whose occurrence order is known in advance, and generates a prediction-match signal when the interrupt factor that has occurred in response to the supply of the corresponding prediction signal is predicted. a signal generating means, an interrupt request signal generating means for generating the interrupt request signal in response to the supply of the predicted coincidence signal, and the specifying information for specifying the cause of the generated interrupt in response to the supply of the predicted coincidence signal. and generating interrupt factor specifying means.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The information processing apparatus shown in FIG. 1 includes a hardware control section 1 and a microprogram control section 2. The hardware control section 1 includes AND circuits 15 to 18 corresponding to interrupt factors a to d, respectively. , an interrupt permission circuit 14 , an OR circuit 19 , an encoder 20 , a flip-flop 21 , and a register 22 .

From hardware control unit 1 to microprogram control unit 2
to interrupt request signal 60 and interrupt parameter 30.3
1, an instruction signal 70 and an instruction parameter 71 are sent from the microprogram control section 2 to the hardware control section 1, respectively.

FIG. 2 is a diagram showing the order in which interrupt factors a to d of the hardware control unit 1 occur. In Figure 2, interrupt factor a
This indicates that the next occurrence is interrupt factor a or b, the next one is interrupt factor C or d, the next one is interrupt factor C, the next one is interrupt factor a, and the next one after interrupt factor d is one of interrupt factor a. Any combination other than this, for example, an interrupt in which interrupt factor C is followed by interrupt factor d does not occur under normal conditions.

FIG. 3 is a diagram showing the relationship between the input and output of the encoder 20. In FIG. 3, when the signal line 36 is "1", the output of the encoder 20 becomes '11', indicating that the interrupt factor a has been turned on.

When the signal line 36 is "O" and the signal line 37 is "1", the output of the encoder 20 becomes "10", indicating that the interrupt factor is turned on. When the signal lines 36 and 37 are “O” and the signal line 38 is °°1 pa, the output of the encoder 20 is “01”
, indicating that interrupt factor C has been turned on. When the signal lines 36, 37, and 38 are O'' and the signal line 39 is ``1'', the output of the encoder 20 becomes ``OO'', indicating that the interrupt factor d is turned on. Also, all signal lines 36 to 39 are “
0'', the output of the encoder 20 is undefined.

FIG. 4 is a diagram showing the relationship between the input and output of the interrupt permission circuit 14. In FIG. 4, when the interrupt parameter 30, 31, which is the input to the interrupt enable circuit 14, is "11", the output of the interrupt enable circuit 14 (signal line 32.3B,
34.35) becomes "1100". This means that the previous interrupt was interrupt factor a, and the next predicted interrupt is
Indicates that it is interrupt factor a or interrupt factor i. When the interrupt parameter 30.31 is "10", the output of the interrupt enable circuit 14 becomes "0011", which indicates that the previous interrupt was the interrupt factor and the next predicted interrupt is the interrupt factor C or the interrupt factor d. Furthermore, when the interrupt parameter 30.31 is "01", the output of the interrupt enable circuit 14 becomes "P1o o o", indicating that the previous interrupt was interrupt cause C, and the next predicted interrupt is an interrupt. Indicates that the cause is a, and sets the interrupt parameter 30.
31 or "OO", the output of the interrupt enable circuit 14 is 10.
o o'', indicating that the previous interrupt was the interrupt factor d, and the next predicted interrupt is the interrupt factor a.

Now register 22 of hardware control unit 1 is set to °°00”°
Assuming that the value of is held, the output of the interrupt permission circuit 14 is "1000". When interrupt factor a turns on in this state, interrupt factor a is turned on by AND circuit 15.
The flip-flop 21 is set through the OR circuit 19, and the output data of the encoder 20 is taken into the register 22. At this time, since the signal line 36 of the encoder 20 is "1", the data "1" indicates that the interrupt is the interrupt factor a.
1" is output. When the flip-flop 21 is set, the interrupt request signal 60 is turned on, and the hardware control section 1 stops operating until an instruction is received from the microprogram control section 2. At this time, the flip-flop The contents of register 21 are held until the interrupt is accepted, and the contents of register 22 are held until the next interrupt occurs.

When the microprogram control unit 2 accepts the interrupt,
Since the interrupt parameter 61 is "11", it is known that the interrupt is caused by interrupt factor a, and an instruction for this interrupt is given through the instruction signal 70° instruction parameter 71. Upon receiving this instruction, the hardware control section 1 resumes the stopped operation and starts moving again.

Suppose that the interrupt factor C is then turned on in the hardware control unit 1 due to a failure or the like. At this time, register 22
holds the value “11” when interrupt factor a occurred, so the interrupt enable circuit 14 outputs “11” to the signal line 34.
O” is output.

Therefore, even if the interrupt factor C is turned on, no interruption occurs to the microprogram control section 2, and other processing executed by the microprogram control section 2 is not inhibited. Furthermore, since the microprogram control section 2 does not issue any instructions to the hardware control section 1, the contents of the hardware control section 1 retain the information before giving any extra instructions.

〔Effect of the invention〕

As explained above, the present invention prevents interruptions other than predicted interrupts to prevent other processing of the microprogram control unit from being inhibited, and facilitates failure analysis of the hardware control unit. It has the effect of making

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the order in which interrupt factors occur in the hardware control unit 1, and FIG. 3 is a diagram showing the relationship between input and output of the encoder 20. , FIG. 4 is a diagram showing the relationship between the input and output of the v1 inclusion permission circuit 14. 1.--Hardware control section, 2.. Microprogram control section, 14.. Interrupt permission circuit, 15-18.
...AND circuit, 19...OR circuit, 20...encoder, 21...flip-flop, 22...register, 30.31...interrupt parameter, 60...interrupt request signal, 70... ...Indication signal, 71...Indication parameter, 32-41...Signal line, a, b, c, d...
- Interrupt factor. Figure 3

Claims (1)

[Scope of Claims] A microprogram control unit, which outputs an interrupt request consisting of an interrupt request signal and specific information specifying the interrupt, and responds to an operation instruction corresponding to the interrupt request supplied from the microprogram control unit. and a hardware control unit that operates in response to the information processing device, the information processing device comprising: a prediction signal generation unit that generates a prediction signal corresponding to an interrupt factor that is predicted to occur next in response to the supply of the specific information; , a prediction match signal that is provided for each of a plurality of interrupt factors whose occurrence order is known in advance and generates a prediction match signal when the interrupt factor that has occurred in response to the supply of the corresponding prediction signal is predicted; generating means; interrupt request signal generating means for generating the interrupt request signal in response to the supply of the prediction match signal; and generating the specific information for specifying the cause of the generated interrupt in response to the supply of the prediction match signal. An information processing device comprising: interrupt factor identification means.