JPS61131135A - Runway detector of microprocessor - Google Patents

Abstract

PURPOSE:To attain normal system operation by detecting a state that an output of an address latch enable signal is not given even after a prescribed time is elapsed by a runaway detection circuit so as to apply an interruption signal and an acknowledge signal to a microprocessor. CONSTITUTION:When the microprocessor 1 outputs an address data to a memory and an I/O port circuit section at accessing, the processor 1 also outputs an address latch enable signal (ALE). The signal ALE is outputted normally in a period of several mus several ms by a program, and if the signal ALE does not exist over a prescribed time longer the said period, a low level signal EACK is outputted. In this case, the interruption signal (INT) and the acknowledge signal ACK0 are fed to the processor 1. When the signal INT is applied, the processor 1 executes a runaway detection program to restore the system operation normally. When the signal ACK0 is inputted from an OR circuit 3, the busy state is released.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a runaway detection device for a microprocessor.

[Prior Art] Conventionally, microprocessors have relied on memory fetch error prevention circuits such as parity to prevent system malfunctions, which can cause serious problems if a program runs out of control.

[Problems to be solved by the invention] - However, with such a system, it is not possible to determine whether the program is operating normally or not, and therefore it is not possible to reliably prevent system malfunctions. This has caused problems such as data destruction or complete stoppage of operation.

The present invention was made to solve such problems, and an object of the present invention is to provide a microprocessor runaway detection device that can detect program runaway with a simple circuit and immediately return the system to normal. shall be.

[Means for Solving the Problems] The present invention outputs an address latch enable signal to access a memory, I/O port, etc., and also receives an acknowledge signal from the memory, I/O port, etc. A microprocessor that moves to the next operation and outputs an address latch enable signal to access memory, I/O ports, etc., and a microprocessor that is triggered in response to the address latch enable signal from this microprocessor. , and a runaway detection circuit that supplies an interrupt signal and an acknowledge signal to the microprocessor when the address latch enable signal is not input for a preset period of time, and the microprocessor receives the interrupt signal from the runaway detection circuit. The runaway detection program is executed based on the input.

[Function] In the present invention having such a configuration, as long as the microprocessor is operating normally and the system is operating normally, an acknowledge signal is input to the microprocessor from the memory, I/O port, etc. The address latch enable signal is repeatedly output from the processor. However, if the microprocessor goes out of control and the system operation becomes unstable, the input of acknowledge signals from the memory, /O boat, etc. continues.If this state continues, the output of the address latch enable signal from the microprocessor remains constant. The runaway detection circuit detects this and supplies an interrupt signal to the microprocessor to execute the runaway program, as well as an acknowledge signal to normalize system operation. .

[Embodiments of the invention]
Embodiments of the present invention will be described below with reference to the drawings.

In FIG. 1, 1 is a microprocessor.

This microprocessor 1 controls a circuit section 2 such as a memory and an I/O port using program data.

When the circuit unit 2 is in a state where it can be accessed from the microprocessor 1, it receives an acknowledge signal /O/MA.
CK is sent back to the microprocessor 1 via the OR gate circuit 3.

Furthermore, the microprocessor 1 outputs an address latch enable signal ALE when outputting address data to the circuit section 2 during access. This address latch enable signal ALE is supplied to a retriggerable monostable multivibrator 4 forming a runaway detection circuit. The address latch enable signal A
Depending on the program, the LE will have several stations to several Is during normal operation.
However, the multivibrator 4 is retriggered in response to the address latch enable signal ALE and outputs a high-level signal EACK, and when the input of the signal ALE is sufficiently longer than the above period, When there is no signal for a long set period of time, a low level signal EACK is output. The multivibrator 4
is supplied to the microprocessor 1 via the inverter circuit 5. When the multivibrator 4 outputs a low level signal EACK, an interrupt signal NT is supplied to the microprocessor 1, and an acknowledge signal is sent to the microprocessor 1. A signal ACKo is supplied via the OR gate circuit 3. When the microprocessor 1 receives the interrupt signal INT, it executes a runaway detection program and performs control to return the system operation to normal. Also, the acknowledge signal ACKO
The busy state is canceled by inputting .

In the device according to the embodiment of the present invention having such a configuration, normally, when the microprocessor 1 accesses the circuit section 2 such as memory or I/O port, the timing at which address data is output is as shown in FIG. 2(a). The address latch enable signal ALE is output to the address latch enable signal ALE. This signal AL
E is output at a cycle of several microseconds to several -5 depending on the program. The monostable multivibrator 4 is always re-triggered by the address latch enable signal ALE, and continues to output a high-level signal EACK as shown in FIG. 2(b). However, the inverter circuit 5
The output is always at low level. In this state, no interrupt is applied to the microprocessor 1. On the other hand, if the system is operating normally, the circuit section 2 responds to the access by (C
) is supplied to the microprocessor 1 via the off-gate circuit 3. As a result, the microprocessor 1 advances the program and moves to the next operation.

In this way, when the microprocessor 1 is operating the program normally and the system is operating normally, the circuit section 2 is operated by access from the microprocessor 1, and the circuit section 2 returns an acknowledge signal ACK to the microprocessor 1. and the monostable multivibrator 4 is always retriggered to output a high level signal EACK.
is outputting.

If the program runs out of control in this state, the system will not be able to operate properly. At this time, even if the microprocessor 1 accesses the circuit section 2, the circuit section 2 does not return an acknowledge signal ACK as shown in FIG. 3(C). Thus, the operation of the microprocessor 1 is stopped. Also, at this time, the microprocessor 1 outputs the address latch enable signal ALε at the time of access, and then stops outputting it at all, as shown in FIG. 3(a). If this state continues for a certain period of time, the monostable multivibrator 4 performs an inverting operation, changing its output signal EACK from a high level to a low level as shown in FIG. 3(b). As shown in FIG. 3(d), the microprocessor 1 receives a high-level interrupt l signal INT and an acknowledge signal ACKa through the inverter circuit 5.
will be supplied. In this way, the microprocessor 1 is interrupted and the runaway detection program is executed in the microprocessor 1. And □
System operation is restored to normal. Further, an acknowledge signal is supplied to the microprocessor 1 to release the busy state.

In this way, when a program runaway occurs in the microprocessor 1, a simple circuit consisting of the monostable multivibrator 4 and the inverter circuit 5 detects it and supplies the interrupt signal INT to the microprocessor 1. Since the runaway detection program is executed to normalize the system, malfunctions of the system due to runaway programs can be prevented as much as possible, and data destruction can also be prevented.

C. Effects of the Invention] As detailed above, according to the present invention, a microcontroller can detect program runaway with a simple circuit and immediately return the system to normal, thereby minimizing adverse effects on the system. A processor runaway detection device can be provided.

[Brief explanation of the drawing]

The figures show an embodiment of the present invention. Fig. 1 is a block diagram, Fig. 2 is a waveform diagram showing the output of each part when the program is normal, and Fig. 3 is a waveform diagram showing the output of each part when the program runs out of control. It is. 1...Microprocessor, 2...Memory, I/O
Circuit parts such as ports, 4...monostable multivibrator, 5...inverter. Applicant's representative Patent attorney Takehiko Suzue/O IOA4Ac, Figure 2, Figure 3(d) INT, AC, 0

Claims (1)

[Claims] The address latch enable signal is output to access the memory, I/O port, etc., and an acknowledge signal is input from the memory, I/O port, etc. to move to the next operation, and the address latch enable signal is input. A microprocessor that outputs signals to access memory, I/O ports, etc., and is triggered in response to an address latch enable signal from this microprocessor, and the input of the address latch enable signal is set in advance. and a runaway detection circuit that supplies an interrupt signal and an acknowledge signal to the microprocessor after a certain period of time, and the microprocessor executes the runaway detection program upon input of the interrupt signal from the runaway detection circuit. Microprocessor runaway detection device.