JPH01199238A - Data processor - Google Patents

Abstract

PURPOSE:To facilitate the collection of the state information at occurrence of an interruption by stopping the clocks of the related parts within a data processor when an interruption is detected. CONSTITUTION:When a mode signal 501 is set to '0', the signal lines 212 and 213 are set to '0'. Thus some factor of an interruption is registered into an interruption factor register 201. When an interruption request line 215 is set to '1' after an interruption request FF 209 is set to '1', an interruption request is given to an interruption control circuit 300. Then a signal line 412 is set at '1' in case some error is detected by a hardware error detecting circuit 400A. Thus a hardware error is reported to an error processing circuit 500 and the circuit 500 gives an instruction to a clock generating circuit 600 to stop the generation of clocks. In case an interruption request is produced with the signal 501 set to '1', no interruption request is given to the software and the action clocks are stopped for a data processor as a whole at that time point.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to a data processing device, and in particular to an interrupt detection circuit that detects the occurrence of a certain event, and an interrupt detection circuit that detects the occurrence of a certain event, and that interrupts software according to a request from the interrupt detection circuit. The present invention relates to a data processing device having an interrupt control circuit that performs interrupt reporting.

[Conventional technology]

Normally, when a certain event occurs in a data processing device,
There is an interrupt processing function that reports the event to the software and requests special processing, but the state inside the data processing device at the time of interrupt occurrence or interrupt detection is important in investigating the cause of the interrupt. In many cases, this information is useful. In particular, when an abnormal state is detected from another system due to some kind of failure in an interface between devices, etc. and a normal interrupt is reported, the state between the interfaces at the time of the interrupt detection is collected as analysis information in order to investigate the cause of the failure. The need arises. Therefore, in order to make it possible to read a large amount of information from software, the amount of hardware is increased and the data at the time of the interrupt is retained. However, due to the balance with the amount of hardware, Often subject to restrictions.

[Problem that the invention seeks to solve]

In the conventional data processing device described above, even if an interrupt occurs, the data processing device does not stop and continues processing, so the state at the time the interrupt is detected usually disappears.To prevent this, However, this method requires a means to increase the amount of hardware and hold as much information as possible, which has the drawback of increasing the amount of hardware.

(Means for Solving the Problems) The information processing device of the present invention includes: an interrupt cause register that holds an interrupt cause detected in the interrupt detection circuit; An interrupt request flip-flop that generates and holds an interrupt request to the control circuit; an error register that holds the cause of a hardware error detected within the data processing device; and an error register that holds the cause of a hardware error detected in the data processing device; On the other hand, there is an error report generation circuit that reports a hardware error, and when the report mode line is at the first logic level, the interrupt request of the interrupt request flip-flop is reported as an interrupt, and the report mode line is at the second logic level. an interrupt report conversion circuit that outputs the interrupt request as a hardware error to the error report generation circuit when the hardware error is reported; and a clock stop line that instructs the clock generation circuit from the error processing circuit to stop the clock when a hardware error is reported. have.

[For production]

By switching the mode of the report mode line and reporting it as a hardware error when an interrupt is detected, and stopping the clocks of the relevant parts in the data processing device, it becomes easier to collect status information at the time the interrupt occurs, and errors can be detected. Information useful for analysis etc. can be obtained.

【Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram of a main part of an embodiment of the data processing device of the present invention, and FIG. 1 shows the interrupt request generation circuit 200 of FIG.
4 is a block diagram showing in detail a portion of a hardware error detection/reporting circuit 400. FIG.

The interrupt request generation circuit 200 is an interface 700A.

700B is connected to the interrupt detection circuit 100, and this circuit detects a certain condition from the interfaces 700A, 700B, etc. and generates an interrupt request.The interrupt detected by the interrupt detection circuit 100 is transmitted to the signal lines 101, 102, 103. Check the contents of the interrupt cause register 201, interrupt request flip-flop 209, and interrupt cause register 201 registered in .104, and if all registers 201 are O, that is, no interrupt cause has occurred. At this time, the signal line 207 is set to logic 1 (becomes a set signal for signal lines 101 to 104), and when an interrupt factor is registered in the register 201, the signal line 107 is set to logic 0, the register 201 is locked, and the signal Line 208 is logic 1 and interrupt request flip-flop 209
a gate circuit 206 that sets the logic 1 to logic 1, and a gate circuit 211 that receives the mode signal on the mode signal line 501 as an input.
and the output signal line 21 of the interrupt request flip-flop 209.
0 and the output signal line 212 of the gate circuit 211, and when both are logic 1, the interrupt request line 215 is set to logic 1 and an interrupt request is made to the interrupt control circuit 300. Output signal 1lA 210 of request flip-flop 209 and output signal line 213 of gate circuit 211
It is composed of a gate circuit 216 that performs the NAND operation. The interrupt control circuit 300 performs request processing via the interfaces 800A and 800B in response to an interrupt request from the interrupt request generating circuit 200 via the interrupt request line 215, and reports the interrupt to software. The hardware error detection/reporting circuit 400 is a hardware error detection circuit 4 that detects hardware errors within the data processing device.
00A and a hardware error reporting circuit 40 that reports the detected hardware error to the error processing circuit 500.
Consists of 0B.

The hardware report circuit 400B includes an error register 405 in which hardware errors detected by the hardware error detection circuit 400A are registered via report lines 401, 402, 403, and 404, and the outputs of the error register 405 and the gate circuit 216. Check the status of the signal line 217, the signal line 217 is logic 1, and the signal lines 406 to 409
are all O, that is, when no hardware error is detected, the signal line 411 is set to logic 1 (signal lines 401 to 40
4 set signal), the error report line 412 is set to logic 0.
If some hardware error is detected by the hardware error detection circuit 400A and the contents are registered in the register 405, and as a result, any of the signal lines 406 to 409 becomes a logic 0, and the signal line 217 becomes a logic O. If the error occurs, the gate circuit 41 sets the signal line 412 to logic l and reports the hardware error to the error processing circuit 500.
Consists of 0. The error processing circuit 500 is connected to the signal line 4
12, the clock generation circuit 600 is instructed to stop the clock via the signal line 502, and when the interrupt request from the interrupt request flip-flop 209 is to be reported as an interrupt, the mode signal line 50
A mode signal of 1 is set to logic O, and when the error is reported to the error processing circuit 500 as a hardware error, the mode signal is set to logic 1.

Next, the operation of this embodiment will be explained.

(1) When the mode signal is set to logic 0.

In this case, the signal line 212 becomes logic 1 and the signal line 213 becomes logic 0, so when some interrupt cause is registered in the interrupt cause register 201 and the interrupt request flip-flop 209 becomes logic 1, the interrupt request line becomes logic 1. 215 becomes logic 1, and an interrupt request is output to the interrupt control circuit 300. On the other hand, since the output signal line 217 of the gate circuit 216 is at logic 1 at this time, if any hardware error is detected by the hardware error detection circuit 400A, the signal line 217
12 becomes logic 1, and a hardware error is reported to the error processing circuit 500. When error processing circuit 500 receives a hardware error report, it instructs clock generation circuit 600 to stop the clock through signal line 502.

(2) When the mode signal line 501 is designated as logic 1.

In this case, the signal line 212 is at logic O, and the interrupt request to the interrupt control circuit 300 is always suppressed, and the signal line 213 is at logic 1, so the interrupt request flip-flop 2
When the interrupt request line 210, which is the output of 09, is logic 1, the signal line 217 becomes logic 0 by the gate circuit 216, and as a result, the hardware error report line 412 becomes logic 1, indicating that a hardware error has occurred in the error processing circuit 500. Reported. In other words, by setting the mode signal to logic 1 in advance, if an interrupt factor is detected for some reason during operation in this state and an interrupt request is generated, the software is instructed to handle the interrupt. Instead of making a request, the operation clock of the entire device is stopped at that point by processing it as a hardware error, the state inside the device at the time of interrupt detection is retained as analysis information, and the data is processed using diagnostic operations such as shift path. You can make them collect.

(Effects of the Invention) As explained above, the present invention sets a mode signal that instructs the selection of whether to report the interrupt or report it as a hardware error when an interrupt is detected, and detects the interrupt at any time. By reporting this as a hardware error and stopping the clocks of the relevant parts of the data processing device, it becomes easier to collect status information at the time the interrupt occurs, which has the effect of providing information useful for error analysis, etc. In particular, if data is collected via the shift path while the clock is stopped, a considerable portion of the data can be collected without increasing the amount of hardware, which is extremely effective in investigating the cause of errors.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a main part of an embodiment of a data processing apparatus of the present invention, and FIG. 2 is a block diagram showing the connection relationship of each circuit in FIG. 1. 100--Interrupt detection circuit, 2QO--Interrupt request generation circuit, 300--Interrupt control circuit, 400--Hardware error detection/report circuit, 40
0A-...Hardware error detection circuit, 400 B-
...Hardware error reporting circuit, 500-...Error processing circuit, 60 (1-...Clock generation circuit, 700A, 700B, 800A, 800B...Interface, 201...Interrupt cause register, 206.211 , 214, 216, 410... Gate circuit, 209... Interrupt request flip-flop, 5(l
I = Mode signal line.

Claims (1)

[Claims] A data processing device comprising an interrupt detection circuit that detects the occurrence of a certain event, and an interrupt control circuit that reports the interrupt to software in response to a request from the interrupt detection circuit, an interrupt cause register that holds an interrupt cause detected by the interrupt detection circuit; an interrupt request flip-flop that generates and holds an interrupt request to the interrupt control circuit from the contents of the interrupt cause register; an error register that holds the cause of a hardware error detected within the data processing device; an error report generation circuit that reports a hardware error to an error processing circuit based on the contents of the hardware error; An interrupt that reports an interrupt request of an interrupt request flip-flop as an interrupt when it is at a logic level, and outputs the interrupt request as a hardware error to an error report generation circuit when the report mode line is at a second logic level. A data processing device comprising: a report conversion circuit; and a clock stop line that instructs a clock generation circuit from an error processing circuit to stop a clock when a hardware error is reported.