JPS60164844A - Detection for trouble of control circuit - Google Patents

Abstract

PURPOSE:To detect a trouble of a control circuit by providing a checking means which checks that only one of operation indicating means, which are outputted from a control circuit and a display means and indicate operations of a processing circuit, is effective. CONSTITUTION:In case of a trouble where a non-operation display signal 21 is not outputted, the non-operation display signal 21, a stage 1 operation signal 23, a stage 2 operation signal 24, and an operation completion signal 25 are not outputted. Therefore, a ''1 ouf of N'' check circuit 5 outputs an error detection signal 26 to detect the trouble of the control circuit. In case of a trouble where the operation completion signal 25 is kept outputted, the operation completion signal 25 and the non-operation display signal 21 are outputted simultaneously. As the result, the ''1 out of N'' check circuit 5 outputs the error detection signal 26 to detect the trouble of the control circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Technology] The present invention relates to a failure detection method for a control circuit of an electronic timing machine system.

[Conventional technology]

The logic circuits that make up the electronic computer system have one specific function! These processing circuits are broadly divided into various processing circuits that perform processing, and control circuits that control the operations of these processing circuits. Various fault detection methods such as the parity check method have been devised to detect faults that have occurred in processing circuits. According to these fault detection methods, the occurrence of a fault can be detected immediately at the time of the fault occurrence. It is possible to do so. On the other hand, regarding the detection of nine failures that occur in a control circuit, there are detection methods using a time-out check that detects when the first-speed processing controlled by the control circuit is completed within a certain amount of time, and a detection method that uses a control circuit. There is only a detection means that indirectly detects this abnormality using a processing circuit, and there is no detection means that directly detects a failure occurring in the control circuit. As a result, when a failure occurs in a control circuit, the processing operations of all nine circuits, including the circuit in which the failure has occurred, have progressed until the occurrence of the failure is known due to a timeout, making it difficult to investigate the cause of the failure. Information necessary for rounding may be disrupted or lost, and if an abnormality is detected in another processing circuit, there may be a failure in that processing circuit or circuit that detected the abnormality.
There is a problem that a large amount of time is required to investigate where in the circuit the failure has occurred and to eliminate the failure in the circuit.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a control circuit failure detection method that directly detects a failure occurring in a control circuit of an electronic computer system.

[Structure of the invention]

The present invention is characterized in that, in a fault detection method for a control circuit that controls the operation of a processing circuit, the present invention includes a display means for displaying that the control circuit is not operating, and the display means and the control circuit. The present invention further includes a testing means for testing whether only one of the operation instruction means for instructing the operation of the processing circuit outputted from the control circuit is valid, thereby detecting a failure in the control circuit.

[Embodiments of the invention]

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the invention. In FIG. 1, the control circuit includes a control circuit non-operation memory flip-flop 1 which stores that the control circuit is not operating and outputs a non-operation display signal 21 indicating that the control circuit is not operating. , an AND circuit 10 which performs a logical product of the non-operation display signal 21 and the operation request signal 13 requesting the operation of this control circuit and outputs a stage 1 request signal 22 requesting the start of the first control stage; , 1st
Stage 1
The first control stage is in operation, which outputs the operation signal 23, and the memory flip-flop 2 is in operation.The second control stage is in operation, which stores the fact that the second control stage is in operation and outputs the stage 2! a control circuit operation completion memory flip 7p block 4 that memorizes that the operation of this control circuit has been completed and outputs an operation completion signal 25; a non-operation display signal 21; and a stage 1 operation signal 2.
3 and stage 2 operation wander signal 24 and operation completion signal 2
5 is valid, and if only one of them is valid, an error detection signal 26 is output if υ is not 1 out
The of N check circuit 5 monitors the time from when the operation request signal 13 is input until the operation completion signal 25 is output, and if the operation completion signal 25 is not output even after a certain period of time has elapsed, It has a timeout check circuit 6 that outputs a timeout detection signal 27. The input signal 11 of step 1 is input to the first processing circuit 71 , and similarly the second input signal 12 is input to the second processing circuit 8 . The first output signal 14 output from the first processing circuit 7 and the second output signal 15 output from the second processing circuit 8 are input to the third processing circuit 9. from the third
The output signal 16 of the stage 11111 production signal 23, the stage 2 m+crop multiplication signal 24 and the operation completion signal 25 are No output. In this state, when the operation request signal 5-13 is input, the AND circuit 10 outputs the stage 1 start request signal 22. The timeout check circuit 6 detects that the operation request signal 13 is input, and starts time monitoring to determine whether or not the operation completion signal 25 is output within a certain period of time.

In the next machine cycle (ts), the first control stage operating storage flip flop 2 which has received the stage 1 start request signal 2'2 outputs the stage 1 operating signal 23. At the same time, the stage 1 start request signal 22 is input as a reset signal to the control circuit non-operation memory flip-flop 1, and the control circuit valve operation memory flip-flop 1 stops outputting the non-operation display signal 21. Assuming that the stage 1 operation signal 23 is not output due to a failure of the first control stage operating memory 7 lip 2, the non-operation display signal 21, the stage 1 operation signal 23 and the stage Since neither the 2-operation signal 24 nor the operation completion signal 25 is output, the 1-out-of-N check circuit 5 outputs an error detection signal 26, and at this point, a failure in the control circuit 6- is immediately detected. Furthermore, if we assume a failure in which the non-operation display signal 21 remains output, the non-operation display signal 21 and the stage 1 operation signal 23 will not be output at the same time. outputs an error detection signal 26, and a failure of this control circuit is detected. The first processing circuit 7 receiving the stage 1 operation signal 23 receives the first input signal 11 and outputs the first output signal 14 . Similarly, the second processing circuit 8 receives the stage 1 operation signal 23, receives the second input signal 12, and outputs the second output signal 15.

Next, in the machine cycle (tl), the second control stage operating memory 7 lip 7a, which has received the stage 1 operating signal 23, outputs the stage 2 operating signal 24. At the same time, the stage 1 operating signal 23 is input as a reset signal for the first control stage operating storage flip-flop 2, and the first control stage operating storage flip-flop 2 stops outputting the stage 1 operating signal 23. Here, we assume a failure in which the stage 2 operation signal 24 is not output.
7=Since neither the worker number 24 nor the operation completion signal 25 is output, the l out of N check circuit 5 outputs the error detection signal 26, and a failure of this control circuit is detected. Furthermore, assuming a failure in which the stage 1 operation signal 23 remains output, the stage 1 operation signal 23 and the stage 2 operation signal 24 will not be output at the same time, or the 11 out of N check circuit 5 outputs an error detection signal 26 to detect a failure in this control circuit. The third stage receives the stage 2 operation signal 24.
The processing circuit 9 receives the output signal 14 from the first processing cape 7.
The third output signal 16 is output by inputting the output signal 15 from the second processing circuit 8.

In the next machine cycle (im), the control circuit operation completion memory 7 lip-flop 4 which has received the stage 2 operation signal 24 outputs an operation completion signal 25.

At the same time, the stage 2 operating signal 24 is input as a reset signal to the second control stage operating memory flip-flop 3, and the second control stage operating memory flip-flop 3 stops outputting the stage 2 operating signal 24. The timeout check circuit 6 detects that the operation completion signal 25 is output and stops time monitoring.

Here, assuming a table failure so that the operation completion signal 25 is not output, since none of the non-operation display signal 21, stage 1 operation signal 23, stage 2 operation signal 24, and operation completion signal 25 is output, 1out
The fN check circuit 5 outputs an error detection signal 26, and a failure of the control circuit is detected. Furthermore, assuming a failure in which the stage 2 operation signal 24 is output 11, the stage 2 operation signal 24 and the operation completion signal 25
1 out o
The fN check circuit 5 outputs an error detection signal 26,
A failure of this control circuit is detected.

In the next machine cycle (t4), the operation completion signal 2
The control circuit non-operation memory 7 lip-flop 1 which received the control circuit 5 outputs a non-operation display signal 21. Simultaneously, operation completion signal 25
is input as a reset signal to the control circuit operation completion memory flip-flop 9- 70 and knob 4, and the control circuit operation completion memory flip-flop 4 receives the operation completion signal 25.
This completes the series of control operations. and ζ, assuming a failure in which the non-operation indication signal 21 is not output, since none of the non-operation indication signal 21, the stage 1 operation signal 23, the stage 2 operation signal 24, and the operation completion signal 25 are output, 1outo
The fN check circuit 5 outputs an error detection signal 26, and a failure of this control circuit is detected. In addition, the operation completion signal 2
If it is determined that a failure such as 5 remains output, the operation completion signal 25 and non-operation display signal 21 will be output at the same time, and the 1 out of N check circuit 5 will output an error extraction signal. 26 is output, and a failure in this control circuit is detected. Test 10 to check whether only one of the operation 970 means of the control stage is effective. This has the effect of being able to directly check for any malfunctions that may occur.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the invention. . 1...Control circuit non-operating memory flip-flop,
2... First control stage operation memory flip-flop, 3... Second control stage @#+ operation memory flip 20 tabs, 4... Control circuit operation completion memory Flip-flop, 5...bow out of
N check circuit, 7...first processing circuit, 8
...Second processing circuit, 9...Third processing circuit, 10...AND circuit, 11...
・First input signal, 12... Second input coefficient,
13...Operation request signal, 14...First
output signal, 15... second output signal, 16.
...Third output signal, 21...Non-operation display signal, 22...Stage 1 start expense request number, 2
3... Stage 1 operation signal, 24...
Stage 2 sweetfish production signal, 25...Operation completion signal,
26...Error detection signal, 27...Timeout detection signal.

Claims (1)

[Claims] In a failure detection method for a control circuit that controls the operation of a processing circuit, there is provided a display means for displaying that the control circuit is operating, and an instruction for the operation of the processing circuit that is output from the display means and the control circuit. and testing means for testing whether only one of the operation instruction means is effective, and detecting a failure in the control circuit.
Failure detection method for control circuit as e.