JPS6051141B2 - Program runaway detection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for detecting program runaway in an arithmetic processing device that requires high-speed real-time processing.

2. Description of the Related Art Arithmetic processing devices such as microprocessors are usually provided with a monitoring function to detect whether a program is being executed correctly without running out of control.

This type of program runaway monitoring method includes a method of inserting a specific monitoring program into the main program and a method of using a monitoring interrupt program separate from the main program. As an example of the former method, a specific monitoring program is inserted and executed every M steps of the main program, the number of steps between each monitoring program is counted, and runaway occurs depending on whether this is M or not. How to detect the presence or absence of M in one main program?
There is a method of inserting M monitoring programs and detecting whether a runaway has occurred based on whether or not the above-mentioned monitoring programs have been executed M times when the main program is executed for the first time. In addition, as an example of the latter method, an interrupt is generated based on a clock with a constant period, a specific monitoring interrupt program is executed, the result is decoded, a pulse is generated, and whether or not the pulse is generated is determined. However, the former method requires that the number of steps change in the arithmetic processing unit where interrupt processing occurs and that it is difficult to detect runaway that occurs during processing. There is a problem that it cannot be applied at all because it cannot be done, and a problem that if a monitoring program is inserted into the main program, the processing time increases accordingly, making it unsuitable for a device that performs high-speed real-time operation.

In addition, in the latter method, when a runaway occurs, the decoder for detecting the calculation result of the monitoring interrupt program is accessed, and a lock occurs as if the correct processing was being performed.As a result, the runaway occurs. This has the problem that detection may not be possible.

Therefore, the present invention solves the above-mentioned problems of the prior art, and an object of the present invention is to reliably detect the occurrence of program runaway in an arithmetic processing device that requires high-speed real-time processing. The purpose of the present invention is to provide a method for detecting program runaway.

The features of the present invention for achieving the above object are as follows:
In an arithmetic processing device that has a plurality of interrupt programs in addition to a main program and performs real-time processing, means for applying a runaway monitoring interrupt pulse having a predetermined cycle to the arithmetic processing device, and execution in response to the interrupt pulse. and a runaway monitoring interrupt program that generates an operation confirmation pulse when a predetermined interrupt process is correctly executed, and has a runaway monitoring interrupt program whose priority is not the highest, and means for counting the operation confirmation pulse,
The number n of interrupt pulses applied to the arithmetic processing unit is compared with the number N of operation check pulses counted, and when α is zero or a positive integer, if N<n-α or n<N, the program An object of the present invention is to provide a program runaway detection method characterized in that a notification to the effect that runaway has occurred is provided.

The reason for setting N<n and N<n-α will be explained below.

In an arithmetic processing device that has a plurality of interrupt programs in addition to the main program and performs real-time processing, when a runaway monitoring program is provided, it is necessary to avoid interfering with real-time processing as much as possible.

In order to achieve this, the present invention uses the runaway monitoring program as an interrupt program, and by giving it a low priority, the runaway monitoring program is executed while the interrupt program with a higher priority is not being executed. However, since interrupt programs with a higher priority than the runaway monitoring program are usually executed randomly, the product of the execution time and execution frequency of each interrupt program and the execution time of the runaway monitoring program is the sum of the execution time of the runaway monitoring program. If the interval is close to the occurrence interval of Due to the generation of interrupt pulses, the number N of operation confirmation pulses may become smaller than the number n of interrupt pulses. α is set as the allowable number of times when the number of operation confirmation pulses is small, and the system is implemented so that it recognizes a runaway when N<n-α instead of N<n. The invention will be described in detail. Fig. 1 is a block diagram of an embodiment of the invention, in which 10 is a microprocessor that executes arithmetic processing by a main program to monitor the occurrence of runaway; 12 is a processor 10; a timer that generates an interrupt pulse of a predetermined period to be applied to the
4 indicates a counter for counting the number n of interrupt pulses applied to the microprocessor 10, respectively. When an interrupt pulse is applied from the timer 12, the processor 10 executes a predetermined interrupt calculation process for detecting runaway, and accesses the decoder 16 if the calculation result is correct. The decoder 16 generates one operation confirmation pulse each time it is accessed, and the counter 18 counts the number N of pulses.
Counter 1 Counter 18 count value N. , N are compared and determined in the comparison/discrimination circuit 20, and if n<N or N<n-α (Tata7, α is zero or a positive integer), it is determined that a runaway has occurred, and, for example, the display mechanism 22 or an alarm is issued. When the comparison is completed,
A reset pulse is output from the reset circuit 24, and the counters 14 and 18 are reset. As described above, in this embodiment, the number N of operation confirmation pulses is counted by the counter 18, and if the number N is larger than the number n of interrupt pulses applied to the processor 10, the decoder 16 is erroneously detected due to runaway or the like. It is assumed that the site has been accessed by someone else, and a notification of an out-of-control situation is sent.

Furthermore, if the count value N of the operation confirmation pulse is smaller than n-α, it is assumed that the interrupt processing has not been performed correctly due to runaway or other failure, and a runaway occurrence is notified. Here, α is appropriately selected as a value of 0, 1, 2, . . . based on the relationship between the processing time of the interrupt program having a higher priority than the runaway detection interrupt program and the period of the runaway detection interrupt pulse. FIG. 2 is a circuit diagram more specific to the embodiment described above, and FIGS. 3A, B, C, and D are time charts thereof.

However, in this case, n is set to a constant value of n=3, and α is set to α=1. The interrupt pulse IRQ as shown in FIG. 3A output by the timer is output on line 26.
The signal is applied to the microprocessor 10 (FIG. 1) via the inverter 28 to perform the monitoring interrupt processing as described above, and is also applied to the clock terminal of the counter 14 via the inverter 28. As a result, the least significant bit output QAl of the output of the counter 14 and the upper bit output QBl of the saw stage become as shown in FIG. 3A, and the pulse CLK3 becomes low level every time three interrupt pulses are applied. It is obtained as the output of the NAND circuit 30. This pulse CLK3 is the NOR circuit 3
2, resulting in pulses CLK, , CLK″4, or CLK″″4 shown in FIGS. 3B, C, and D, respectively,
By applying these pulses CLK4, CLK''4, and CLK''4 as clocks to the D-type flip-flop 34, the state of the flip-flop 34 at that point in time, that is, at the point in time when three interrupt pulses are generated, is determined.

The pulse CLK3 is also applied to the D-type flip-flop 36, and after a predetermined delay, the pulse CLK3 shown in FIG.
A reset pulse CLKl as shown in FIG. 1 is generated to reset the counters 14 and 18 as well as the flip-flop 36 itself. Next, a case will be described in which the main program does not run out of control and operates normally.
In this case, the decoder 16 shown in FIG. 1 is accessed once every time the runaway monitoring interrupt process is performed, and the operation confirmation pulse CLK2 shown in FIG. 3B is sent to the counter 18 via the line 38 each time. Therefore, the least significant bit output QA2 of the output of the counter 18 and the sequentially higher order bit outputs QB2 and QO2 are as shown in FIG. 3B. It should be noted here that the bit output QB8 is at a high level, that is, the level of logic "1" at the time when the clock CLK4 is applied to the flip-flop 34, and the bit output QB8 is at a high level, that is, the level of logic "1".
2 is applied to the clock CLK4, the level of logic "゜1゛" is never reached.

In other words, this means that the number N of operation confirmation pulses generated until the number n of interrupt pulses reaches n=3 is either N=2 or N=3.
It means that.

In such a case, the 100 output ALM of the flip-flop 34
is always at the logic "0" level, and an alarm signal indicating the occurrence of runaway is not output.If the number of operation check pulses N that have occurred until the number of interrupt pulses n reaches n=3 is N=0 or N=1. In this case, as shown in FIG. 3C, the bit output Q"B2 of the counter 18 is at the logic "0" level at the time when the clock CLK"4 is applied to the flip-flop 34. O output AL
M'' is inverted to the logic level of ``1'', and therefore an alarm signal indicating the occurrence of runaway is output.

Furthermore, if four or more operation confirmation pulses occur before the number of interrupt pulses reaches n=3, as shown in FIG. 3D,
Bit output Q″ of counter 18.

2 becomes the level of logic 4 "1" and 5, and the flip-flop 34 is immediately cleared, so at that point the O output ALM" becomes the level of logic "1" and the occurrence of runaway is notified.

As described above, according to the configuration shown in FIG. 2, n=3, so if N<2 or 3<N, a runaway occurrence notification will always be given.

Next, the relationship between the period T and α of the interrupt pulse will be explained.

When a runaway monitoring interrupt process is requested or if an interrupt process request with a higher priority occurs during the interrupt process, the runaway monitoring interrupt process enters a standby state.

Figure 4 shows this situation, where a indicates main program processing, b indicates runaway monitoring interrupt processing, c indicates other higher priority interrupt processing, and d indicates processing during execution 7. , El, e2, and e3 represent the times when the timer 12 requests an interrupt for runaway monitoring. That is, even if an interrupt request occurs at time E2, it is necessary to wait until the high-priority interrupt processing is completed, and during that time, the decoder 16 is not accessed and the operation confirmation pulse 9 does not appear. Therefore, ignoring the processing time of the runaway monitoring interrupt processing, the maximum duration of the interrupt processing with a higher priority is T.
. Then, the period T of the interrupt pulse for runaway monitoring is T. <
When T, the error of the number N of operation confirmation pulses generated by the above-mentioned waiting period with respect to the number n of interrupt pulses is 1 at maximum. Therefore, in this case, α only needs to be 1 or more. Also, liver. <T, α can also be set to 0. As explained in detail above, according to the method of the present invention,
The number n of interrupt pulses requesting runaway monitoring interrupt processing is compared with the count value N of normal operation confirmation pulses for the interrupt processing, and when N<n-α or n<N, a runaway occurrence notification is issued. This allows us to reliably detect the occurrence of runaways and failures, and since it is monitored by interrupt processing, no extra steps are inserted into the main program, and no other steps are inserted. The present invention can also be applied to an arithmetic processing device in which interrupt processing is performed.

Therefore, if the present invention is applied to an arithmetic processing device that requires high-speed real-time processing and handles more interrupt processing than its surroundings, such as an arithmetic processing device that performs transmission/reception control in data transmission, it will be of great benefit.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a circuit diagram of a more specific example of the above embodiment, Fig. 3 is a time chart of Fig. 2, and Fig. 4 is an interrupt wait time chart. FIG. 10...Microprocessor, 12...
Timer, 14, 18... Counter, 16...
...Decoder, 20... Comparison/discrimination circuit, 22...
... Display mechanism, 24 ... Reset circuit, 34
, 36...D type flip-flop.

Claims (1)

[Scope of Claims] 1. In an arithmetic processing device that has a plurality of interrupt programs in addition to a main program and performs real-time processing, means for applying a runaway monitoring interrupt pulse having a predetermined cycle to the arithmetic processing device; The interrupt program includes a runaway monitoring interrupt program that is executed in response to the interrupt pulse, generates an operation confirmation pulse when a predetermined interrupt process is correctly executed, and has a runaway monitoring interrupt program that does not have the highest priority, and means for counting the operation confirmation pulses. , compare and determine the interrupt pulse n applied to the arithmetic processing unit and the counted number of operation check pulses N, and when α is zero or a positive integer, if N<n-α or n<N. A program runaway detection method is characterized in that a notification to the effect that a program runaway has occurred is provided. 2. Claim 1 in which the number n of interrupt pulses applied to the arithmetic processing device is obtained by counting the pulses.
Program runaway detection method described in section. 3. The program according to claim 1 or 2, which compares and determines the count value N of the operation confirmation pulses obtained when a predetermined number n of interrupt pulses are applied to the arithmetic processing device. Runaway detection method.