JPH04106637A - Stall detection circuit - Google Patents

Abstract

PURPOSE:To enable an information processor itself to detect its own stall within appropriate monitoring time by monitoring the repeating time of the same microprogram operation or the waiting time for the execution of a microprogram by means of a counter. CONSTITUTION:A comparator circuit 2 compares the address 51 of the currently executed microprogram from an address register 5 with the address 11 of the microprogram executed immediately before the currently executed microprogram from an address buffer register 1. When the compared addresses do not coincide with each other, the circuit 2 sets a discordance signal 21 to logic '1' and, when the addresses coincide with each other, sets a coincidence signal 22 to logic '1'. A counter 3 is reset synchronously to a system clock 70 when the discordance signal 21 from the circuit 2 is logic '1' and counted up synchronously to the clock 70 when the coincidence signal 22 from the circuit 2 is logic '1'. The counter 3 sends a stall signal 31 when the count value overflows. Therefore, an information processor itself can detect its own stall with appropriate monitoring time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a stall detection circuit, and more particularly to a stall detection circuit that detects a stall in a microprogram in a microprogram control type information processing apparatus.

[Conventional technology]

Conventionally, in this type of information processing device, the operation of the same microprogram may be repeated due to a malfunction or the like, or the microprogram may stop functioning due to no response from other devices and the execution of the microprogram is forced to wait). As a method for detecting a stall in an information processing device, there is a method in which the information processing device is periodically monitored by another device, for example, a diagnostic device.

[Problem to be solved by the invention]

In the conventional stall detection method described above, it is generally difficult to accurately predict the length of time to be monitored.
We had no choice but to set a time length with considerable leeway. Therefore, there is a drawback that the stall detection of the information processing apparatus is delayed, and since the cause of the functional stoppage of the information processing apparatus is unknown, recovery measures cannot be taken, and there is a high possibility that the system will go down.

[Means to solve the problem]

The stall detection circuit of the present invention includes: an address buffer register in which a currently executed microprogram address is set; a comparison circuit that compares the currently executed microprogram address with the value of the address buffer register; and a counter that is reset by the non-coincidence output signal and counts up while the coincidence output signal of the comparator circuit is being output, and sends out a stall signal when the counter reaches a predetermined value.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, one embodiment of the present invention includes an address buffer register 1, a comparator circuit 2, a counter 3, a control memory 4, and an address register 5.

Next, the operation of this embodiment will be explained.

The microprogram address 60 to be executed is connected to the AT input of the control store 4 and to the data input of the address register 5. Furthermore, the microprogram address 51 currently being executed is connected to the data input of the address buffer register 1 and one input of the comparison circuit 2, and the microprogram address 11 executed immediately before is connected to the other input of the comparison circuit 2. Connected. The comparison circuit 2 receives the currently executing microprogram address 5 from the address register 5.
1 and the most recently executed microprogram address 11 from the address buffer register 1, and when the results do not match, the mismatch signal 21 is set to logic "1", and when the results match, the match signal 22 is set to logic "1". Make it logical “1°. The counter 3 is reset in synchronization with the system clock 70 when the mismatch signal 21 from the comparator circuit 2 is logic '1', and is reset in synchronization with the system clock 70 when the match signal 22 from the comparator circuit 2 is logic '1'. A stall signal 31 is sent out when the count value overflows.

Note that the stall monitoring time is set based on the frequency of the system clock 70 and the number of bits of the counter 3.

〔Effect of the invention〕

As explained above, the present invention is based on the time when the currently executed microprogram address matches the immediately previously executed microprogram address, that is, the repetition time of the same microprogram operation or the time during which the execution of the microprogram is awaited. By monitoring this using a counter, there is an effect that the information processing apparatus itself can detect its own stall within an appropriate monitoring time.

Register, 11...Address of the microprogram executed just before, 21...Disagreement signal, 22...Coincidence signal, 31...Stall signal, 51...Address of the microprogram currently being executed, 60...Execution Should microprogram address, 70... system clock.

Claims (1)

[Claims] an address buffer register in which the address of the microprogram currently being executed is set; a comparison circuit that compares the address of the microprogram currently being executed with the value of the address buffer register; 1. A stall detection circuit comprising: a counter that is counted up while a coincidence output signal of a comparison circuit is being outputted; and a stall detection circuit that sends out a stall signal when the counter reaches a predetermined value.