JPS5983438A - Program failure detecting system - Google Patents

Abstract

PURPOSE:To attain the detection of failure of a more strict program, by checking that a monitor timer reset instruction from a program enters the range for a prescribed count time. CONSTITUTION:A monitor clock producing circuit 33 generates a timing pulse, which is inputted to a clock device counting a counter of a monitor timer 32. A carry output signal 385 of the counter is made active after a prescribed time if no reset input is given to the timer 32, a failure detection FF37 is set and a program failure detection signal line 40 is made active. When the program is operated normally, a monitor timer reset instruction is outputted via a processor bus 20. An I/O decoder 31 receives this instruction and outputs a timer reset signal 381. The monitor timer is reset by this signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides software (
This invention relates to a method for detecting abnormalities in programs.

Conventionally, various circuits have been used to detect this type of program abnormality, and a so-called watchdog timer is one of them. This means that if the monitoring timer is not reset by the program for a certain period of time, the program will become abnormal and run out of control.It will determine that the program is not running on the specified route, and the system will use interrupt processing or other means. It is used to handle abnormalities and recover the system.

According to this method, if the program goes out of control and repeats a loop including a supervisory timer reset instruction, abnormality cannot be detected forever. For this reason, measures are taken to ensure the normality of the system itself, such as detection by external monitoring equipment and self-reporting by subscribers.

However, the former method has the drawback of increasing the amount of hardware, and the latter method has the drawback of reducing serviceability.

The present invention has been made in view of the above-mentioned conventional circumstances, and therefore, an object of the present invention is to check whether a monitor timer reset command from a program is within a certain fixed count time range. This provides a new program abnormality detection formula that eliminates the above-mentioned drawbacks.

That is, the program abnormality detection power formula of the present invention can be used when the reset signal of the monitoring timer from the program is received at the counting time 'rBTt+o)t of the monitoring timer, or between the counting time T1 and T2 CTl <T2). The feature is that if the program is not received, it is detected as a program abnormality.

The values of the count times T1 and T2 of the monitoring timer are determined in relation to the program configuration. The sibling program recognizes the time by the interval timer interrupt, and the interval timer period becomes the time base, and the reset period of the watchdog timer is determined, so the count time of the watchdog timer is T1.
is set to a value that is at least equal to or greater than this period.

Next, a preferred embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows the position of the program abnormality detection circuit of the present invention in the system. A program executes processing on the central processing unit 10. The program sends a monitoring timer reset command to the program abnormality detection circuit 30 via the processor bus 20 using an algorithm stipulated by the program structure.
Send to. When the program abnormality detection circuit 30 detects a program abnormality, it sends an interrupt to the program abnormality detection signal line 40, an interrupt to the central processing unit 10, and reports it to an external device. In addition, in a redundant system, it is reported to the mate system, and the ACT/5TAND B of the entire system is
Switch Y.

FIG. 2 shows a detailed configuration of the program abnormality detection circuit 30. In this embodiment, the interval timer interrupt is 1
(Since it is kns, the count time n of the monitoring timer is 4Q.
ms and T2 are each set to 160m5. In this case, due to the program configuration, a restriction is set so that the monitor timer reset command is not output within 40m5. The supervisory clock generation circuit 33 generates a timing pulse of 10m5 cycles, which is inputted as a clock for counting the counter of the supervisory timer 32 every 1Qms. The monitoring timer 32 is set to 16 when there is no reset input.
When 0 ms elapses, the counter's carry output signal 38
5 becomes active (hereinafter referred to as "ACTIVE"), and the abnormality detection flip-flop (hereinafter referred to as "stage") 37
and set the program abnormality detection signal line 40 to "ACT".
ffE”.

If the program is operating normally, a supervisory timer reset command is output via the processor bus 20. The VO decoder 31 receives the command and outputs a supervisory timer reset signal 381.

The monitor timer 32 is reset by this reset signal 381. If there is a program error, 9 T1=40
If the reset signal 381 is output within ms, the 22-bit counter output of the monitoring timer 32 and the i-pit become 0.
”, the circuit 35 is not “ACTIVE”, the abnormality detection F/E' 37 is set through the zero circuit 36, and there is no reset signal until T2 = 160 ms. , program abnormality detection signal line 4
O-4 ("ACTIVE" K -f le.

Abnormality detection F/F' 37 is system reset signal line 38
8 is reset. Further, the monitoring timer 32 is also reset by the system reset signal line 389.

The values of the count times T1 and T2 of the monitoring timer are set to appropriate values in terms of the program configuration, separate from the values of this embodiment, so it is easy to change the values by switching jumper wires or making them programmable. By the way.

Compared to the conventional watchdog timer circuit, the abnormality detection method according to the present invention has a circuit 35 as shown in this embodiment.
．． 36 only increases.

As explained above, the present invention enables more precise program abnormality detection with a smaller increase in the amount of hardware compared to conventional methods, improves serviceability of the system as a whole, and improves the hardware of the entire system. It has the effect of reducing the amount.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the position of the program abnormality detection circuit in the system, and FIG. 2 is a detailed block diagram showing one embodiment of the program abnormality detection circuit according to the present invention. 10, central processing unit, 20. ,,processor bus,
30. ,. Program abnormality detection circuit, 31. ,,I10 decoder,
3200. Monitoring timer (counter), 33. ,,supervision clock generation circuit, 37. ,,Anomaly detected/F ,34
．． 35.36. ,, Logic circuits, 381-389. ,,signal line,40. ,, Program error detection signal line

Claims (1)

[Claims] In the data exchange processing device, the monitor timer reset signal from the program is sent to the monitor timer count time 'r.
A program abnormality detecting power formula characterized in that a program abnormality is detected when the program is received within a time period of T1 to T2 (TI<T2) or when it is not received within a count time of T1 to T2 (TI<T2).