JPH0296840A - Runaway prevention circuit of central processing unit - Google Patents

Abstract

PURPOSE:To prevent the increase of a circuit scale and to securely detect a runaway by outputting a runaway detection signal which is synchronized with synchronous communication to a signal line between central processing units and supervising the signal in a timer circuit for a prescribed period. CONSTITUTION:When synchronous communication is performed between the central processing units 1 and 2, the signal which has synchronized with the synchronous communication between respective central processing units 1 and 2, namely, the runaway detection signal, is generated, and the runaway detection signal from one central processing unit 1 is checked in the other central processing unit 2, whereby the runaway detection signal is outputted from the central processing unit 2. The signal is supervised in the timer circuit 3 for the prescribed period. When the central processing unit 1 has run away, the central processing unit 2 detects the runaway, and it prevents the occurrence of communication for the timer circuit 3. When the central processing unit 2 has run away, the timer circuit 3 counts up and resets a system since communication for the timer circuit 3 is prevented. Thus, circuit constitution can be miniaturized and the precision of runaway detection can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a runaway prevention circuit suitable for preventing runaway of a central processing unit in a system composed of a plurality of central processing units.

[Conventional technology]

Conventionally, as a runaway prevention circuit for this type of central processing unit,
For example, there is something like the one shown in Figure 5.
This will be explained with reference to the figures. In the figure, reference numerals 1 and 2 denote a plurality of central processing units as microprocessors, and each of these central processing units 1 and 2 is provided with a runaway detection circuit ti12 for detecting runaway of the central processing unit. . At this time, each runaway detection circuit 1f12 is input with signals around the central processing unit 1, such as address signals, data signals, C8 signals, etc., in which rlJ and rOJ are constantly changing, and these runaway detection circuits 1f12 are inputted. The detection circuits 11 and 12 respectively monitor the signal lines at regular intervals, and detect runaway when the signal no longer changes.

Then, the outputs of the respective runaway detection circuits 11 and 12 are logically summed in the logical sum circuit 13, and the output is inputted to the reset circuit 4 of the central processing unit system, so that either one of the central processing units 1 or 2 After detecting runaway, the system is set up and the system is set up again from the initial settings.

[Problems that the invention helps solve]

However, in the conventional circuit described above, as the number of central processing units (also called MPUs) increases, a runaway detection circuit is required for each processor, so the circuit size increases as the number of processors increases. Put it away. In addition, the signals for detecting runaway may run out so that the rIJ and rOJ signals stop changing at the time of runaway, or may not stop changing even if runaway occurs.In the former case, runaway can be detected. However, in the latter case, there was a problem that it could not be detected.

The present invention has been made in view of the above points, and its object is to prevent a runaway prevention circuit for a central processing unit that can reliably detect runaway without increasing the circuit scale even when the number of central processing units increases. Our goal is to provide the following.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a method for detecting runaway in synchronization with synchronous communication between the central processing units when synchronous communication is performed between the central processing units in a system composed of a plurality of central processing units. an output means for generating a signal to each central processing unit, inspecting a runaway detection signal from another central processing unit, and outputting a runaway detection signal from the central processing unit; The system is equipped with a timer circuit that counts up after a certain period of time when the runaway detection signal is no longer output, and a reset circuit that initializes the system based on the count-up output of the timer circuit.

[Effect]

Therefore, in the present invention, when any one of the plurality of central processing units stops outputting the runaway detection signal, the timer circuit counts up after a certain period of time.
The count-up output of the timer circuit allows the reset circuit to reset the central processing unit system and initialize it.

〔Example〕

Hereinafter, the present invention will be described in detail based on embodiments shown in the drawings.

FIG. 1 is a block diagram showing an embodiment of a runaway prevention circuit for a central processing unit according to the present invention. In Figure 1, 1,
Reference numeral 2 denotes a plurality of (two in this example) central processing units as microprocessors, and the first central processing unit 1 and the second central processing unit 2 operate in a time-consuming manner as shown in FIG. 2 (&). The first central processing unit 1 performs synchronous communication at
In synchronization with the timing of this synchronous communication, the program generates a signal as shown in FIG. 2(b) as a runaway detection signal, and transmits the signal to the second central processing unit 2 via the signal line 5. . In addition, the second central processing unit 2 is configured as shown in FIG.
) is generated as a runaway detection signal, and the signal from the central processing unit 1 is inspected and a signal associated with whether the signal is normal or abnormal is generated as a runaway detection signal. At this time, the central processing unit 2
The signal generation is stopped if the signals from rOJ and rlJ are not regular alternating signals or if rOJ and rlJ are fixed. The signal from the central processing unit 2 is transmitted to the timer circuit 3 via the signal line 6.
Enter to reset. This timer circuit 3 operates for a certain period T.
The CPU performs a count-up operation, inputs the counted-up signal to a reset circuit 4, and outputs a reset signal from the reset circuit 4, thereby initializing the central processing unit system.

In the runaway prevention circuit configured as described above, if the central processing unit 1 goes out of control as shown in FIG. 3 while performing synchronous communication between the central processing units 1 and 2, this central processing unit The signal will no longer be output from (see the same figure (, )).

Then, since no signal is received from the central processing unit 1, the central processing unit 2 does not output a signal to the timer circuit 3 (see FIG. 3(b)).

Therefore, since the reset signal is not supplied to the timer circuit 3 within a certain period T, the timer circuit 3 counts up and resets the reset circuit 4.
(See figure (c)).

As a result, the reset circuit 4 generates a reset signal based on the count-up output (see (d) in the same figure).
Reset the central processing unit system as before.

Furthermore, even when the central processing unit 2 goes out of control, as shown in Figure 4, although the central processing unit 1 outputs a normal signal (see (, ) in the figure), the central processing unit 2 outputs a normal signal. No signal is output regardless of the central processing unit 1 (see (b) in the same figure).

Therefore, as described above, the timer circuit 3 can reset the system by counting up and outputting a signal to the reset circuit 4 (see (e) and (d) in the figure).

According to this embodiment, when synchronous communication is performed between the central processing units 1 and 2, a runaway detection signal is generated that is synchronized with the synchronous communication between the central processing units 1 and 2, A runaway detection signal from one central processing unit 1 is checked by the other central processing unit 2, and the runaway detection signal is output from the other central processing unit 2, and the signal is monitored by a timer circuit 3 for a certain period of time. As a result, the central processing unit 1 goes out of control, and at 9:00, the central processing unit e2 detects the runaway, and the timer circuit 3
A timer circuit 3 is counted up and reset without generating a signal to. Furthermore, if the central processing unit 2 goes out of control, no signal is generated to the timer circuit 3, so the timer circuit 3 can count up and be reset. This eliminates the need to provide a runaway detection circuit in both the central processing unit and the central processing unit as in the prior art, thereby providing the advantage that the circuit configuration can be made smaller and the accuracy of runaway detection can be improved.

〔Effect of the invention〕

As explained above, according to the present invention, a signal line and a timer circuit are provided as a means of communication between central processing units, and a runaway detection signal synchronized with synchronous communication between central processing units is outputted to the signal line by a program. By monitoring the signal using a timer circuit for a certain period of time, runaway in the central processing unit can be detected by simply adding signal lines without the need for a special runaway detection circuit, allowing the circuit size to be reduced. . Furthermore, since the runaway detection signal is generated by the program, there are effects such as more accurate detection of runaway.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a time chart of a synchronous communication signal and a runaway detection signal, which is used to explain the above embodiment, and Fig. 3 is also provided to explain the above embodiment. A time chart when the first central processing unit goes out of control;
FIG. 4 is a time chart when the second central processing unit goes out of control, which is also used to explain the above embodiment, and FIG. 5 is a block diagram showing an example of the prior art. j, 2##11-central processing unit, 3.-# timer circuit, 411@.-reset circuit, 5.6e... signal line. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] In a system consisting of multiple central processing units,
When synchronous communication is performed between central processing units, each central processing unit generates a runaway detection signal synchronized with the synchronous communication between the central processing units, and checks the runaway detection signal from other central processing units. an output means for outputting a runaway detection signal from the central processing unit; a timer circuit that counts up after a certain period of time when the runaway detection signal is no longer output from any one of the central processing units; A runaway prevention circuit for a central processing unit, comprising a reset circuit for initializing the system by outputting a count up.