JPH07230432A - Calculating device - Google Patents

Abstract

PURPOSE:To analyze a fault after use without adding a measuring instrument specially even for the purpose of use wherein a fault can not be analyzed during the use by providing a bus monitor means which monitors a bus transaction and a history storage means which stores a signal value on a bus. CONSTITUTION:If a fault occurs to one of processors, an abnormal signal detecting circuit 12 detects that and stops a memory control circuit 13 from sending a control signal. When the processor restarts operating after the fault occurrence, one of the processors sends a command to a bus transaction detecting circuit 11 through the bus 4 and then the memory control circuit 13 is stopped from sending the control signal. The contents of a nonvolatile memory 24 are not rewritten thereafter and information on the bus transaction right before the fault occurs is saved in the nonvolatile memory 24. Consequently, no special measuring instrument need not be added even for the purpose of use wherein a fault can not be analyzed during the use, and the fault information can be read out and analyzed afterward.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to analysis of a fault due to interworking between processors in a computer having a plurality of processors connected by a bus.

[0002]

2. Description of the Related Art In a computing device in which a plurality of processors are connected by a bus, the processors operate while interacting with each other. Therefore, even if the operation of each processor is verified, there is a possibility of failure due to the interaction. Such disorders may occur intermittently or accidentally depending on the timing of interaction. Since it is difficult to verify all the timings in advance, it is important to improve the system integrity by providing recovery means and failure analysis means on the assumption that a failure will occur to some extent.

[0003] Especially when the failure occurred during flight cannot be analyzed without returning to a maintenance facility on the ground, as in the case of mounting on a small aircraft, it is important to save the failure information. This is because it is difficult for an intermittent or accidental fault to be reproduced at a maintenance facility on the ground, and the cause cannot be analyzed unless the fault information is saved.

The problems of the prior art will be described based on an example. FIG. 5 shows a conventional computing device including, for example, two processors. 1 and 2 are first and second processors, respectively, 3 is a shared memory, 4 is a bus connecting all of them, and 5 is a request from each processor. It is an arbiter that takes as input and outputs the number of the processor that grants permission.

In the conventional computing device, the first processor 1 (hereinafter referred to as A) happens to interact with the second processor 2 (hereinafter referred to as B) through the bus 4 (that is, interprocessor communication or data transfer) at a certain timing. As a result, if a failure occurs such that the operation of A goes out of control or the processing does not end within a predetermined time, A starts exception processing and the state of A at that time is stored in the shared memory 3. Write and save as fault information. As a result of occurrence of a failure in A, there may be a case where a secondary failure such as B not being able to obtain a response from A within a predetermined time, and in that case, B similarly changes the state of B to shared memory 3 To save the failure information.

[0006]

In the above computing device, the failure information of each processor can be saved when a failure occurs, but what interaction it has with other processors and what processor it is. It is impossible to know whether the failure of the above is first and the failure of other processors is secondary. Obviously, it can be observed if a measuring device is attached, but if the measuring device cannot be attached during flight as in the case of mounting on a small aircraft, analysis is impossible. The intermittent failure can be retried or forcedly reset to resume the operation, but the failure cause will continue to be used without being known, which may lead to a serious failure in the future.

The present invention has been made in order to solve such a problem, and even in a use in which failure analysis is impossible during use, it is possible to analyze a failure after use without adding a special measuring device. It is an object of the present invention to provide a computing device.

[0008]

Since the interaction between processors is performed by communication between processors via a bus or data transfer (hereinafter collectively referred to as a bus transaction), it is necessary to understand all bus transactions. All interactions will be understood. Therefore, the computing device of the present invention is provided with bus monitoring means for connecting to the bus to monitor bus transactions and history storing means for connecting to the bus and storing signal values on the bus. Also,
The bus monitoring means is provided with an abnormal signal detection circuit for inputting an abnormal signal from each processor and a memory control circuit for outputting a control signal to the history storage means. Further, the history storage means is provided with a timer and a non-volatile memory for storing bus transaction information.

[0009]

In the computer configured as described above, the bus
Each time a transaction occurs, the bus monitoring means detects it and sends a control signal to the history storage means. The history storage means receives the control signal and writes the signal value on the bus into the nonvolatile memory, and at the same time, the arbiter Write the processor number permitted by and the output of the timer indicating the time in the non-volatile memory. When a fault occurs, the bus monitoring means detects it by the abnormal signal detection circuit, and stops the memory control circuit from sending the control signal to the history storage means. Therefore, the bus transaction information immediately before the occurrence of the failure is stored in the history storage means.

[0010]

【Example】

Example 1. FIG. 1 is a block diagram showing an embodiment of the present invention, and 1 to 5 are the same as the conventional example. Reference numeral 10 is a bus monitoring means, 11 is a bus transaction detection circuit connected to the bus 4, 12 is an abnormal signal detection circuit for inputting an abnormal signal from each processor processor 1, 2.
Reference numeral 13 is a memory control circuit. Reference numeral 20 denotes a history storage means, 21 of which is a timer, 22 and 23 are a counter and an overflow flag which constitute the timer 21, and 2
Reference numeral 4 is a non-volatile memory which receives the output of the bus 4, the arbiter 5, the timer 21, and the control signal from the memory control circuit 13.

Next, the operation of this embodiment will be described. For example, a bus from the second processor 2 to the first processor 1
When there is a transaction, the bus / transaction detection circuit 11 detects it, and the memory control circuit 13 sends a control signal to the history storage means 20. In response to the control signal, the history storage means 20 receives the control signal, the value of the counter 22 and the overflow flag 23, which is the output of the timer 21, the signal value on the bus 4, and the processor number, which is the output of the arbiter 5, in the nonvolatile memory 24. Write to. Here, the counter 22 is constantly counting up, and when it reaches the upper limit value, the overflow flag 23 is set and it returns to zero. The overflow flag 23 is cleared when the output of the timer 21 is written in the nonvolatile memory. By repeating the above operation, information of all bus transactions is written in the nonvolatile memory 24. The nonvolatile memory 2
When 4 is written to the final address, it is overwritten from the first address again, so that the latest bus transaction information is always stored. As a result of the operation as described above, information such as the time when the bus transaction occurs, the processor number that caused the bus transaction, the contents of the bus transaction, etc. is stored in the non-volatile memory 24, for example, as shown in FIG.

When a failure occurs in any one of the processors, the abnormal signal detection circuit 12 detects it and stops the memory control circuit 13 from sending a control signal. When restarting from the occurrence of a failure, one of the processors sends a command to the bus transaction detection circuit 11 through the bus 4 to stop the memory control circuit 13 from sending a control signal. After that, the contents of the non-volatile memory 24 are not rewritten, and the information of the bus transaction immediately before the failure occurs is stored in the non-volatile memory 24.

When analyzing a failure, the nonvolatile memory 2
By reading the information of No. 4, it is possible to analyze which bus transaction the fault has a causal relationship with, and which processor fault is first and the fault of the other processor is secondary.

Example 2. 2 is a block diagram showing another embodiment, in which the same numerals as those in FIG. 1 indicate the same constituent elements, and 25 corresponds to the nonvolatile memory 24 in FIG. 1, but may be volatile memory, 26. Is a backup non-volatile memory connected to the memory 25. In this embodiment,
When a failure occurs in any one of the processors, the abnormal signal detection circuit 12 detects it, and the memory control circuit 13 sends a control signal to backup the entire contents of the memory 25.
Copy to 6. When the fault is resumed, the bus transaction information is continuously written. In this embodiment, the bus transaction information is automatically saved in the backup non-volatile memory 26 even if the processor does not send a command as in the embodiment of FIG.

Further, by using the hardware of the present invention in the following method, it is possible to obtain a temporal order relation between tasks running on each processor, that is, an interprocessor task schedule. First, in the first step, each of the processors 1 and 2 writes to a specific address of the shared memory 3 by software every time the task is switched. This write bus transaction is performed by the timer 21.
Is stored in the history storage means 20 together with the value of. At the time of failure analysis, any one of the processors stops the bus monitoring means 10 in the second step. In the third step, any one of the processors reads out the bus transaction information stored in the history storage means 20, and extracts only the bus transaction information written to the specific address in the first step. As a result of the above operation,
For example, an inter-processor task schedule immediately before a failure as shown in FIG. 4 can be obtained.

In the above embodiment, the case where the number of processors is two has been described, but the same applies when the number of processors is three or more.

[0017]

As described above, since the information on the interaction between the processors immediately before the occurrence of the failure is automatically saved, the measuring device is specially used even in the case where the failure analysis cannot be performed during use. This fault information can be read out and analyzed later without adding the.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing another embodiment of the present invention.

FIG. 3 is a diagram showing an example of saving bus transaction information.

FIG. 4 is a diagram showing an example of a task schedule between processors.

FIG. 5 is a block diagram showing a conventional example.

[Explanation of symbols]

 1 First Processor 2 Second Processor 3 Shared Memory 4 Bus 5 Arbiter 10 Bus Monitoring Unit 11 Bus Transaction Detection Circuit 12 Abnormal Signal Detection Circuit 13 Memory Control Circuit 20 History Storage Means 21 Timer 22 Counter 23 Overflow Flag 24 Nonvolatile Memory 25 Memory 26 Backup non-volatile memory

Claims (5)

[Claims] 1. A usage right when a plurality of processors, a shared memory shared by the plurality of processors, a bus connecting the plurality of processors and the shared memory, and a bus usage right request from the plurality of processors are input. An arbiter that outputs the number of the processor that has acquired the bus, a bus monitoring unit that is connected to the bus to monitor the bus transaction, and a history storage unit that is connected to the bus and the arbiter to store the information of the bus transaction. A computing device comprising: 2. The bus monitoring means includes a bus transaction detection circuit connected to the bus, an abnormal signal detection circuit for inputting an abnormal signal from each processor, and a memory control for outputting a control signal to the history storage means. The computer according to claim 1, further comprising a circuit. 3. The computer according to claim 1, wherein the history storage means includes a timer, and a nonvolatile memory which receives signals from the timer, the bus and the arbiter. 4. The history storage means comprises a timer, a memory to which signals from the timer, the bus and the arbiter are input, and a backup non-volatile memory connected to the memory. The computing device according to 1. 5. The timer comprises a counter and an overflow.
5. The computer according to claim 3, further comprising a flag.