JPS6275744A - Program monitoring system - Google Patents

Abstract

PURPOSE:To monitor the executed condition of a program without giving any influences to the processing program, by providing means which outputs address bus, data bus, and control bus information to the outside in a system to be monitored. CONSTITUTION:Address bus information, control bus information, and data bus information read by a central controller 11 from a main memory 12 are respectively stored in an address buffer 14, control buffer 15, and data buffer 13 through an address bus 102, control bus 103, and data bus 101. The address bus information and control bus information are respectively sent to the address matching circuit 331 of a supervisory system 3 and the control circuit 333 of the system 3 through monitor buses 2. At a supervisory circuit 33 control information is extracted by a designated monitor address and stored in a memory 32, and then, checked, displayed, and so forth, by a supervisory system controller 31 and supervisory system display device 34.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a program monitoring method, and particularly to a method for monitoring a program without affecting the execution of a system processing program.

[Conventional technology]

Conventional monitoring techniques during debugging include: - Including a program to assist the monitor within the processing program of the system being debugged; - Simulating the program on a different system rather than on the system being debugged. There are two methods: one in which a probe is installed in the system to be debugged, such as an in-circuit emulator, and the other is monitored.

In addition, conventional techniques for monitoring program execution status include: ■ A method in which a higher-level program in the monitored system monitors the execution status of lower-level programs; ■ A hardware timer is installed in the monitored system, and the timer is set periodically by a program. There are two methods: - A method that monitors program runaway by initializing the program, and a method that periodically outputs a normal signal from the system program to be monitored.

[Problem that the invention seeks to solve]

With the conventional program monitoring method described above, detailed execution status cannot be monitored, and if the program execution status is to be monitored in detail, the load increases and the processing speed decreases. Furthermore, it is difficult to debug the system while keeping it in exactly the same state as after entering service.

An object of the present invention is to provide a program monitor system that solves these problems.

[Means for solving problems]

The program monitor method of the present invention includes an output section for outputting address bus, data bus, and control bus information sound from a processing system including a storage program processor, an input section for inputting a monitor address, and an input section for inputting a monitor address from the output information. The device has an extracting section for extracting information, a memory section for storing the extracted information, and a display section for displaying the memory contents of the memory section.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a hardware configuration diagram of an embodiment of the present invention, in which a monitored system 1. A monitored system 1, which indicates a monitor bus 2 and a monitoring system 3, is a processing system including a storage program type processor, and a central control unit 1.
1. and main memory 12, data bus 101,
address bus 102. They are connected via a control bus 103. System 1 is.

address bus information read from main memory 12;
Address buffer 14 for temporarily storing control bus information and data bus information and outputting it to the outside. Control buffer 15. It has a f-ta buffer 13,
These are address bus 102, control bus 103. It is connected to the data bus 101. Reference numeral 104 in the main memory 12 of the monitored system 1 indicates a program to be monitored.

Data buffer 13 of monitored system 1. Address buffer 14. The control buffer 15 is connected to the monitoring circuit 33 of the monitoring system 3 via the monitor bus 2. The monitoring circuit 33 includes an address register 332, an address match circuit 3316, a control circuit 333. buffer memory 3
34, which are the monitored systems 1.
address buffer 14. Control buffer 15.
They are respectively connected to the data buffer 13 via the monitor bus 2. The monitoring circuit 33 further includes an address register 332 into which a monitor address is input in advance, and the output of the address register 332 is a monitor address signal line 33.
5 is connected to the other power supply of the address match circuit 331. An address match signal line 336, which is an output of the address match circuit, is connected to a control circuit 333, and the control circuit 333 is connected to a buffer 334. The above address register 332. Control circuit 333. Buffer memory 334 is connected to monitoring system bus 301. The monitoring circuit 33 extracts information from the monitor address in the main memory 12 of the monitored system 1, as will be described later.

The monitoring system 3 further includes a monitoring system memory 32 for storing information extracted by the monitoring circuit 33, and a monitoring system display device 34 for displaying the contents of this memory. It has a monitoring system control device 31 that controls the entire monitoring system 3, and these monitoring system memories 32. Monitoring system display device 34. The monitoring system control device 31 is connected to the monitoring system bus 3 old.

FIG. 2 shows part of the flow of the program 104 to be monitored. In Figure 2, BR indicates conditional branch processing, and E
VI and EV2 are event writing.

4 shows a process of setting control information of the program 104, such as reading.

Next, an overview of the overall operation of this embodiment and details of the operation of each part will be explained. The central controller 11 has a main memory 1
- Execute the program 104 stored in 2. In the course of executing the program 104, the central control m1ll accesses control information in the main memory 12 using the data bus 101, the address bus 102, and the control bus 103. As a result, the address bus information and control bus information read from the main memory 12,
Data bus information is transmitted through address bus 102. Control bus 103. Address buffer 14 . Control buffer 15. Each is stored in the data buffer 13.

The address bus information is sent to the address match circuit 331 of the monitoring system 3, the control bus information to the control circuit 333, and the data bus information to the buffer memory 334 via the monitor bus 2. The monitoring circuit 33 extracts the address bus information, control bus information, and data bus information (these pieces of information are collectively referred to as control information) sent from the monitored system 1 according to the specified monitor address, and extracts the extracted control information. Information is stored in the supervisory system memory 32 via the supervisory system bus 3.

The control information stored in the monitoring system memory 32 is stored in the monitoring system controller 31 . Control information is checked, displayed, etc. by the monitoring system display device 34.

The above is an overview of the overall operation. Next, the operation of the monitoring circuit 33 will be explained in detail. As shown in FIG. 2, the program 104 in the main memory 12 is stored in main memo January 2 in EVI and EV2 after condition determination in BR.
Access the control information in the control information setting memory allocated in the . The monitoring circuit 33 uses the same address as this control information setting memory address as a monitor address.
The address register 332 is set in advance.

A monitor address signal line 335, which is an output of the address register 332, is input to an address match circuit 331, and the address match circuit 331 detects a match between the address being accessed by the monitored system 1 and the monitor address. The output of the address match circuit 331 is input to the control circuit 333 via an address match signal line 336. The control circuit 333 detects access to the monitor address by the monitored system 1 and notifies the monitoring system control device 31, and also sends control information sent via the monitor bus 2 to the monitoring system memory 32 through the buffer memory 334. Write.

The supervisory system controller 31 reads control information from the supervisory system memory 32 via the supervisory system bus 301 and sends it to the supervisory system display 34 . Surveillance system 3
Now, the monitored control information is displayed on the monitoring system display device 34.
The program 104 can be traced by displaying the program 104 in order. Furthermore, when the monitoring system 3 reads out specific control information, the monitoring system 3 can control the monitored system 1 and perform operations such as issuing an alarm. Furthermore, by changing the monitor address in the monitoring system 3, it becomes possible to monitor any part of the program 104 of the monitored system 1.

〔Effect of the invention〕

As explained above, in the present invention, by providing means for outputting address bus, data bus, and control bus information to the outside within the monitored system, it is possible to easily connect the monitored system to a monitoring system placed outside the monitored system. This makes it possible to monitor the execution status of a program without affecting the processing program of the monitored system, which is effective for collecting program behavior and failure data when a failure occurs, and for system debugging, maintenance, and Reliability can be improved.

[Brief explanation of drawings]

FIG. 1 is a hardware configuration diagram of an embodiment of the present invention, and FIG. 2 is a diagram showing part of a program flow within a monitored system. 1... Monitor target system 2...
・ Monitor bus 3 ... Monitoring system 11 ... Central control unit 12 ... Main memory 13 ... Data buffer 14 ...
... Address buffer 15 ... Control buffer 101 ... Data bus 102 ... Address bus 103 ... Control bus 104 ...
... Program 31 ... Monitoring system control device 32
...... Monitoring system memory 33 ...
- Monitoring circuit 34 ... Monitoring system display device 331
...Address match circuit 332...
Address register 333... Control circuit 334... Buffer memory 335... Monitor address signal line 336...
・・・ Address Match Signal Line Agent Patent Attorney Iwa
Yoshiyuki Sa 1--Monikuna 1 staring system 31...Supervision system child control device 2...Monikunogusu 3
2. Monitoring system 10 system memory 3... - Supervising system
33...-rmHD**11... Centrally installed egg device 34-Q rear system display, device 12...
Main menu 331... - Atoshi Smart 7+
Colloquial language 13...te°"-ta Jma...I"77 3
32...-Ato Shisushi"Mata 14-...Ato"'Shisu lX"11.Fa 333...Control wholesale 0 route 15~-
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Claims (1)

[Claims] (1) An output section that outputs address bus, data bus, and control bus information from a processing system including a storage program type processor, an input section that inputs a monitor address, and an extraction section that extracts information on the monitor address from the output information. A program monitor system having a memory section, a memory section for storing extracted information, and a display section for displaying the memory contents of the memory section.