JPS60254332A - Data processor - Google Patents

Abstract

PURPOSE:To reduce hardware for adding a false fault by collecting status information in a main memory and setting a false fault for the information obtained by compressing and editing said collected information. CONSTITUTION:False fault information is received from a diagnosis control part 140 and stored in a fault detecting information storage area 220 of the main storage 200 and false fault setting time information is also received from the diagnosis control part 140 to start time monitoring. When the false fault setting time information is turned to ''0'', the clocking of a processing part 100 is stopped and an instruction to freeze the status information of each part at the false fault setting time is applied to the diagnosis control part 140 to freeze the status information. After receiving a freezing completion report, a false fault setting flag formed in a memory 420 is set to ''1'' and then the frozen status information of each part is collected. Since the false fault setting flag has been set to ''1'', it is rewritten to ''0'' and then CPU initializing operation is started. Said operation is equivalent to the status that the an FF in an error detecting latch circuit of the processing part 100 is set to ''1'' because of the fault and a fault signal is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing apparatus, and more particularly to a data processing apparatus having means for confirming failure processing due to a pseudo failure.

[Conventional technology]

As information processing systems become more complex and sophisticated, the processing functions for system failures also become more complex and diverse.

Maintaining this high degree of reliability has become an important issue.

For this reason, a method is used to generate a pseudo failure and check whether the processing function operates as expected.

In conventional data processing equipment, the method described above is to apply a pseudo fault to the actual circuit (functional block that constitutes the processing unit) or to directly apply a pseudo fault signal to the fault detection circuit. After detecting the fault, a signal notifying that a fault has occurred is given to the fault processing function circuit 1 through this circuit.

′　It activates the related circuits.

[Problem that the invention seeks to solve]

Therefore, conventional data processing devices require an additional circuit (for example, an OR circuit) to provide a pseudo fault to each circuit (each functional block).

This method has the drawback of increasing the amount of hardware needed to confirm failure handling.

[Means for solving problems]

The data processing device according to the present invention has a processing section and a main memory, and a fault detection storage means is provided for each functional block constituting the processing section and detects and stores a fault in the functional block and generates a start signal. and writing means for reading out state information of the processing section including at least the fault detection storage means and writing it into the main memory in response to the supply of the activation signal.

Editing means for selectively extracting and editing the state information corresponding to the fault detection storage means in the state information written in the main memory after the completion of the writing, and storing the editing result in the fault detection information storage means; .

and a fault processing means for initializing the processing unit after completion of storage by the editing means, analyzing the contents of the fault detection information storage means, and performing predetermined fault handling; means for storing bundled failure information specified in advance in a storage means; signal generation and activation means for generating the activation signal at a specified time to activate the writing means; and the activation from the signal generation and activation means. and activation means for inhibiting the editing means and activating the failure handling means when the writing of the writing means activated in response to a signal is completed, and the failure handling confirmation is much easier than in conventional data processing devices. It is characterized by reducing the amount of hardware required.

EMBODIMENTS Next, two embodiments of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, one embodiment of a data processing apparatus according to the present invention is illustrated in a block diagram.

a processing unit (CPU) 100 that performs information processing operations;
Main memory (MM) 200 that stores programs and data
.

It is comprised of a memory access control unit 300 that controls access to the main memory 200 and a service processor unit (SVP) 400 that performs failure handling, maintenance, and the like.

The processing section 100 includes a plurality of cracks 110, 120, and 130, and a diagnostic control section 140 that diagnoses these cracks. - The package 110 is equipped with a plurality of circuits 14-4, 112, and 113 that perform predetermined functions.

The output of each circuit is connected to an error detection latch circuit (E
DL) 114, 115 and 116 are added. Each error detection sub circuit monitors the error in the output of each circuit, detects it when an error occurs, and connects it to the Friso deflop circuit (F/F) in its own circuit.
At the same time, a logic "1" is sent to the diagnostic control unit 140 via the OR gate 117 to notify the occurrence of a failure. In addition.

・Although not shown in FIG. 2, the Yakkake 120 and 130 are equipped with circuits similar to the Yakkake 110 in terms of failure detection.

The diagnostic control unit 140 is a circuit that controls the interface between the service processor unit 400 and the processing unit 100, and simultaneously notifies the service processor unit 400 of failure notifications from each guccano.
Diagnosis control of each circuit in the processing section 100 is performed under control from 00.

The error log area 210 in main memory 2°00 is 2,
This is an area for storing status information of each part of the processing unit 100 at a certain point in time, and a failure detection information storage area 220 in the main memory 200 where the status information is stored includes information stored in the error log area 210. Among the status information, processing unit 1
The state information corresponding to the error detection latch circuit 00 is selectively extracted, edited, and stored.

Zorocessor 410 in the service Zorocessor section 400
The memory is controlled by a program and performs fault processing, diagnosis, maintenance, etc.

420 stores extra programs, data, and the like.

- Figures 2, 3 and 4 are flowcharts of nine embodiments.
; As shown, ■ in Figure 2 is replaced by ■ in Figure 3.

■ in Figure 3 follows ■ in Figure 4, respectively. next.

The operation of the two embodiments will be explained with reference to FIGS. 1 to 4.

First, let's talk about what to do when an actual failure occurs.

Next, a failure handling operation confirmation test using a pseudo failure will be explained.

a. Treatment process when an actual failure occurs @ 10. , QK implemented・Guckage 1
For example, if a fault occurs in the circuit 112 in the circuit 10, this will be detected by the error detection latch circuit 115, and the error detection latch circuit 15 will detect the occurrence of the fault in the flip-flop circuit in the circuit. It stores the fact that the fault A1 has occurred, and sends a logic "1" to the diagnostic control unit 140 via the OR gate 117 to notify that the fault has occurred. In response to the supply of this failure notification signal, the diagnostic control unit 140 stops the clock of the processing unit 100, freezes and holds the status information of each unit at the time of failure, and also causes the service processor unit 40 to stop the clock of the processing unit 100.
0 (step 51).

Hereafter, Noro Kassa 4 in the service processor section 4.00
Failure processing is performed by the operation 10.

That is, first, it is determined whether or not the interrupt requests execution of a pseudo-failure setting command, which will be described later (step 52).
). In this case, it is confirmed that there is an actual number of failures and that an actual failure has occurred in step 53, and step 63 is entered. Note that if no actual failure has occurred, other processing is performed, but since this is not the subject of this embodiment, a description thereof will be omitted.

Next, the processor 410 executes the frozen processing unit 1 described above.
"Status information in 00" is collected. . Namely.

Noyackage address in processor 410 -
The address of the package whose status information is to be collected first (hereinafter, the contents stored in the address register will be abbreviated as PKG-ADR8) is set in the data register (not shown) (step 63). In addition, Zorosessa 410
The main memory address in the register (not shown) is the start address of the error log area 210 in the main memory 200 where state information is to be stored.

The contents stored in the main memory address register M M
, -ADR8) (step 64)
0 then 2 PKG-ADR to the diagnostic control unit 140
Step 65) to send 8 PKG-ADR
It instructs to read the status information of the flip-flop circuit (F/F) that stores the occurrence of an error in the error detection launch circuit installed in the package specified in step 8 (step 66). For this reading, a known method 9 is used, such as a method of using a scan path and a method of switching using a selector. Next, step 67) confirms whether the read status information has been received, and step 68) confirms whether ψ is installed in the corresponding Noggano. If confirmed, the read status information is stored in the error log area 210 of the main memory 200 indicated by MM-ADR8 (step 69). A certain MM-ADR with the contents of the storage address register and the package address register.
3 and PKG-ADR3 step 70
, 72), and return to step 65 again. 2) Repeat the operations described above to collect all state information in the processing unit 100.
Do it. When it is confirmed in step 68 that f is not implemented, it means that there is no valid status information 1d, so the error log area 210 contains the first 9
This will move on to the operation of collecting Tsukeno's status information.

Having collected and stored the status information of all the cages,
It is confirmed in step 71, and step 73 is reached, and since the pseudo fault setting flag (as described later, this flag is set to logic "1" only during the fault handling confirmation test) is logic "0", step 74 is reached. reach

In step 74, the information corresponding to the error detection latches scattered in the error log area 210 is read and edited, and in the next step 75, the edited fault detection information is used to detect the fault in the main memory 200. It is stored in the detection information storage area 220. Next, in step 77, the diagnostic control unit 140 is instructed to initialize the processing unit 100 to restore it to the state before the failure occurred. Thereafter, the status information in the failure detection information storage area 220 is analyzed and failure processing is performed (step 78). This failure handling is a well-known technique and is not the subject of this embodiment, so its explanation will be omitted.

This concludes the explanation of what to do when an actual failure occurs, but the point is that what is necessary for failure handling is how to collect status information of each part at the time of failure. Then, in order to confirm the failure handling operation, the question becomes how to create status information of each part at the time of failure in the failure detection information storage area 220.

The failure handling operation confirmation test using pseudo failures will be explained below.

b. Test for confirming failure handling operation due to pseudo-failure In this case, the processing unit 100 is performing arbitrary processing, and the operation is checked when a failure occurs at a specified location of the processing unit 100 at a specified time in the middle of the process.

First, from the 9 diagnostic control unit 140 to the service processor unit 40
An interrupt is made at 0 (step 51).

Thereafter, the processor 410 continues the operation.

That is, it is recognized that the interrupt requests execution of an instruction (hereinafter abbreviated as pseudo-fault setting instruction) V for setting a pseudo-fault (step 52). Therefore, the pseudo-failure setting command at least specifies the time at which the pseudo-failure should occur (as an example).

If the pseudo fault should be generated 0 μsec after the current time, if the unit is 10 μsec, then specify "5" (hereinafter referred to as pseudo fault setting time information)) and specify the location where the pseudo fault should occur (for example, main memory 200 (pseudo fault information to be stored in the fault detection information storage area 220). 2. To specify the time, the processor 410 in the service processor section 400 arbitrarily selects and specifies the time.

Including cases where specified. For example, the specification in this case is rAJ
shall be.

Next, at the time specified by the simulated failure setting time information, the processing unit 10
The process moves on to the operation of activating the operation of collecting status information of each part of 0. In other words, pseudo failure information is received from the diagnostic control unit 140 (step 54).

The pseudo fault information is stored in the fault detection information storage area 220 in the main memory 200 (step 55).

Furthermore, upon receiving pseudo-failure setting time information (in this case, "5") from the second diagnosis control unit 140, the process moves to step 56) and a two-hour monitoring operation. Note that when the pseudo failure setting time information is rAJ, the numerical value selected by the processor 410 becomes the pseudo setting time information used for the time monitoring operation. First, it is determined whether or not the simulated failure setting time information is "0" (step 57), and if it is not r months, after a time of 10 μSee has passed (step 58)
, "1" is subtracted from the simulated fault setting time information to obtain "4" (step 59), the process moves to step 57, and this process is repeated thereafter. When the false failure setting time information reaches 10.

Step 60) instructs the diagnostic control unit 140 to stop the clock of the processing unit 100 and freeze the status information of each unit at the pseudo fault setting time.

After receiving the freezing completion report from the diagnostic control unit 440 (step 61), a pseudo failure setting flag (not shown) provided in the memory 420 is set to "1" (step 62). This flag is displayed as ``1'' only when a pseudo failure is set and a failure handling test is being performed, and is set to ``0'' in other cases, so that it can be clearly distinguished that a failure handling test is being performed. It is for the purpose of

Next, an operation is performed to collect status information of each frozen part, but this operation is the same as the operation at the time of the actual failure described above, and steps 63 to 7 are performed.
3.

Since the pseudo fault setting flag was set to "1" in step 62, the pseudo fault setting flag was rewritten to "0". (Step 76
), the process moves to the CPU initialization operation (step 77).

This is equivalent to the error detection switch circuit in the processing unit 100 corresponding to the preset pseudo failure information being set to logic "1" due to the failure and generating a failure signal. This means that status information has been created. In other words, a pseudo failure has occurred at a specified location at a specified time. In this way, the same status information as the actual occurrence of a failure is stored in the failure detection information storage area 220.

Thereafter, the failure processing can be confirmed through step 78 in the same manner as when a failure actually occurs.

In this way, in this embodiment, the status information of each part of the processing unit 100 is frozen at a specified time, this status information is stored in the error log area 210, and specified pseudo failure information is stored in the failure detection information storage area 220. We recommend that you configure the settings and perform a confirmation test for failure handling using this status information.
Unlike conventional data processing devices, it is not necessary to prepare an additional circuit for each circuit to add a pseudo failure.

In the second embodiment, only the collection of F/F state information of the error detection latch circuit was explained.

The present invention is not limited to this. for example.

It can also be applied to the case of collecting all status information of each circuit targeted for failure processing.

〔Effect of the invention〕

As described above, according to the present invention, state information is collected in the main memory, and a pseudo fault is set for information obtained by compressing and editing the information, thereby simulating faults much more effectively than conventional data processing devices. This has the effect of reducing the amount of additional hardware.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIGS. 2, 3, and 4 are flowcharts showing an example of the operation of the present invention. 100... Processing unit (CPU), ' 110... Package. 111.112,113...Circuit, 114, 11
5゜116...Error detection latch circuit, 117...
Orgate. 129.130...Gucceno, 140...Diagnosis control unit, 200...Main memory (MM), 210...Error log area. 220...Fault detection information storage area, 300...Memory access control unit, 400...Service processor unit' (SVP), 410...Processor, 420
...Memo 1. Agent (7127) ``Yousuke Goto, Physician, Figure 3, Figure 4

Claims (1)

[Claims] 1. Fault detection storage means having a processing section and a main memory, provided for each functional block constituting the processing section, detecting and storing a fault in the functional block and generating a start signal; writing means for reading out state information of the processing unit including at least the fault detection storage means and writing it into the main memory in response to the supply; and the fault in the state information written to the main memory after the writing is completed. editing means for selectively extracting and editing status information corresponding to the detection storage means and storing the editing result in the fault detection information storage means; A data processing device comprising a failure processing means for analyzing the contents of a storage means containing detected information and performing predetermined failure processing, a means for storing pseudo-failure information specified in advance in the failure detection information storage means; a signal generation activation means for generating the activation signal at a specified time to activate the writing means; and at the end of writing of the writing means activated in response to the activation signal from the signal generation activation means; 1. A data processing device comprising: activation means for inhibiting editing means and activation of the failure processing means.